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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / phy / mscc.c
blobdb50efb30df58bcacbed107bb1cf7eb2dd83ed21
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Driver for Microsemi VSC85xx PHYs
4 *
5 * Author: Nagaraju Lakkaraju
6 * License: Dual MIT/GPL
7 * Copyright (c) 2016 Microsemi Corporation
8 */
9
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/of.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
20
21 enum rgmii_rx_clock_delay {
22 RGMII_RX_CLK_DELAY_0_2_NS = 0,
23 RGMII_RX_CLK_DELAY_0_8_NS = 1,
24 RGMII_RX_CLK_DELAY_1_1_NS = 2,
25 RGMII_RX_CLK_DELAY_1_7_NS = 3,
26 RGMII_RX_CLK_DELAY_2_0_NS = 4,
27 RGMII_RX_CLK_DELAY_2_3_NS = 5,
28 RGMII_RX_CLK_DELAY_2_6_NS = 6,
29 RGMII_RX_CLK_DELAY_3_4_NS = 7
30 };
31
32 /* Microsemi VSC85xx PHY registers */
33 /* IEEE 802. Std Registers */
34 #define MSCC_PHY_BYPASS_CONTROL 18
35 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
36 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
37 #define DISABLE_POLARITY_CORR_MASK 0x0010
38 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
39
40 #define MSCC_PHY_EXT_CNTL_STATUS 22
41 #define SMI_BROADCAST_WR_EN 0x0001
42
43 #define MSCC_PHY_ERR_RX_CNT 19
44 #define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
45 #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
46 #define ERR_CNT_MASK GENMASK(7, 0)
47
48 #define MSCC_PHY_EXT_PHY_CNTL_1 23
49 #define MAC_IF_SELECTION_MASK 0x1800
50 #define MAC_IF_SELECTION_GMII 0
51 #define MAC_IF_SELECTION_RMII 1
52 #define MAC_IF_SELECTION_RGMII 2
53 #define MAC_IF_SELECTION_POS 11
54 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
55 #define VSC8584_MAC_IF_SELECTION_SGMII 0
56 #define VSC8584_MAC_IF_SELECTION_1000BASEX 1
57 #define VSC8584_MAC_IF_SELECTION_POS 12
58 #define FAR_END_LOOPBACK_MODE_MASK 0x0008
59 #define MEDIA_OP_MODE_MASK 0x0700
60 #define MEDIA_OP_MODE_COPPER 0
61 #define MEDIA_OP_MODE_SERDES 1
62 #define MEDIA_OP_MODE_1000BASEX 2
63 #define MEDIA_OP_MODE_100BASEFX 3
64 #define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
65 #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
66 #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
67 #define MEDIA_OP_MODE_POS 8
68
69 #define MSCC_PHY_EXT_PHY_CNTL_2 24
70
71 #define MII_VSC85XX_INT_MASK 25
72 #define MII_VSC85XX_INT_MASK_MASK 0xa000
73 #define MII_VSC85XX_INT_MASK_WOL 0x0040
74 #define MII_VSC85XX_INT_STATUS 26
75
76 #define MSCC_PHY_WOL_MAC_CONTROL 27
77 #define EDGE_RATE_CNTL_POS 5
78 #define EDGE_RATE_CNTL_MASK 0x00E0
79
80 #define MSCC_PHY_DEV_AUX_CNTL 28
81 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
82
83 #define MSCC_PHY_LED_MODE_SEL 29
84 #define LED_MODE_SEL_POS(x) ((x) * 4)
85 #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
86 #define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
87
88 #define MSCC_EXT_PAGE_ACCESS 31
89 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
90 #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
91 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
92 #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
93 #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
94 /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
95 * in the same package.
96 */
97 #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
98 #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
99 #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
100
101 /* Extended Page 1 Registers */
102 #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
103 #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
104
105 #define MSCC_PHY_EXT_MODE_CNTL 19
106 #define FORCE_MDI_CROSSOVER_MASK 0x000C
107 #define FORCE_MDI_CROSSOVER_MDIX 0x000C
108 #define FORCE_MDI_CROSSOVER_MDI 0x0008
109
110 #define MSCC_PHY_ACTIPHY_CNTL 20
111 #define PHY_ADDR_REVERSED 0x0200
112 #define DOWNSHIFT_CNTL_MASK 0x001C
113 #define DOWNSHIFT_EN 0x0010
114 #define DOWNSHIFT_CNTL_POS 2
115
116 #define MSCC_PHY_EXT_PHY_CNTL_4 23
117 #define PHY_CNTL_4_ADDR_POS 11
118
119 #define MSCC_PHY_VERIPHY_CNTL_2 25
120
121 #define MSCC_PHY_VERIPHY_CNTL_3 26
122
123 /* Extended Page 2 Registers */
124 #define MSCC_PHY_CU_PMD_TX_CNTL 16
125
126 #define MSCC_PHY_RGMII_CNTL 20
127 #define RGMII_RX_CLK_DELAY_MASK 0x0070
128 #define RGMII_RX_CLK_DELAY_POS 4
129
130 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
131 #define MSCC_PHY_WOL_MID_MAC_ADDR 22
132 #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
133 #define MSCC_PHY_WOL_LOWER_PASSWD 24
134 #define MSCC_PHY_WOL_MID_PASSWD 25
135 #define MSCC_PHY_WOL_UPPER_PASSWD 26
136
137 #define MSCC_PHY_WOL_MAC_CONTROL 27
138 #define SECURE_ON_ENABLE 0x8000
139 #define SECURE_ON_PASSWD_LEN_4 0x4000
140
141 /* Extended Page 3 Registers */
142 #define MSCC_PHY_SERDES_TX_VALID_CNT 21
143 #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
144 #define MSCC_PHY_SERDES_RX_VALID_CNT 28
145 #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
146
147 /* Extended page GPIO Registers */
148 #define MSCC_DW8051_CNTL_STATUS 0
149 #define MICRO_NSOFT_RESET 0x8000
150 #define RUN_FROM_INT_ROM 0x4000
151 #define AUTOINC_ADDR 0x2000
152 #define PATCH_RAM_CLK 0x1000
153 #define MICRO_PATCH_EN 0x0080
154 #define DW8051_CLK_EN 0x0010
155 #define MICRO_CLK_EN 0x0008
156 #define MICRO_CLK_DIVIDE(x) ((x) >> 1)
157 #define MSCC_DW8051_VLD_MASK 0xf1ff
158
159 /* x Address in range 1-4 */
160 #define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
161 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
162 #define MSCC_INT_MEM_ADDR 11
163
164 #define MSCC_INT_MEM_CNTL 12
165 #define READ_SFR 0x6000
166 #define READ_PRAM 0x4000
167 #define READ_ROM 0x2000
168 #define READ_RAM 0x0000
169 #define INT_MEM_WRITE_EN 0x1000
170 #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
171 #define INT_MEM_DATA_M 0x00ff
172 #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
173
174 #define MSCC_PHY_PROC_CMD 18
175 #define PROC_CMD_NCOMPLETED 0x8000
176 #define PROC_CMD_FAILED 0x4000
177 #define PROC_CMD_SGMII_PORT(x) ((x) << 8)
178 #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
179 #define PROC_CMD_QSGMII_PORT 0x0c00
180 #define PROC_CMD_RST_CONF_PORT 0x0080
181 #define PROC_CMD_RECONF_PORT 0x0000
182 #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
183 #define PROC_CMD_WRITE 0x0040
184 #define PROC_CMD_READ 0x0000
185 #define PROC_CMD_FIBER_DISABLE 0x0020
186 #define PROC_CMD_FIBER_100BASE_FX 0x0010
187 #define PROC_CMD_FIBER_1000BASE_X 0x0000
188 #define PROC_CMD_SGMII_MAC 0x0030
189 #define PROC_CMD_QSGMII_MAC 0x0020
190 #define PROC_CMD_NO_MAC_CONF 0x0000
191 #define PROC_CMD_1588_DEFAULT_INIT 0x0010
192 #define PROC_CMD_NOP 0x000f
193 #define PROC_CMD_PHY_INIT 0x000a
194 #define PROC_CMD_CRC16 0x0008
195 #define PROC_CMD_FIBER_MEDIA_CONF 0x0001
196 #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
197 #define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
198
199 #define MSCC_PHY_MAC_CFG_FASTLINK 19
200 #define MAC_CFG_MASK 0xc000
201 #define MAC_CFG_SGMII 0x0000
202 #define MAC_CFG_QSGMII 0x4000
203
204 /* Test page Registers */
205 #define MSCC_PHY_TEST_PAGE_5 5
206 #define MSCC_PHY_TEST_PAGE_8 8
207 #define MSCC_PHY_TEST_PAGE_9 9
208 #define MSCC_PHY_TEST_PAGE_20 20
209 #define MSCC_PHY_TEST_PAGE_24 24
210
211 /* Token ring page Registers */
212 #define MSCC_PHY_TR_CNTL 16
213 #define TR_WRITE 0x8000
214 #define TR_ADDR(x) (0x7fff & (x))
215 #define MSCC_PHY_TR_LSB 17
216 #define MSCC_PHY_TR_MSB 18
217
218 /* Microsemi PHY ID's */
219 #define PHY_ID_VSC8530 0x00070560
220 #define PHY_ID_VSC8531 0x00070570
221 #define PHY_ID_VSC8540 0x00070760
222 #define PHY_ID_VSC8541 0x00070770
223 #define PHY_ID_VSC8574 0x000704a0
224 #define PHY_ID_VSC8584 0x000707c0
225
226 #define MSCC_VDDMAC_1500 1500
227 #define MSCC_VDDMAC_1800 1800
228 #define MSCC_VDDMAC_2500 2500
229 #define MSCC_VDDMAC_3300 3300
230
231 #define DOWNSHIFT_COUNT_MAX 5
232
233 #define MAX_LEDS 4
234
235 #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
236 BIT(VSC8531_LINK_1000_ACTIVITY) | \
237 BIT(VSC8531_LINK_100_ACTIVITY) | \
238 BIT(VSC8531_LINK_10_ACTIVITY) | \
239 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
240 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
241 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
242 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
243 BIT(VSC8531_DUPLEX_COLLISION) | \
244 BIT(VSC8531_COLLISION) | \
245 BIT(VSC8531_ACTIVITY) | \
246 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
247 BIT(VSC8531_AUTONEG_FAULT) | \
248 BIT(VSC8531_SERIAL_MODE) | \
249 BIT(VSC8531_FORCE_LED_OFF) | \
250 BIT(VSC8531_FORCE_LED_ON))
251
252 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
253 BIT(VSC8531_LINK_1000_ACTIVITY) | \
254 BIT(VSC8531_LINK_100_ACTIVITY) | \
255 BIT(VSC8531_LINK_10_ACTIVITY) | \
256 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
257 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
258 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
259 BIT(VSC8531_DUPLEX_COLLISION) | \
260 BIT(VSC8531_COLLISION) | \
261 BIT(VSC8531_ACTIVITY) | \
262 BIT(VSC8531_AUTONEG_FAULT) | \
263 BIT(VSC8531_SERIAL_MODE) | \
264 BIT(VSC8531_FORCE_LED_OFF) | \
265 BIT(VSC8531_FORCE_LED_ON))
266
267 #define MSCC_VSC8584_REVB_INT8051_FW "mscc_vsc8584_revb_int8051_fb48.bin"
268 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
269 #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
270
271 #define MSCC_VSC8574_REVB_INT8051_FW "mscc_vsc8574_revb_int8051_29e8.bin"
272 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
273 #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
274
275 #define VSC8584_REVB 0x0001
276 #define MSCC_DEV_REV_MASK GENMASK(3, 0)
277
278 struct reg_val {
279 u16 reg;
280 u32 val;
281 };
282
283 struct vsc85xx_hw_stat {
284 const char *string;
285 u8 reg;
286 u16 page;
287 u16 mask;
288 };
289
290 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
291 {
292 .string = "phy_receive_errors",
293 .reg = MSCC_PHY_ERR_RX_CNT,
294 .page = MSCC_PHY_PAGE_STANDARD,
295 .mask = ERR_CNT_MASK,
296 }, {
297 .string = "phy_false_carrier",
298 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
299 .page = MSCC_PHY_PAGE_STANDARD,
300 .mask = ERR_CNT_MASK,
301 }, {
302 .string = "phy_cu_media_link_disconnect",
303 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
304 .page = MSCC_PHY_PAGE_STANDARD,
305 .mask = ERR_CNT_MASK,
306 }, {
307 .string = "phy_cu_media_crc_good_count",
308 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
309 .page = MSCC_PHY_PAGE_EXTENDED,
310 .mask = VALID_CRC_CNT_CRC_MASK,
311 }, {
312 .string = "phy_cu_media_crc_error_count",
313 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
314 .page = MSCC_PHY_PAGE_EXTENDED,
315 .mask = ERR_CNT_MASK,
316 },
317 };
318
319 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
320 {
321 .string = "phy_receive_errors",
322 .reg = MSCC_PHY_ERR_RX_CNT,
323 .page = MSCC_PHY_PAGE_STANDARD,
324 .mask = ERR_CNT_MASK,
325 }, {
326 .string = "phy_false_carrier",
327 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
328 .page = MSCC_PHY_PAGE_STANDARD,
329 .mask = ERR_CNT_MASK,
330 }, {
331 .string = "phy_cu_media_link_disconnect",
332 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
333 .page = MSCC_PHY_PAGE_STANDARD,
334 .mask = ERR_CNT_MASK,
335 }, {
336 .string = "phy_cu_media_crc_good_count",
337 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
338 .page = MSCC_PHY_PAGE_EXTENDED,
339 .mask = VALID_CRC_CNT_CRC_MASK,
340 }, {
341 .string = "phy_cu_media_crc_error_count",
342 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
343 .page = MSCC_PHY_PAGE_EXTENDED,
344 .mask = ERR_CNT_MASK,
345 }, {
346 .string = "phy_serdes_tx_good_pkt_count",
347 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
348 .page = MSCC_PHY_PAGE_EXTENDED_3,
349 .mask = VALID_CRC_CNT_CRC_MASK,
350 }, {
351 .string = "phy_serdes_tx_bad_crc_count",
352 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
353 .page = MSCC_PHY_PAGE_EXTENDED_3,
354 .mask = ERR_CNT_MASK,
355 }, {
356 .string = "phy_serdes_rx_good_pkt_count",
357 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
358 .page = MSCC_PHY_PAGE_EXTENDED_3,
359 .mask = VALID_CRC_CNT_CRC_MASK,
360 }, {
361 .string = "phy_serdes_rx_bad_crc_count",
362 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
363 .page = MSCC_PHY_PAGE_EXTENDED_3,
364 .mask = ERR_CNT_MASK,
365 },
366 };
367
368 struct vsc8531_private {
369 int rate_magic;
370 u16 supp_led_modes;
371 u32 leds_mode[MAX_LEDS];
372 u8 nleds;
373 const struct vsc85xx_hw_stat *hw_stats;
374 u64 *stats;
375 int nstats;
376 bool pkg_init;
377 /* For multiple port PHYs; the MDIO address of the base PHY in the
378 * package.
379 */
380 unsigned int base_addr;
381 };
382
383 #ifdef CONFIG_OF_MDIO
384 struct vsc8531_edge_rate_table {
385 u32 vddmac;
386 u32 slowdown[8];
387 };
388
389 static const struct vsc8531_edge_rate_table edge_table[] = {
390 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
391 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
392 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
393 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
394 };
395 #endif /* CONFIG_OF_MDIO */
396
397 static int vsc85xx_phy_read_page(struct phy_device *phydev)
398 {
399 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
400 }
401
402 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
403 {
404 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
405 }
406
407 static int vsc85xx_get_sset_count(struct phy_device *phydev)
408 {
409 struct vsc8531_private *priv = phydev->priv;
410
411 if (!priv)
412 return 0;
413
414 return priv->nstats;
415 }
416
417 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
418 {
419 struct vsc8531_private *priv = phydev->priv;
420 int i;
421
422 if (!priv)
423 return;
424
425 for (i = 0; i < priv->nstats; i++)
426 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
427 ETH_GSTRING_LEN);
428 }
429
430 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
431 {
432 struct vsc8531_private *priv = phydev->priv;
433 int val;
434
435 val = phy_read_paged(phydev, priv->hw_stats[i].page,
436 priv->hw_stats[i].reg);
437 if (val < 0)
438 return U64_MAX;
439
440 val = val & priv->hw_stats[i].mask;
441 priv->stats[i] += val;
442
443 return priv->stats[i];
444 }
445
446 static void vsc85xx_get_stats(struct phy_device *phydev,
447 struct ethtool_stats *stats, u64 *data)
448 {
449 struct vsc8531_private *priv = phydev->priv;
450 int i;
451
452 if (!priv)
453 return;
454
455 for (i = 0; i < priv->nstats; i++)
456 data[i] = vsc85xx_get_stat(phydev, i);
457 }
458
459 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
460 u8 led_num,
461 u8 mode)
462 {
463 int rc;
464 u16 reg_val;
465
466 mutex_lock(&phydev->lock);
467 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
468 reg_val &= ~LED_MODE_SEL_MASK(led_num);
469 reg_val |= LED_MODE_SEL(led_num, (u16)mode);
470 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
471 mutex_unlock(&phydev->lock);
472
473 return rc;
474 }
475
476 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
477 {
478 u16 reg_val;
479
480 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
481 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
482 *mdix = ETH_TP_MDI_X;
483 else
484 *mdix = ETH_TP_MDI;
485
486 return 0;
487 }
488
489 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
490 {
491 int rc;
492 u16 reg_val;
493
494 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
495 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
496 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
497 DISABLE_POLARITY_CORR_MASK |
498 DISABLE_HP_AUTO_MDIX_MASK);
499 } else {
500 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
501 DISABLE_POLARITY_CORR_MASK |
502 DISABLE_HP_AUTO_MDIX_MASK);
503 }
504 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
505 if (rc)
506 return rc;
507
508 reg_val = 0;
509
510 if (mdix == ETH_TP_MDI)
511 reg_val = FORCE_MDI_CROSSOVER_MDI;
512 else if (mdix == ETH_TP_MDI_X)
513 reg_val = FORCE_MDI_CROSSOVER_MDIX;
514
515 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
516 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
517 reg_val);
518 if (rc < 0)
519 return rc;
520
521 return genphy_restart_aneg(phydev);
522 }
523
524 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
525 {
526 int reg_val;
527
528 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
529 MSCC_PHY_ACTIPHY_CNTL);
530 if (reg_val < 0)
531 return reg_val;
532
533 reg_val &= DOWNSHIFT_CNTL_MASK;
534 if (!(reg_val & DOWNSHIFT_EN))
535 *count = DOWNSHIFT_DEV_DISABLE;
536 else
537 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
538
539 return 0;
540 }
541
542 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
543 {
544 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
545 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
546 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
547 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
548 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
549 return -ERANGE;
550 } else if (count) {
551 /* Downshift count is either 2,3,4 or 5 */
552 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
553 }
554
555 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
556 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
557 count);
558 }
559
560 static int vsc85xx_wol_set(struct phy_device *phydev,
561 struct ethtool_wolinfo *wol)
562 {
563 int rc;
564 u16 reg_val;
565 u8 i;
566 u16 pwd[3] = {0, 0, 0};
567 struct ethtool_wolinfo *wol_conf = wol;
568 u8 *mac_addr = phydev->attached_dev->dev_addr;
569
570 mutex_lock(&phydev->lock);
571 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
572 if (rc < 0) {
573 rc = phy_restore_page(phydev, rc, rc);
574 goto out_unlock;
575 }
576
577 if (wol->wolopts & WAKE_MAGIC) {
578 /* Store the device address for the magic packet */
579 for (i = 0; i < ARRAY_SIZE(pwd); i++)
580 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
581 mac_addr[5 - i * 2];
582 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
583 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
584 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
585 } else {
586 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
587 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
588 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
589 }
590
591 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
592 for (i = 0; i < ARRAY_SIZE(pwd); i++)
593 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
594 wol_conf->sopass[5 - i * 2];
595 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
596 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
597 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
598 } else {
599 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
600 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
601 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
602 }
603
604 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
605 if (wol_conf->wolopts & WAKE_MAGICSECURE)
606 reg_val |= SECURE_ON_ENABLE;
607 else
608 reg_val &= ~SECURE_ON_ENABLE;
609 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
610
611 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
612 if (rc < 0)
613 goto out_unlock;
614
615 if (wol->wolopts & WAKE_MAGIC) {
616 /* Enable the WOL interrupt */
617 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
618 reg_val |= MII_VSC85XX_INT_MASK_WOL;
619 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
620 if (rc)
621 goto out_unlock;
622 } else {
623 /* Disable the WOL interrupt */
624 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
625 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
626 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
627 if (rc)
628 goto out_unlock;
629 }
630 /* Clear WOL iterrupt status */
631 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
632
633 out_unlock:
634 mutex_unlock(&phydev->lock);
635
636 return rc;
637 }
638
639 static void vsc85xx_wol_get(struct phy_device *phydev,
640 struct ethtool_wolinfo *wol)
641 {
642 int rc;
643 u16 reg_val;
644 u8 i;
645 u16 pwd[3] = {0, 0, 0};
646 struct ethtool_wolinfo *wol_conf = wol;
647
648 mutex_lock(&phydev->lock);
649 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
650 if (rc < 0)
651 goto out_unlock;
652
653 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
654 if (reg_val & SECURE_ON_ENABLE)
655 wol_conf->wolopts |= WAKE_MAGICSECURE;
656 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
657 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
658 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
659 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
660 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
661 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
662 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
663 >> 8;
664 }
665 }
666
667 out_unlock:
668 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
669 mutex_unlock(&phydev->lock);
670 }
671
672 #ifdef CONFIG_OF_MDIO
673 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
674 {
675 u32 vdd, sd;
676 int i, j;
677 struct device *dev = &phydev->mdio.dev;
678 struct device_node *of_node = dev->of_node;
679 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
680
681 if (!of_node)
682 return -ENODEV;
683
684 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
685 vdd = MSCC_VDDMAC_3300;
686
687 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
688 sd = 0;
689
690 for (i = 0; i < ARRAY_SIZE(edge_table); i++)
691 if (edge_table[i].vddmac == vdd)
692 for (j = 0; j < sd_array_size; j++)
693 if (edge_table[i].slowdown[j] == sd)
694 return (sd_array_size - j - 1);
695
696 return -EINVAL;
697 }
698
699 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
700 char *led,
701 u32 default_mode)
702 {
703 struct vsc8531_private *priv = phydev->priv;
704 struct device *dev = &phydev->mdio.dev;
705 struct device_node *of_node = dev->of_node;
706 u32 led_mode;
707 int err;
708
709 if (!of_node)
710 return -ENODEV;
711
712 led_mode = default_mode;
713 err = of_property_read_u32(of_node, led, &led_mode);
714 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
715 phydev_err(phydev, "DT %s invalid\n", led);
716 return -EINVAL;
717 }
718
719 return led_mode;
720 }
721
722 #else
723 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
724 {
725 return 0;
726 }
727
728 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
729 char *led,
730 u8 default_mode)
731 {
732 return default_mode;
733 }
734 #endif /* CONFIG_OF_MDIO */
735
736 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
737 u32 *default_mode)
738 {
739 struct vsc8531_private *priv = phydev->priv;
740 char led_dt_prop[28];
741 int i, ret;
742
743 for (i = 0; i < priv->nleds; i++) {
744 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
745 if (ret < 0)
746 return ret;
747
748 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
749 default_mode[i]);
750 if (ret < 0)
751 return ret;
752 priv->leds_mode[i] = ret;
753 }
754
755 return 0;
756 }
757
758 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
759 {
760 int rc;
761
762 mutex_lock(&phydev->lock);
763 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
764 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
765 edge_rate << EDGE_RATE_CNTL_POS);
766 mutex_unlock(&phydev->lock);
767
768 return rc;
769 }
770
771 static int vsc85xx_mac_if_set(struct phy_device *phydev,
772 phy_interface_t interface)
773 {
774 int rc;
775 u16 reg_val;
776
777 mutex_lock(&phydev->lock);
778 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
779 reg_val &= ~(MAC_IF_SELECTION_MASK);
780 switch (interface) {
781 case PHY_INTERFACE_MODE_RGMII:
782 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
783 break;
784 case PHY_INTERFACE_MODE_RMII:
785 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
786 break;
787 case PHY_INTERFACE_MODE_MII:
788 case PHY_INTERFACE_MODE_GMII:
789 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
790 break;
791 default:
792 rc = -EINVAL;
793 goto out_unlock;
794 }
795 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
796 if (rc)
797 goto out_unlock;
798
799 rc = genphy_soft_reset(phydev);
800
801 out_unlock:
802 mutex_unlock(&phydev->lock);
803
804 return rc;
805 }
806
807 static int vsc85xx_default_config(struct phy_device *phydev)
808 {
809 int rc;
810 u16 reg_val;
811
812 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
813 mutex_lock(&phydev->lock);
814
815 reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
816
817 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
818 MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
819 reg_val);
820
821 mutex_unlock(&phydev->lock);
822
823 return rc;
824 }
825
826 static int vsc85xx_get_tunable(struct phy_device *phydev,
827 struct ethtool_tunable *tuna, void *data)
828 {
829 switch (tuna->id) {
830 case ETHTOOL_PHY_DOWNSHIFT:
831 return vsc85xx_downshift_get(phydev, (u8 *)data);
832 default:
833 return -EINVAL;
834 }
835 }
836
837 static int vsc85xx_set_tunable(struct phy_device *phydev,
838 struct ethtool_tunable *tuna,
839 const void *data)
840 {
841 switch (tuna->id) {
842 case ETHTOOL_PHY_DOWNSHIFT:
843 return vsc85xx_downshift_set(phydev, *(u8 *)data);
844 default:
845 return -EINVAL;
846 }
847 }
848
849 /* mdiobus lock should be locked when using this function */
850 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
851 {
852 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
853 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
854 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
855 }
856
857 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
858 {
859 int rc;
860 const struct reg_val init_seq[] = {
861 {0x0f90, 0x00688980},
862 {0x0696, 0x00000003},
863 {0x07fa, 0x0050100f},
864 {0x1686, 0x00000004},
865 };
866 unsigned int i;
867 int oldpage;
868
869 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
870 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
871 SMI_BROADCAST_WR_EN);
872 if (rc < 0)
873 return rc;
874 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
875 MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
876 if (rc < 0)
877 return rc;
878 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
879 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
880 if (rc < 0)
881 return rc;
882 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
883 MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000);
884 if (rc < 0)
885 return rc;
886
887 mutex_lock(&phydev->lock);
888 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
889 if (oldpage < 0)
890 goto out_unlock;
891
892 for (i = 0; i < ARRAY_SIZE(init_seq); i++)
893 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
894
895 out_unlock:
896 oldpage = phy_restore_page(phydev, oldpage, oldpage);
897 mutex_unlock(&phydev->lock);
898
899 return oldpage;
900 }
901
902 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
903 {
904 const struct reg_val init_eee[] = {
905 {0x0f82, 0x0012b00a},
906 {0x1686, 0x00000004},
907 {0x168c, 0x00d2c46f},
908 {0x17a2, 0x00000620},
909 {0x16a0, 0x00eeffdd},
910 {0x16a6, 0x00071448},
911 {0x16a4, 0x0013132f},
912 {0x16a8, 0x00000000},
913 {0x0ffc, 0x00c0a028},
914 {0x0fe8, 0x0091b06c},
915 {0x0fea, 0x00041600},
916 {0x0f80, 0x00000af4},
917 {0x0fec, 0x00901809},
918 {0x0fee, 0x0000a6a1},
919 {0x0ffe, 0x00b01007},
920 {0x16b0, 0x00eeff00},
921 {0x16b2, 0x00007000},
922 {0x16b4, 0x00000814},
923 };
924 unsigned int i;
925 int oldpage;
926
927 mutex_lock(&phydev->lock);
928 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
929 if (oldpage < 0)
930 goto out_unlock;
931
932 for (i = 0; i < ARRAY_SIZE(init_eee); i++)
933 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
934
935 out_unlock:
936 oldpage = phy_restore_page(phydev, oldpage, oldpage);
937 mutex_unlock(&phydev->lock);
938
939 return oldpage;
940 }
941
942 /* phydev->bus->mdio_lock should be locked when using this function */
943 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
944 {
945 struct vsc8531_private *priv = phydev->priv;
946
947 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
948 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
949 dump_stack();
950 }
951
952 return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val);
953 }
954
955 /* phydev->bus->mdio_lock should be locked when using this function */
956 static int phy_base_read(struct phy_device *phydev, u32 regnum)
957 {
958 struct vsc8531_private *priv = phydev->priv;
959
960 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
961 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
962 dump_stack();
963 }
964
965 return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum);
966 }
967
968 /* bus->mdio_lock should be locked when using this function */
969 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
970 {
971 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
972 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
973 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
974 }
975
976 /* bus->mdio_lock should be locked when using this function */
977 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
978 {
979 unsigned long deadline;
980 u16 reg_val;
981
982 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
983 MSCC_PHY_PAGE_EXTENDED_GPIO);
984
985 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
986
987 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
988 do {
989 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
990 } while (time_before(jiffies, deadline) &&
991 (reg_val & PROC_CMD_NCOMPLETED) &&
992 !(reg_val & PROC_CMD_FAILED));
993
994 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
995
996 if (reg_val & PROC_CMD_FAILED)
997 return -EIO;
998
999 if (reg_val & PROC_CMD_NCOMPLETED)
1000 return -ETIMEDOUT;
1001
1002 return 0;
1003 }
1004
1005 /* bus->mdio_lock should be locked when using this function */
1006 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
1007 bool patch_en)
1008 {
1009 u32 enable, release;
1010
1011 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1012 MSCC_PHY_PAGE_EXTENDED_GPIO);
1013
1014 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
1015 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
1016 MICRO_CLK_EN;
1017
1018 if (patch_en) {
1019 enable |= MICRO_PATCH_EN;
1020 release |= MICRO_PATCH_EN;
1021
1022 /* Clear all patches */
1023 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1024 }
1025
1026 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
1027 * override and addr. auto-incr; operate at 125 MHz
1028 */
1029 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
1030 /* Release 8051 Micro SW reset */
1031 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
1032
1033 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1034
1035 return 0;
1036 }
1037
1038 /* bus->mdio_lock should be locked when using this function */
1039 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
1040 {
1041 int ret;
1042 u16 reg;
1043
1044 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1045 if (ret)
1046 return ret;
1047
1048 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1049 MSCC_PHY_PAGE_EXTENDED_GPIO);
1050
1051 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1052 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1053 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1054
1055 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
1056 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
1057
1058 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1059 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
1060 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1061
1062 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
1063
1064 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1065 reg &= ~MICRO_NSOFT_RESET;
1066 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
1067
1068 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
1069 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
1070 PROC_CMD_READ);
1071
1072 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1073 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1074 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1075
1076 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1077
1078 return 0;
1079 }
1080
1081 /* bus->mdio_lock should be locked when using this function */
1082 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
1083 u16 *crc)
1084 {
1085 int ret;
1086
1087 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1088
1089 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
1090 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
1091
1092 /* Start Micro command */
1093 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
1094 if (ret)
1095 goto out;
1096
1097 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1098
1099 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
1100
1101 out:
1102 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1103
1104 return ret;
1105 }
1106
1107 /* bus->mdio_lock should be locked when using this function */
1108 static int vsc8584_patch_fw(struct phy_device *phydev,
1109 const struct firmware *fw)
1110 {
1111 int i, ret;
1112
1113 ret = vsc8584_micro_assert_reset(phydev);
1114 if (ret) {
1115 dev_err(&phydev->mdio.dev,
1116 "%s: failed to assert reset of micro\n", __func__);
1117 return ret;
1118 }
1119
1120 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1121 MSCC_PHY_PAGE_EXTENDED_GPIO);
1122
1123 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
1124 * Disable the 8051 Micro clock
1125 */
1126 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
1127 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
1128 MICRO_CLK_DIVIDE(2));
1129 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
1130 INT_MEM_DATA(2));
1131 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
1132
1133 for (i = 0; i < fw->size; i++)
1134 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
1135 INT_MEM_WRITE_EN | fw->data[i]);
1136
1137 /* Clear internal memory access */
1138 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1139
1140 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1141
1142 return 0;
1143 }
1144
1145 /* bus->mdio_lock should be locked when using this function */
1146 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1147 {
1148 u16 reg;
1149 bool ret;
1150
1151 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1152 MSCC_PHY_PAGE_EXTENDED_GPIO);
1153
1154 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1155 if (reg != 0x3eb7) {
1156 ret = false;
1157 goto out;
1158 }
1159
1160 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1161 if (reg != 0x4012) {
1162 ret = false;
1163 goto out;
1164 }
1165
1166 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1167 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1168 ret = false;
1169 goto out;
1170 }
1171
1172 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1173 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
1174 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1175 ret = false;
1176 goto out;
1177 }
1178
1179 ret = true;
1180 out:
1181 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1182
1183 return ret;
1184 }
1185
1186 /* bus->mdio_lock should be locked when using this function */
1187 static int vsc8574_config_pre_init(struct phy_device *phydev)
1188 {
1189 const struct reg_val pre_init1[] = {
1190 {0x0fae, 0x000401bd},
1191 {0x0fac, 0x000f000f},
1192 {0x17a0, 0x00a0f147},
1193 {0x0fe4, 0x00052f54},
1194 {0x1792, 0x0027303d},
1195 {0x07fe, 0x00000704},
1196 {0x0fe0, 0x00060150},
1197 {0x0f82, 0x0012b00a},
1198 {0x0f80, 0x00000d74},
1199 {0x02e0, 0x00000012},
1200 {0x03a2, 0x00050208},
1201 {0x03b2, 0x00009186},
1202 {0x0fb0, 0x000e3700},
1203 {0x1688, 0x00049f81},
1204 {0x0fd2, 0x0000ffff},
1205 {0x168a, 0x00039fa2},
1206 {0x1690, 0x0020640b},
1207 {0x0258, 0x00002220},
1208 {0x025a, 0x00002a20},
1209 {0x025c, 0x00003060},
1210 {0x025e, 0x00003fa0},
1211 {0x03a6, 0x0000e0f0},
1212 {0x0f92, 0x00001489},
1213 {0x16a2, 0x00007000},
1214 {0x16a6, 0x00071448},
1215 {0x16a0, 0x00eeffdd},
1216 {0x0fe8, 0x0091b06c},
1217 {0x0fea, 0x00041600},
1218 {0x16b0, 0x00eeff00},
1219 {0x16b2, 0x00007000},
1220 {0x16b4, 0x00000814},
1221 {0x0f90, 0x00688980},
1222 {0x03a4, 0x0000d8f0},
1223 {0x0fc0, 0x00000400},
1224 {0x07fa, 0x0050100f},
1225 {0x0796, 0x00000003},
1226 {0x07f8, 0x00c3ff98},
1227 {0x0fa4, 0x0018292a},
1228 {0x168c, 0x00d2c46f},
1229 {0x17a2, 0x00000620},
1230 {0x16a4, 0x0013132f},
1231 {0x16a8, 0x00000000},
1232 {0x0ffc, 0x00c0a028},
1233 {0x0fec, 0x00901c09},
1234 {0x0fee, 0x0004a6a1},
1235 {0x0ffe, 0x00b01807},
1236 };
1237 const struct reg_val pre_init2[] = {
1238 {0x0486, 0x0008a518},
1239 {0x0488, 0x006dc696},
1240 {0x048a, 0x00000912},
1241 {0x048e, 0x00000db6},
1242 {0x049c, 0x00596596},
1243 {0x049e, 0x00000514},
1244 {0x04a2, 0x00410280},
1245 {0x04a4, 0x00000000},
1246 {0x04a6, 0x00000000},
1247 {0x04a8, 0x00000000},
1248 {0x04aa, 0x00000000},
1249 {0x04ae, 0x007df7dd},
1250 {0x04b0, 0x006d95d4},
1251 {0x04b2, 0x00492410},
1252 };
1253 struct device *dev = &phydev->mdio.dev;
1254 const struct firmware *fw;
1255 unsigned int i;
1256 u16 crc, reg;
1257 bool serdes_init;
1258 int ret;
1259
1260 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1261
1262 /* all writes below are broadcasted to all PHYs in the same package */
1263 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1264 reg |= SMI_BROADCAST_WR_EN;
1265 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1266
1267 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1268
1269 /* The below register writes are tweaking analog and electrical
1270 * configuration that were determined through characterization by PHY
1271 * engineers. These don't mean anything more than "these are the best
1272 * values".
1273 */
1274 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1275
1276 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1277
1278 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1279 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1280 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1281 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1282
1283 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1284 reg |= 0x8000;
1285 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1286
1287 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1288
1289 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1290 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1291
1292 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1293
1294 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1295
1296 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1297
1298 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1299 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1300
1301 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1302
1303 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1304 reg &= ~0x8000;
1305 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1306
1307 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1308
1309 /* end of write broadcasting */
1310 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1311 reg &= ~SMI_BROADCAST_WR_EN;
1312 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1313
1314 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1315 if (ret) {
1316 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1317 MSCC_VSC8574_REVB_INT8051_FW, ret);
1318 return ret;
1319 }
1320
1321 /* Add one byte to size for the one added by the patch_fw function */
1322 ret = vsc8584_get_fw_crc(phydev,
1323 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1324 fw->size + 1, &crc);
1325 if (ret)
1326 goto out;
1327
1328 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1329 serdes_init = vsc8574_is_serdes_init(phydev);
1330
1331 if (!serdes_init) {
1332 ret = vsc8584_micro_assert_reset(phydev);
1333 if (ret) {
1334 dev_err(dev,
1335 "%s: failed to assert reset of micro\n",
1336 __func__);
1337 goto out;
1338 }
1339 }
1340 } else {
1341 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1342
1343 serdes_init = false;
1344
1345 if (vsc8584_patch_fw(phydev, fw))
1346 dev_warn(dev,
1347 "failed to patch FW, expect non-optimal device\n");
1348 }
1349
1350 if (!serdes_init) {
1351 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1352 MSCC_PHY_PAGE_EXTENDED_GPIO);
1353
1354 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1355 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1356 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1357 EN_PATCH_RAM_TRAP_ADDR(1));
1358
1359 vsc8584_micro_deassert_reset(phydev, false);
1360
1361 /* Add one byte to size for the one added by the patch_fw
1362 * function
1363 */
1364 ret = vsc8584_get_fw_crc(phydev,
1365 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1366 fw->size + 1, &crc);
1367 if (ret)
1368 goto out;
1369
1370 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1371 dev_warn(dev,
1372 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1373 }
1374
1375 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1376 MSCC_PHY_PAGE_EXTENDED_GPIO);
1377
1378 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1379 PROC_CMD_PHY_INIT);
1380
1381 out:
1382 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1383
1384 release_firmware(fw);
1385
1386 return ret;
1387 }
1388
1389 /* bus->mdio_lock should be locked when using this function */
1390 static int vsc8584_config_pre_init(struct phy_device *phydev)
1391 {
1392 const struct reg_val pre_init1[] = {
1393 {0x07fa, 0x0050100f},
1394 {0x1688, 0x00049f81},
1395 {0x0f90, 0x00688980},
1396 {0x03a4, 0x0000d8f0},
1397 {0x0fc0, 0x00000400},
1398 {0x0f82, 0x0012b002},
1399 {0x1686, 0x00000004},
1400 {0x168c, 0x00d2c46f},
1401 {0x17a2, 0x00000620},
1402 {0x16a0, 0x00eeffdd},
1403 {0x16a6, 0x00071448},
1404 {0x16a4, 0x0013132f},
1405 {0x16a8, 0x00000000},
1406 {0x0ffc, 0x00c0a028},
1407 {0x0fe8, 0x0091b06c},
1408 {0x0fea, 0x00041600},
1409 {0x0f80, 0x00fffaff},
1410 {0x0fec, 0x00901809},
1411 {0x0ffe, 0x00b01007},
1412 {0x16b0, 0x00eeff00},
1413 {0x16b2, 0x00007000},
1414 {0x16b4, 0x00000814},
1415 };
1416 const struct reg_val pre_init2[] = {
1417 {0x0486, 0x0008a518},
1418 {0x0488, 0x006dc696},
1419 {0x048a, 0x00000912},
1420 };
1421 const struct firmware *fw;
1422 struct device *dev = &phydev->mdio.dev;
1423 unsigned int i;
1424 u16 crc, reg;
1425 int ret;
1426
1427 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1428
1429 /* all writes below are broadcasted to all PHYs in the same package */
1430 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1431 reg |= SMI_BROADCAST_WR_EN;
1432 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1433
1434 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1435
1436 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1437 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1438 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1439
1440 /* The below register writes are tweaking analog and electrical
1441 * configuration that were determined through characterization by PHY
1442 * engineers. These don't mean anything more than "these are the best
1443 * values".
1444 */
1445 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1446
1447 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1448
1449 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1450
1451 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1452
1453 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1454 reg |= 0x8000;
1455 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1456
1457 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1458
1459 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1460
1461 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1462 reg &= ~0x007f;
1463 reg |= 0x0019;
1464 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1465
1466 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1467
1468 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1469 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1470
1471 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1472
1473 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1474
1475 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1476
1477 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1478 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1479
1480 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1481
1482 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1483 reg &= ~0x8000;
1484 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1485
1486 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1487
1488 /* end of write broadcasting */
1489 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1490 reg &= ~SMI_BROADCAST_WR_EN;
1491 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1492
1493 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1494 if (ret) {
1495 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1496 MSCC_VSC8584_REVB_INT8051_FW, ret);
1497 return ret;
1498 }
1499
1500 /* Add one byte to size for the one added by the patch_fw function */
1501 ret = vsc8584_get_fw_crc(phydev,
1502 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1503 fw->size + 1, &crc);
1504 if (ret)
1505 goto out;
1506
1507 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1508 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1509 if (vsc8584_patch_fw(phydev, fw))
1510 dev_warn(dev,
1511 "failed to patch FW, expect non-optimal device\n");
1512 }
1513
1514 vsc8584_micro_deassert_reset(phydev, false);
1515
1516 /* Add one byte to size for the one added by the patch_fw function */
1517 ret = vsc8584_get_fw_crc(phydev,
1518 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1519 fw->size + 1, &crc);
1520 if (ret)
1521 goto out;
1522
1523 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1524 dev_warn(dev,
1525 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1526
1527 ret = vsc8584_micro_assert_reset(phydev);
1528 if (ret)
1529 goto out;
1530
1531 vsc8584_micro_deassert_reset(phydev, true);
1532
1533 out:
1534 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1535
1536 release_firmware(fw);
1537
1538 return ret;
1539 }
1540
1541 /* Check if one PHY has already done the init of the parts common to all PHYs
1542 * in the Quad PHY package.
1543 */
1544 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed)
1545 {
1546 struct mdio_device **map = phydev->mdio.bus->mdio_map;
1547 struct vsc8531_private *vsc8531;
1548 struct phy_device *phy;
1549 int i, addr;
1550
1551 /* VSC8584 is a Quad PHY */
1552 for (i = 0; i < 4; i++) {
1553 vsc8531 = phydev->priv;
1554
1555 if (reversed)
1556 addr = vsc8531->base_addr - i;
1557 else
1558 addr = vsc8531->base_addr + i;
1559
1560 phy = container_of(map[addr], struct phy_device, mdio);
1561
1562 if ((phy->phy_id & phydev->drv->phy_id_mask) !=
1563 (phydev->drv->phy_id & phydev->drv->phy_id_mask))
1564 continue;
1565
1566 vsc8531 = phy->priv;
1567
1568 if (vsc8531 && vsc8531->pkg_init)
1569 return true;
1570 }
1571
1572 return false;
1573 }
1574
1575 static int vsc8584_config_init(struct phy_device *phydev)
1576 {
1577 struct vsc8531_private *vsc8531 = phydev->priv;
1578 u16 addr, val;
1579 int ret, i;
1580
1581 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1582
1583 mutex_lock(&phydev->mdio.bus->mdio_lock);
1584
1585 __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
1586 MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1587 addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1588 MSCC_PHY_EXT_PHY_CNTL_4);
1589 addr >>= PHY_CNTL_4_ADDR_POS;
1590
1591 val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1592 MSCC_PHY_ACTIPHY_CNTL);
1593 if (val & PHY_ADDR_REVERSED)
1594 vsc8531->base_addr = phydev->mdio.addr + addr;
1595 else
1596 vsc8531->base_addr = phydev->mdio.addr - addr;
1597
1598 /* Some parts of the init sequence are identical for every PHY in the
1599 * package. Some parts are modifying the GPIO register bank which is a
1600 * set of registers that are affecting all PHYs, a few resetting the
1601 * microprocessor common to all PHYs. The CRC check responsible of the
1602 * checking the firmware within the 8051 microprocessor can only be
1603 * accessed via the PHY whose internal address in the package is 0.
1604 * All PHYs' interrupts mask register has to be zeroed before enabling
1605 * any PHY's interrupt in this register.
1606 * For all these reasons, we need to do the init sequence once and only
1607 * once whatever is the first PHY in the package that is initialized and
1608 * do the correct init sequence for all PHYs that are package-critical
1609 * in this pre-init function.
1610 */
1611 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) {
1612 if ((phydev->phy_id & phydev->drv->phy_id_mask) ==
1613 (PHY_ID_VSC8574 & phydev->drv->phy_id_mask))
1614 ret = vsc8574_config_pre_init(phydev);
1615 else if ((phydev->phy_id & phydev->drv->phy_id_mask) ==
1616 (PHY_ID_VSC8584 & phydev->drv->phy_id_mask))
1617 ret = vsc8584_config_pre_init(phydev);
1618 else
1619 ret = -EINVAL;
1620
1621 if (ret)
1622 goto err;
1623 }
1624
1625 vsc8531->pkg_init = true;
1626
1627 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1628 MSCC_PHY_PAGE_EXTENDED_GPIO);
1629
1630 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1631 val &= ~MAC_CFG_MASK;
1632 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1633 val |= MAC_CFG_QSGMII;
1634 else
1635 val |= MAC_CFG_SGMII;
1636
1637 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1638 if (ret)
1639 goto err;
1640
1641 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1642 PROC_CMD_READ_MOD_WRITE_PORT;
1643 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1644 val |= PROC_CMD_QSGMII_MAC;
1645 else
1646 val |= PROC_CMD_SGMII_MAC;
1647
1648 ret = vsc8584_cmd(phydev, val);
1649 if (ret)
1650 goto err;
1651
1652 usleep_range(10000, 20000);
1653
1654 /* Disable SerDes for 100Base-FX */
1655 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1656 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1657 PROC_CMD_READ_MOD_WRITE_PORT |
1658 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1659 if (ret)
1660 goto err;
1661
1662 /* Disable SerDes for 1000Base-X */
1663 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1664 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1665 PROC_CMD_READ_MOD_WRITE_PORT |
1666 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1667 if (ret)
1668 goto err;
1669
1670 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1671
1672 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1673
1674 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1675 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1676 val |= MEDIA_OP_MODE_COPPER | (VSC8584_MAC_IF_SELECTION_SGMII <<
1677 VSC8584_MAC_IF_SELECTION_POS);
1678 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1679
1680 ret = genphy_soft_reset(phydev);
1681 if (ret)
1682 return ret;
1683
1684 for (i = 0; i < vsc8531->nleds; i++) {
1685 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1686 if (ret)
1687 return ret;
1688 }
1689
1690 return genphy_config_init(phydev);
1691
1692 err:
1693 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1694 return ret;
1695 }
1696
1697 static int vsc85xx_config_init(struct phy_device *phydev)
1698 {
1699 int rc, i, phy_id;
1700 struct vsc8531_private *vsc8531 = phydev->priv;
1701
1702 rc = vsc85xx_default_config(phydev);
1703 if (rc)
1704 return rc;
1705
1706 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1707 if (rc)
1708 return rc;
1709
1710 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1711 if (rc)
1712 return rc;
1713
1714 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1715 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1716 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1717 rc = vsc8531_pre_init_seq_set(phydev);
1718 if (rc)
1719 return rc;
1720 }
1721
1722 rc = vsc85xx_eee_init_seq_set(phydev);
1723 if (rc)
1724 return rc;
1725
1726 for (i = 0; i < vsc8531->nleds; i++) {
1727 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1728 if (rc)
1729 return rc;
1730 }
1731
1732 return genphy_config_init(phydev);
1733 }
1734
1735 static int vsc8584_did_interrupt(struct phy_device *phydev)
1736 {
1737 int rc = 0;
1738
1739 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1740 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1741
1742 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1743 }
1744
1745 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
1746 {
1747 int rc = 0;
1748
1749 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1750 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1751
1752 return (rc < 0) ? rc : 0;
1753 }
1754
1755 static int vsc85xx_config_intr(struct phy_device *phydev)
1756 {
1757 int rc;
1758
1759 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1760 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
1761 MII_VSC85XX_INT_MASK_MASK);
1762 } else {
1763 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
1764 if (rc < 0)
1765 return rc;
1766 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1767 }
1768
1769 return rc;
1770 }
1771
1772 static int vsc85xx_config_aneg(struct phy_device *phydev)
1773 {
1774 int rc;
1775
1776 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
1777 if (rc < 0)
1778 return rc;
1779
1780 return genphy_config_aneg(phydev);
1781 }
1782
1783 static int vsc85xx_read_status(struct phy_device *phydev)
1784 {
1785 int rc;
1786
1787 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
1788 if (rc < 0)
1789 return rc;
1790
1791 return genphy_read_status(phydev);
1792 }
1793
1794 static int vsc8574_probe(struct phy_device *phydev)
1795 {
1796 struct vsc8531_private *vsc8531;
1797 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1798 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1799 VSC8531_DUPLEX_COLLISION};
1800
1801 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1802 if (!vsc8531)
1803 return -ENOMEM;
1804
1805 phydev->priv = vsc8531;
1806
1807 vsc8531->nleds = 4;
1808 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
1809 vsc8531->hw_stats = vsc8584_hw_stats;
1810 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
1811 vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1812 sizeof(u64), GFP_KERNEL);
1813 if (!vsc8531->stats)
1814 return -ENOMEM;
1815
1816 return vsc85xx_dt_led_modes_get(phydev, default_mode);
1817 }
1818
1819 static int vsc8584_probe(struct phy_device *phydev)
1820 {
1821 struct vsc8531_private *vsc8531;
1822 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1823 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1824 VSC8531_DUPLEX_COLLISION};
1825
1826 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
1827 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
1828 return -ENOTSUPP;
1829 }
1830
1831 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1832 if (!vsc8531)
1833 return -ENOMEM;
1834
1835 phydev->priv = vsc8531;
1836
1837 vsc8531->nleds = 4;
1838 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
1839 vsc8531->hw_stats = vsc8584_hw_stats;
1840 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
1841 vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1842 sizeof(u64), GFP_KERNEL);
1843 if (!vsc8531->stats)
1844 return -ENOMEM;
1845
1846 return vsc85xx_dt_led_modes_get(phydev, default_mode);
1847 }
1848
1849 static int vsc85xx_probe(struct phy_device *phydev)
1850 {
1851 struct vsc8531_private *vsc8531;
1852 int rate_magic;
1853 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
1854 VSC8531_LINK_100_ACTIVITY};
1855
1856 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
1857 if (rate_magic < 0)
1858 return rate_magic;
1859
1860 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1861 if (!vsc8531)
1862 return -ENOMEM;
1863
1864 phydev->priv = vsc8531;
1865
1866 vsc8531->rate_magic = rate_magic;
1867 vsc8531->nleds = 2;
1868 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
1869 vsc8531->hw_stats = vsc85xx_hw_stats;
1870 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
1871 vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1872 sizeof(u64), GFP_KERNEL);
1873 if (!vsc8531->stats)
1874 return -ENOMEM;
1875
1876 return vsc85xx_dt_led_modes_get(phydev, default_mode);
1877 }
1878
1879 /* Microsemi VSC85xx PHYs */
1880 static struct phy_driver vsc85xx_driver[] = {
1881 {
1882 .phy_id = PHY_ID_VSC8530,
1883 .name = "Microsemi FE VSC8530",
1884 .phy_id_mask = 0xfffffff0,
1885 .features = PHY_BASIC_FEATURES,
1886 .soft_reset = &genphy_soft_reset,
1887 .config_init = &vsc85xx_config_init,
1888 .config_aneg = &vsc85xx_config_aneg,
1889 .aneg_done = &genphy_aneg_done,
1890 .read_status = &vsc85xx_read_status,
1891 .ack_interrupt = &vsc85xx_ack_interrupt,
1892 .config_intr = &vsc85xx_config_intr,
1893 .suspend = &genphy_suspend,
1894 .resume = &genphy_resume,
1895 .probe = &vsc85xx_probe,
1896 .set_wol = &vsc85xx_wol_set,
1897 .get_wol = &vsc85xx_wol_get,
1898 .get_tunable = &vsc85xx_get_tunable,
1899 .set_tunable = &vsc85xx_set_tunable,
1900 .read_page = &vsc85xx_phy_read_page,
1901 .write_page = &vsc85xx_phy_write_page,
1902 .get_sset_count = &vsc85xx_get_sset_count,
1903 .get_strings = &vsc85xx_get_strings,
1904 .get_stats = &vsc85xx_get_stats,
1905 },
1906 {
1907 .phy_id = PHY_ID_VSC8531,
1908 .name = "Microsemi VSC8531",
1909 .phy_id_mask = 0xfffffff0,
1910 .features = PHY_GBIT_FEATURES,
1911 .soft_reset = &genphy_soft_reset,
1912 .config_init = &vsc85xx_config_init,
1913 .config_aneg = &vsc85xx_config_aneg,
1914 .aneg_done = &genphy_aneg_done,
1915 .read_status = &vsc85xx_read_status,
1916 .ack_interrupt = &vsc85xx_ack_interrupt,
1917 .config_intr = &vsc85xx_config_intr,
1918 .suspend = &genphy_suspend,
1919 .resume = &genphy_resume,
1920 .probe = &vsc85xx_probe,
1921 .set_wol = &vsc85xx_wol_set,
1922 .get_wol = &vsc85xx_wol_get,
1923 .get_tunable = &vsc85xx_get_tunable,
1924 .set_tunable = &vsc85xx_set_tunable,
1925 .read_page = &vsc85xx_phy_read_page,
1926 .write_page = &vsc85xx_phy_write_page,
1927 .get_sset_count = &vsc85xx_get_sset_count,
1928 .get_strings = &vsc85xx_get_strings,
1929 .get_stats = &vsc85xx_get_stats,
1930 },
1931 {
1932 .phy_id = PHY_ID_VSC8540,
1933 .name = "Microsemi FE VSC8540 SyncE",
1934 .phy_id_mask = 0xfffffff0,
1935 .features = PHY_BASIC_FEATURES,
1936 .soft_reset = &genphy_soft_reset,
1937 .config_init = &vsc85xx_config_init,
1938 .config_aneg = &vsc85xx_config_aneg,
1939 .aneg_done = &genphy_aneg_done,
1940 .read_status = &vsc85xx_read_status,
1941 .ack_interrupt = &vsc85xx_ack_interrupt,
1942 .config_intr = &vsc85xx_config_intr,
1943 .suspend = &genphy_suspend,
1944 .resume = &genphy_resume,
1945 .probe = &vsc85xx_probe,
1946 .set_wol = &vsc85xx_wol_set,
1947 .get_wol = &vsc85xx_wol_get,
1948 .get_tunable = &vsc85xx_get_tunable,
1949 .set_tunable = &vsc85xx_set_tunable,
1950 .read_page = &vsc85xx_phy_read_page,
1951 .write_page = &vsc85xx_phy_write_page,
1952 .get_sset_count = &vsc85xx_get_sset_count,
1953 .get_strings = &vsc85xx_get_strings,
1954 .get_stats = &vsc85xx_get_stats,
1955 },
1956 {
1957 .phy_id = PHY_ID_VSC8541,
1958 .name = "Microsemi VSC8541 SyncE",
1959 .phy_id_mask = 0xfffffff0,
1960 .features = PHY_GBIT_FEATURES,
1961 .soft_reset = &genphy_soft_reset,
1962 .config_init = &vsc85xx_config_init,
1963 .config_aneg = &vsc85xx_config_aneg,
1964 .aneg_done = &genphy_aneg_done,
1965 .read_status = &vsc85xx_read_status,
1966 .ack_interrupt = &vsc85xx_ack_interrupt,
1967 .config_intr = &vsc85xx_config_intr,
1968 .suspend = &genphy_suspend,
1969 .resume = &genphy_resume,
1970 .probe = &vsc85xx_probe,
1971 .set_wol = &vsc85xx_wol_set,
1972 .get_wol = &vsc85xx_wol_get,
1973 .get_tunable = &vsc85xx_get_tunable,
1974 .set_tunable = &vsc85xx_set_tunable,
1975 .read_page = &vsc85xx_phy_read_page,
1976 .write_page = &vsc85xx_phy_write_page,
1977 .get_sset_count = &vsc85xx_get_sset_count,
1978 .get_strings = &vsc85xx_get_strings,
1979 .get_stats = &vsc85xx_get_stats,
1980 },
1981 {
1982 .phy_id = PHY_ID_VSC8574,
1983 .name = "Microsemi GE VSC8574 SyncE",
1984 .phy_id_mask = 0xfffffff0,
1985 .features = PHY_GBIT_FEATURES,
1986 .soft_reset = &genphy_soft_reset,
1987 .config_init = &vsc8584_config_init,
1988 .config_aneg = &vsc85xx_config_aneg,
1989 .aneg_done = &genphy_aneg_done,
1990 .read_status = &vsc85xx_read_status,
1991 .ack_interrupt = &vsc85xx_ack_interrupt,
1992 .config_intr = &vsc85xx_config_intr,
1993 .did_interrupt = &vsc8584_did_interrupt,
1994 .suspend = &genphy_suspend,
1995 .resume = &genphy_resume,
1996 .probe = &vsc8574_probe,
1997 .set_wol = &vsc85xx_wol_set,
1998 .get_wol = &vsc85xx_wol_get,
1999 .get_tunable = &vsc85xx_get_tunable,
2000 .set_tunable = &vsc85xx_set_tunable,
2001 .read_page = &vsc85xx_phy_read_page,
2002 .write_page = &vsc85xx_phy_write_page,
2003 .get_sset_count = &vsc85xx_get_sset_count,
2004 .get_strings = &vsc85xx_get_strings,
2005 .get_stats = &vsc85xx_get_stats,
2006 },
2007 {
2008 .phy_id = PHY_ID_VSC8584,
2009 .name = "Microsemi GE VSC8584 SyncE",
2010 .phy_id_mask = 0xfffffff0,
2011 .features = PHY_GBIT_FEATURES,
2012 .soft_reset = &genphy_soft_reset,
2013 .config_init = &vsc8584_config_init,
2014 .config_aneg = &vsc85xx_config_aneg,
2015 .aneg_done = &genphy_aneg_done,
2016 .read_status = &vsc85xx_read_status,
2017 .ack_interrupt = &vsc85xx_ack_interrupt,
2018 .config_intr = &vsc85xx_config_intr,
2019 .did_interrupt = &vsc8584_did_interrupt,
2020 .suspend = &genphy_suspend,
2021 .resume = &genphy_resume,
2022 .probe = &vsc8584_probe,
2023 .get_tunable = &vsc85xx_get_tunable,
2024 .set_tunable = &vsc85xx_set_tunable,
2025 .read_page = &vsc85xx_phy_read_page,
2026 .write_page = &vsc85xx_phy_write_page,
2027 .get_sset_count = &vsc85xx_get_sset_count,
2028 .get_strings = &vsc85xx_get_strings,
2029 .get_stats = &vsc85xx_get_stats,
2030 }
2031
2032 };
2033
2034 module_phy_driver(vsc85xx_driver);
2035
2036 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2037 { PHY_ID_VSC8530, 0xfffffff0, },
2038 { PHY_ID_VSC8531, 0xfffffff0, },
2039 { PHY_ID_VSC8540, 0xfffffff0, },
2040 { PHY_ID_VSC8541, 0xfffffff0, },
2041 { PHY_ID_VSC8574, 0xfffffff0, },
2042 { PHY_ID_VSC8584, 0xfffffff0, },
2043 { }
2044 };
2045
2046 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2047
2048 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2049 MODULE_AUTHOR("Nagaraju Lakkaraju");
2050 MODULE_LICENSE("Dual MIT/GPL");
Linux with added FPC-III support