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1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, see <http://www.gnu.org/licenses/>.
25 */
27 /*
28 Module: rt2800
29 Abstract: Data structures and registers for the rt2800 modules.
30 Supported chipsets: RT2800E, RT2800ED & RT2800U.
31 */
33 #ifndef RT2800_H
34 #define RT2800_H
36 /*
37 * RF chip defines.
38 *
39 * RF2820 2.4G 2T3R
40 * RF2850 2.4G/5G 2T3R
41 * RF2720 2.4G 1T2R
42 * RF2750 2.4G/5G 1T2R
43 * RF3020 2.4G 1T1R
44 * RF2020 2.4G B/G
45 * RF3021 2.4G 1T2R
46 * RF3022 2.4G 2T2R
47 * RF3052 2.4G/5G 2T2R
48 * RF2853 2.4G/5G 3T3R
49 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
50 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
51 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
52 * RF5592 2.4G/5G 2T2R
53 * RF3070 2.4G 1T1R
54 * RF5360 2.4G 1T1R
55 * RF5362 2.4G 1T1R
56 * RF5370 2.4G 1T1R
57 * RF5390 2.4G 1T1R
58 */
59 #define RF2820 0x0001
60 #define RF2850 0x0002
61 #define RF2720 0x0003
62 #define RF2750 0x0004
63 #define RF3020 0x0005
64 #define RF2020 0x0006
65 #define RF3021 0x0007
66 #define RF3022 0x0008
67 #define RF3052 0x0009
68 #define RF2853 0x000a
69 #define RF3320 0x000b
70 #define RF3322 0x000c
71 #define RF3053 0x000d
72 #define RF5592 0x000f
73 #define RF3070 0x3070
74 #define RF3290 0x3290
75 #define RF5350 0x5350
76 #define RF5360 0x5360
77 #define RF5362 0x5362
78 #define RF5370 0x5370
79 #define RF5372 0x5372
80 #define RF5390 0x5390
81 #define RF5392 0x5392
82 #define RF7620 0x7620
84 /*
85 * Chipset revisions.
86 */
87 #define REV_RT2860C 0x0100
88 #define REV_RT2860D 0x0101
89 #define REV_RT2872E 0x0200
90 #define REV_RT3070E 0x0200
91 #define REV_RT3070F 0x0201
92 #define REV_RT3071E 0x0211
93 #define REV_RT3090E 0x0211
94 #define REV_RT3390E 0x0211
95 #define REV_RT3593E 0x0211
96 #define REV_RT5390F 0x0502
97 #define REV_RT5370G 0x0503
98 #define REV_RT5390R 0x1502
99 #define REV_RT5592C 0x0221
101 #define DEFAULT_RSSI_OFFSET 120
103 /*
104 * Register layout information.
105 */
106 #define CSR_REG_BASE 0x1000
107 #define CSR_REG_SIZE 0x0800
108 #define EEPROM_BASE 0x0000
109 #define EEPROM_SIZE 0x0200
110 #define BBP_BASE 0x0000
111 #define BBP_SIZE 0x00ff
112 #define RF_BASE 0x0004
113 #define RF_SIZE 0x0010
114 #define RFCSR_BASE 0x0000
115 #define RFCSR_SIZE 0x0040
117 /*
118 * Number of TX queues.
119 */
120 #define NUM_TX_QUEUES 4
122 /*
123 * Registers.
124 */
127 /*
128 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
129 */
130 #define MAC_CSR0_3290 0x0000
132 /*
133 * E2PROM_CSR: PCI EEPROM control register.
134 * RELOAD: Write 1 to reload eeprom content.
135 * TYPE: 0: 93c46, 1:93c66.
136 * LOAD_STATUS: 1:loading, 0:done.
137 */
138 #define E2PROM_CSR 0x0004
139 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
140 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
141 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
142 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
143 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
144 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
145 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
147 /*
148 * CMB_CTRL_CFG
149 */
150 #define CMB_CTRL 0x0020
151 #define AUX_OPT_BIT0 FIELD32(0x00000001)
152 #define AUX_OPT_BIT1 FIELD32(0x00000002)
153 #define AUX_OPT_BIT2 FIELD32(0x00000004)
154 #define AUX_OPT_BIT3 FIELD32(0x00000008)
155 #define AUX_OPT_BIT4 FIELD32(0x00000010)
156 #define AUX_OPT_BIT5 FIELD32(0x00000020)
157 #define AUX_OPT_BIT6 FIELD32(0x00000040)
158 #define AUX_OPT_BIT7 FIELD32(0x00000080)
159 #define AUX_OPT_BIT8 FIELD32(0x00000100)
160 #define AUX_OPT_BIT9 FIELD32(0x00000200)
161 #define AUX_OPT_BIT10 FIELD32(0x00000400)
162 #define AUX_OPT_BIT11 FIELD32(0x00000800)
163 #define AUX_OPT_BIT12 FIELD32(0x00001000)
164 #define AUX_OPT_BIT13 FIELD32(0x00002000)
165 #define AUX_OPT_BIT14 FIELD32(0x00004000)
166 #define AUX_OPT_BIT15 FIELD32(0x00008000)
167 #define LDO25_LEVEL FIELD32(0x00030000)
168 #define LDO25_LARGEA FIELD32(0x00040000)
169 #define LDO25_FRC_ON FIELD32(0x00080000)
170 #define CMB_RSV FIELD32(0x00300000)
171 #define XTAL_RDY FIELD32(0x00400000)
172 #define PLL_LD FIELD32(0x00800000)
173 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
174 #define LDO_BGSEL FIELD32(0x30000000)
175 #define LDO3_EN FIELD32(0x40000000)
176 #define LDO0_EN FIELD32(0x80000000)
178 /*
179 * EFUSE_CSR_3290: RT3290 EEPROM
180 */
181 #define EFUSE_CTRL_3290 0x0024
183 /*
184 * EFUSE_DATA3 of 3290
185 */
186 #define EFUSE_DATA3_3290 0x0028
188 /*
189 * EFUSE_DATA2 of 3290
190 */
191 #define EFUSE_DATA2_3290 0x002c
193 /*
194 * EFUSE_DATA1 of 3290
195 */
196 #define EFUSE_DATA1_3290 0x0030
198 /*
199 * EFUSE_DATA0 of 3290
200 */
201 #define EFUSE_DATA0_3290 0x0034
203 /*
204 * OSC_CTRL_CFG
205 * Ring oscillator configuration
206 */
207 #define OSC_CTRL 0x0038
208 #define OSC_REF_CYCLE FIELD32(0x00001fff)
209 #define OSC_RSV FIELD32(0x0000e000)
210 #define OSC_CAL_CNT FIELD32(0x0fff0000)
211 #define OSC_CAL_ACK FIELD32(0x10000000)
212 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
213 #define OSC_CAL_REQ FIELD32(0x40000000)
214 #define OSC_ROSC_EN FIELD32(0x80000000)
216 /*
217 * COEX_CFG_0
218 */
219 #define COEX_CFG0 0x0040
220 #define COEX_CFG_ANT FIELD32(0xff000000)
221 /*
222 * COEX_CFG_1
223 */
224 #define COEX_CFG1 0x0044
226 /*
227 * COEX_CFG_2
228 */
229 #define COEX_CFG2 0x0048
230 #define BT_COEX_CFG1 FIELD32(0xff000000)
231 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
232 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
233 #define WL_COEX_CFG0 FIELD32(0x000000ff)
234 /*
235 * PLL_CTRL_CFG
236 * PLL configuration register
237 */
238 #define PLL_CTRL 0x0050
239 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
240 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
241 #define PLL_CONTROL FIELD32(0x00070000)
242 #define PLL_LPF_R1 FIELD32(0x00080000)
243 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
244 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
245 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
246 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
247 #define PLL_LOCK_CTRL FIELD32(0x70000000)
248 #define PLL_VBGBK_EN FIELD32(0x80000000)
251 /*
252 * WLAN_CTRL_CFG
253 * RT3290 wlan configuration
254 */
255 #define WLAN_FUN_CTRL 0x0080
256 #define WLAN_EN FIELD32(0x00000001)
257 #define WLAN_CLK_EN FIELD32(0x00000002)
258 #define WLAN_RSV1 FIELD32(0x00000004)
259 #define WLAN_RESET FIELD32(0x00000008)
260 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
261 #define FRC_WL_ANT_SET FIELD32(0x00000020)
262 #define INV_TR_SW0 FIELD32(0x00000040)
263 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
264 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
265 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
266 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
267 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
268 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
269 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
270 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
271 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
272 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
273 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
274 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
275 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
276 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
277 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
278 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
279 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
280 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
281 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
282 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
283 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
284 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
285 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
286 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
287 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
288 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
289 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
291 /*
292 * AUX_CTRL: Aux/PCI-E related configuration
293 */
294 #define AUX_CTRL 0x10c
295 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
296 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
298 /*
299 * OPT_14: Unknown register used by rt3xxx devices.
300 */
301 #define OPT_14_CSR 0x0114
302 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
304 /*
305 * INT_SOURCE_CSR: Interrupt source register.
306 * Write one to clear corresponding bit.
307 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
308 */
309 #define INT_SOURCE_CSR 0x0200
310 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
311 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
312 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
313 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
314 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
315 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
316 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
317 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
318 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
319 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
320 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
321 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
322 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
323 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
324 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
325 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
326 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
327 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
329 /*
330 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
331 */
332 #define INT_MASK_CSR 0x0204
333 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
334 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
335 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
336 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
337 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
338 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
339 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
340 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
341 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
342 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
343 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
344 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
345 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
346 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
347 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
348 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
349 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
350 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
352 /*
353 * WPDMA_GLO_CFG
354 */
355 #define WPDMA_GLO_CFG 0x0208
356 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
357 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
358 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
359 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
360 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
361 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
362 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
363 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
364 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
366 /*
367 * WPDMA_RST_IDX
368 */
369 #define WPDMA_RST_IDX 0x020c
370 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
371 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
372 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
373 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
374 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
375 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
376 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
378 /*
379 * DELAY_INT_CFG
380 */
381 #define DELAY_INT_CFG 0x0210
382 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
383 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
384 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
385 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
386 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
387 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
389 /*
390 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
391 * AIFSN0: AC_VO
392 * AIFSN1: AC_VI
393 * AIFSN2: AC_BE
394 * AIFSN3: AC_BK
395 */
396 #define WMM_AIFSN_CFG 0x0214
397 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
398 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
399 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
400 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
402 /*
403 * WMM_CWMIN_CSR: CWmin for each EDCA AC
404 * CWMIN0: AC_VO
405 * CWMIN1: AC_VI
406 * CWMIN2: AC_BE
407 * CWMIN3: AC_BK
408 */
409 #define WMM_CWMIN_CFG 0x0218
410 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
411 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
412 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
413 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
415 /*
416 * WMM_CWMAX_CSR: CWmax for each EDCA AC
417 * CWMAX0: AC_VO
418 * CWMAX1: AC_VI
419 * CWMAX2: AC_BE
420 * CWMAX3: AC_BK
421 */
422 #define WMM_CWMAX_CFG 0x021c
423 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
424 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
425 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
426 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
428 /*
429 * AC_TXOP0: AC_VO/AC_VI TXOP register
430 * AC0TXOP: AC_VO in unit of 32us
431 * AC1TXOP: AC_VI in unit of 32us
432 */
433 #define WMM_TXOP0_CFG 0x0220
434 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
435 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
437 /*
438 * AC_TXOP1: AC_BE/AC_BK TXOP register
439 * AC2TXOP: AC_BE in unit of 32us
440 * AC3TXOP: AC_BK in unit of 32us
441 */
442 #define WMM_TXOP1_CFG 0x0224
443 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
444 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
446 /*
447 * GPIO_CTRL:
448 * GPIO_CTRL_VALx: GPIO value
449 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
450 */
451 #define GPIO_CTRL 0x0228
452 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
453 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
454 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
455 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
456 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
457 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
458 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
459 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
460 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
461 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
462 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
463 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
464 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
465 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
466 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
467 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
468 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
469 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
470 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
471 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
472 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
473 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
475 /*
476 * MCU_CMD_CFG
477 */
478 #define MCU_CMD_CFG 0x022c
480 /*
481 * AC_VO register offsets
482 */
483 #define TX_BASE_PTR0 0x0230
484 #define TX_MAX_CNT0 0x0234
485 #define TX_CTX_IDX0 0x0238
486 #define TX_DTX_IDX0 0x023c
488 /*
489 * AC_VI register offsets
490 */
491 #define TX_BASE_PTR1 0x0240
492 #define TX_MAX_CNT1 0x0244
493 #define TX_CTX_IDX1 0x0248
494 #define TX_DTX_IDX1 0x024c
496 /*
497 * AC_BE register offsets
498 */
499 #define TX_BASE_PTR2 0x0250
500 #define TX_MAX_CNT2 0x0254
501 #define TX_CTX_IDX2 0x0258
502 #define TX_DTX_IDX2 0x025c
504 /*
505 * AC_BK register offsets
506 */
507 #define TX_BASE_PTR3 0x0260
508 #define TX_MAX_CNT3 0x0264
509 #define TX_CTX_IDX3 0x0268
510 #define TX_DTX_IDX3 0x026c
512 /*
513 * HCCA register offsets
514 */
515 #define TX_BASE_PTR4 0x0270
516 #define TX_MAX_CNT4 0x0274
517 #define TX_CTX_IDX4 0x0278
518 #define TX_DTX_IDX4 0x027c
520 /*
521 * MGMT register offsets
522 */
523 #define TX_BASE_PTR5 0x0280
524 #define TX_MAX_CNT5 0x0284
525 #define TX_CTX_IDX5 0x0288
526 #define TX_DTX_IDX5 0x028c
528 /*
529 * RX register offsets
530 */
531 #define RX_BASE_PTR 0x0290
532 #define RX_MAX_CNT 0x0294
533 #define RX_CRX_IDX 0x0298
534 #define RX_DRX_IDX 0x029c
536 /*
537 * USB_DMA_CFG
538 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
539 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
540 * PHY_CLEAR: phy watch dog enable.
541 * TX_CLEAR: Clear USB DMA TX path.
542 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
543 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
544 * RX_BULK_EN: Enable USB DMA Rx.
545 * TX_BULK_EN: Enable USB DMA Tx.
546 * EP_OUT_VALID: OUT endpoint data valid.
547 * RX_BUSY: USB DMA RX FSM busy.
548 * TX_BUSY: USB DMA TX FSM busy.
549 */
550 #define USB_DMA_CFG 0x02a0
551 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
552 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
553 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
554 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
555 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
556 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
557 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
558 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
559 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
560 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
561 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
563 /*
564 * US_CYC_CNT
565 * BT_MODE_EN: Bluetooth mode enable
566 * CLOCK CYCLE: Clock cycle count in 1us.
567 * PCI:0x21, PCIE:0x7d, USB:0x1e
568 */
569 #define US_CYC_CNT 0x02a4
570 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
571 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
573 /*
574 * PBF_SYS_CTRL
575 * HOST_RAM_WRITE: enable Host program ram write selection
576 */
577 #define PBF_SYS_CTRL 0x0400
578 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
579 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
581 /*
582 * HOST-MCU shared memory
583 */
584 #define HOST_CMD_CSR 0x0404
585 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
587 /*
588 * PBF registers
589 * Most are for debug. Driver doesn't touch PBF register.
590 */
591 #define PBF_CFG 0x0408
592 #define PBF_MAX_PCNT 0x040c
593 #define PBF_CTRL 0x0410
594 #define PBF_INT_STA 0x0414
595 #define PBF_INT_ENA 0x0418
597 /*
598 * BCN_OFFSET0:
599 */
600 #define BCN_OFFSET0 0x042c
601 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
602 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
603 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
604 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
606 /*
607 * BCN_OFFSET1:
608 */
609 #define BCN_OFFSET1 0x0430
610 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
611 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
612 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
613 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
615 /*
616 * TXRXQ_PCNT: PBF register
617 * PCNT_TX0Q: Page count for TX hardware queue 0
618 * PCNT_TX1Q: Page count for TX hardware queue 1
619 * PCNT_TX2Q: Page count for TX hardware queue 2
620 * PCNT_RX0Q: Page count for RX hardware queue
621 */
622 #define TXRXQ_PCNT 0x0438
623 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
624 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
625 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
626 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
628 /*
629 * PBF register
630 * Debug. Driver doesn't touch PBF register.
631 */
632 #define PBF_DBG 0x043c
634 /*
635 * RF registers
636 */
637 #define RF_CSR_CFG 0x0500
638 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
639 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
640 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
641 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
643 /*
644 * MT7620 RF registers (reversed order)
645 */
646 #define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
647 #define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
648 #define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
649 #define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
651 /* undocumented registers for calibration of new MAC */
652 #define RF_CONTROL0 0x0518
653 #define RF_BYPASS0 0x051c
654 #define RF_CONTROL1 0x0520
655 #define RF_BYPASS1 0x0524
656 #define RF_CONTROL2 0x0528
657 #define RF_BYPASS2 0x052c
658 #define RF_CONTROL3 0x0530
659 #define RF_BYPASS3 0x0534
661 /*
662 * EFUSE_CSR: RT30x0 EEPROM
663 */
664 #define EFUSE_CTRL 0x0580
665 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
666 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
667 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
668 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
670 /*
671 * EFUSE_DATA0
672 */
673 #define EFUSE_DATA0 0x0590
675 /*
676 * EFUSE_DATA1
677 */
678 #define EFUSE_DATA1 0x0594
680 /*
681 * EFUSE_DATA2
682 */
683 #define EFUSE_DATA2 0x0598
685 /*
686 * EFUSE_DATA3
687 */
688 #define EFUSE_DATA3 0x059c
690 /*
691 * LDO_CFG0
692 */
693 #define LDO_CFG0 0x05d4
694 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
695 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
696 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
697 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
698 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
699 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
700 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
702 /*
703 * GPIO_SWITCH
704 */
705 #define GPIO_SWITCH 0x05dc
706 #define GPIO_SWITCH_0 FIELD32(0x00000001)
707 #define GPIO_SWITCH_1 FIELD32(0x00000002)
708 #define GPIO_SWITCH_2 FIELD32(0x00000004)
709 #define GPIO_SWITCH_3 FIELD32(0x00000008)
710 #define GPIO_SWITCH_4 FIELD32(0x00000010)
711 #define GPIO_SWITCH_5 FIELD32(0x00000020)
712 #define GPIO_SWITCH_6 FIELD32(0x00000040)
713 #define GPIO_SWITCH_7 FIELD32(0x00000080)
715 /*
716 * FIXME: where the DEBUG_INDEX name come from?
717 */
718 #define MAC_DEBUG_INDEX 0x05e8
719 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
721 /*
722 * MAC Control/Status Registers(CSR).
723 * Some values are set in TU, whereas 1 TU == 1024 us.
724 */
726 /*
727 * MAC_CSR0: ASIC revision number.
728 * ASIC_REV: 0
729 * ASIC_VER: 2860 or 2870
730 */
731 #define MAC_CSR0 0x1000
732 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
733 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
735 /*
736 * MAC_SYS_CTRL:
737 */
738 #define MAC_SYS_CTRL 0x1004
739 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
740 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
741 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
742 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
743 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
744 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
745 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
746 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
748 /*
749 * MAC_ADDR_DW0: STA MAC register 0
750 */
751 #define MAC_ADDR_DW0 0x1008
752 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
753 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
754 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
755 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
757 /*
758 * MAC_ADDR_DW1: STA MAC register 1
759 * UNICAST_TO_ME_MASK:
760 * Used to mask off bits from byte 5 of the MAC address
761 * to determine the UNICAST_TO_ME bit for RX frames.
762 * The full mask is complemented by BSS_ID_MASK:
763 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
764 */
765 #define MAC_ADDR_DW1 0x100c
766 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
767 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
768 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
770 /*
771 * MAC_BSSID_DW0: BSSID register 0
772 */
773 #define MAC_BSSID_DW0 0x1010
774 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
775 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
776 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
777 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
779 /*
780 * MAC_BSSID_DW1: BSSID register 1
781 * BSS_ID_MASK:
782 * 0: 1-BSSID mode (BSS index = 0)
783 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
784 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
785 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
786 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
787 * BSSID. This will make sure that those bits will be ignored
788 * when determining the MY_BSS of RX frames.
789 */
790 #define MAC_BSSID_DW1 0x1014
791 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
792 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
793 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
794 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
796 /*
797 * MAX_LEN_CFG: Maximum frame length register.
798 * MAX_MPDU: rt2860b max 16k bytes
799 * MAX_PSDU: Maximum PSDU length
800 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
801 */
802 #define MAX_LEN_CFG 0x1018
803 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
804 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
805 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
806 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
808 /*
809 * BBP_CSR_CFG: BBP serial control register
810 * VALUE: Register value to program into BBP
811 * REG_NUM: Selected BBP register
812 * READ_CONTROL: 0 write BBP, 1 read BBP
813 * BUSY: ASIC is busy executing BBP commands
814 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
815 * BBP_RW_MODE: 0 serial, 1 parallel
816 */
817 #define BBP_CSR_CFG 0x101c
818 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
819 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
820 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
821 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
822 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
823 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
825 /*
826 * RF_CSR_CFG0: RF control register
827 * REGID_AND_VALUE: Register value to program into RF
828 * BITWIDTH: Selected RF register
829 * STANDBYMODE: 0 high when standby, 1 low when standby
830 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
831 * BUSY: ASIC is busy executing RF commands
832 */
833 #define RF_CSR_CFG0 0x1020
834 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
835 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
836 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
837 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
838 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
839 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
841 /*
842 * RF_CSR_CFG1: RF control register
843 * REGID_AND_VALUE: Register value to program into RF
844 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
845 * 0: 3 system clock cycle (37.5usec)
846 * 1: 5 system clock cycle (62.5usec)
847 */
848 #define RF_CSR_CFG1 0x1024
849 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
850 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
852 /*
853 * RF_CSR_CFG2: RF control register
854 * VALUE: Register value to program into RF
855 */
856 #define RF_CSR_CFG2 0x1028
857 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
859 /*
860 * LED_CFG: LED control
861 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
862 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
863 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
864 * color LED's:
865 * 0: off
866 * 1: blinking upon TX2
867 * 2: periodic slow blinking
868 * 3: always on
869 * LED polarity:
870 * 0: active low
871 * 1: active high
872 */
873 #define LED_CFG 0x102c
874 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
875 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
876 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
877 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
878 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
879 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
880 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
882 /*
883 * AMPDU_BA_WINSIZE: Force BlockAck window size
884 * FORCE_WINSIZE_ENABLE:
885 * 0: Disable forcing of BlockAck window size
886 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
887 * window size values in the TXWI
888 * FORCE_WINSIZE: BlockAck window size
889 */
890 #define AMPDU_BA_WINSIZE 0x1040
891 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
892 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
894 /*
895 * XIFS_TIME_CFG: MAC timing
896 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
897 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
898 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
899 * when MAC doesn't reference BBP signal BBRXEND
900 * EIFS: unit 1us
901 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
902 *
903 */
904 #define XIFS_TIME_CFG 0x1100
905 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
906 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
907 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
908 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
909 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
911 /*
912 * BKOFF_SLOT_CFG:
913 */
914 #define BKOFF_SLOT_CFG 0x1104
915 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
916 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
918 /*
919 * NAV_TIME_CFG:
920 */
921 #define NAV_TIME_CFG 0x1108
922 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
923 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
924 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
925 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
927 /*
928 * CH_TIME_CFG: count as channel busy
929 * EIFS_BUSY: Count EIFS as channel busy
930 * NAV_BUSY: Count NAS as channel busy
931 * RX_BUSY: Count RX as channel busy
932 * TX_BUSY: Count TX as channel busy
933 * TMR_EN: Enable channel statistics timer
934 */
935 #define CH_TIME_CFG 0x110c
936 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
937 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
938 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
939 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
940 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
942 /*
943 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
944 */
945 #define PBF_LIFE_TIMER 0x1110
947 /*
948 * BCN_TIME_CFG:
949 * BEACON_INTERVAL: in unit of 1/16 TU
950 * TSF_TICKING: Enable TSF auto counting
951 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
952 * BEACON_GEN: Enable beacon generator
953 */
954 #define BCN_TIME_CFG 0x1114
955 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
956 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
957 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
958 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
959 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
960 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
962 /*
963 * TBTT_SYNC_CFG:
964 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
965 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
966 */
967 #define TBTT_SYNC_CFG 0x1118
968 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
969 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
970 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
971 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
973 /*
974 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
975 */
976 #define TSF_TIMER_DW0 0x111c
977 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
979 /*
980 * TSF_TIMER_DW1: Local msb TSF timer, read-only
981 */
982 #define TSF_TIMER_DW1 0x1120
983 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
985 /*
986 * TBTT_TIMER: TImer remains till next TBTT, read-only
987 */
988 #define TBTT_TIMER 0x1124
990 /*
991 * INT_TIMER_CFG: timer configuration
992 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
993 * GP_TIMER: period of general purpose timer in units of 1/16 TU
994 */
995 #define INT_TIMER_CFG 0x1128
996 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
997 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
999 /*
1000 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
1001 */
1002 #define INT_TIMER_EN 0x112c
1003 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
1004 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
1006 /*
1007 * CH_IDLE_STA: channel idle time (in us)
1008 */
1009 #define CH_IDLE_STA 0x1130
1011 /*
1012 * CH_BUSY_STA: channel busy time on primary channel (in us)
1013 */
1014 #define CH_BUSY_STA 0x1134
1016 /*
1017 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
1018 */
1019 #define CH_BUSY_STA_SEC 0x1138
1021 /*
1022 * MAC_STATUS_CFG:
1023 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1024 * if 1 or higher one of the 2 registers is busy.
1025 */
1026 #define MAC_STATUS_CFG 0x1200
1027 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1029 /*
1030 * PWR_PIN_CFG:
1031 */
1032 #define PWR_PIN_CFG 0x1204
1034 /*
1035 * AUTOWAKEUP_CFG: Manual power control / status register
1036 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1037 * AUTOWAKE: 0:sleep, 1:awake
1038 */
1039 #define AUTOWAKEUP_CFG 0x1208
1040 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1041 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1042 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1044 /*
1045 * MIMO_PS_CFG: MIMO Power-save Configuration
1046 */
1047 #define MIMO_PS_CFG 0x1210
1048 #define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
1049 #define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
1050 #define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
1051 #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
1052 #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
1054 /*
1055 * EDCA_AC0_CFG:
1056 */
1057 #define EDCA_AC0_CFG 0x1300
1058 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1059 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1060 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1061 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1063 /*
1064 * EDCA_AC1_CFG:
1065 */
1066 #define EDCA_AC1_CFG 0x1304
1067 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1068 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1069 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1070 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1072 /*
1073 * EDCA_AC2_CFG:
1074 */
1075 #define EDCA_AC2_CFG 0x1308
1076 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1077 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1078 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1079 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1081 /*
1082 * EDCA_AC3_CFG:
1083 */
1084 #define EDCA_AC3_CFG 0x130c
1085 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1086 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1087 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1088 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1090 /*
1091 * EDCA_TID_AC_MAP:
1092 */
1093 #define EDCA_TID_AC_MAP 0x1310
1095 /*
1096 * TX_PWR_CFG:
1097 */
1098 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1099 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1100 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1101 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1102 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1103 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1104 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1105 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1107 /*
1108 * TX_PWR_CFG_0:
1109 */
1110 #define TX_PWR_CFG_0 0x1314
1111 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1112 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1113 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1114 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1115 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1116 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1117 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1118 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1119 /* bits for 3T devices */
1120 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1121 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1122 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1123 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1124 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1125 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1126 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1127 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1128 /* bits for new 2T devices */
1129 #define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
1130 #define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
1131 #define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
1132 #define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
1135 /*
1136 * TX_PWR_CFG_1:
1137 */
1138 #define TX_PWR_CFG_1 0x1318
1139 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1140 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1141 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1142 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1143 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1144 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1145 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1146 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1147 /* bits for 3T devices */
1148 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1149 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1150 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1151 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1152 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1153 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1154 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1155 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1156 /* bits for new 2T devices */
1157 #define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
1158 #define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
1159 #define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
1160 #define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
1162 /*
1163 * TX_PWR_CFG_2:
1164 */
1165 #define TX_PWR_CFG_2 0x131c
1166 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1167 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1168 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1169 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1170 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1171 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1172 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1173 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1174 /* bits for 3T devices */
1175 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1176 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1177 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1178 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1179 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1180 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1181 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1182 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1183 /* bits for new 2T devices */
1184 #define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
1185 #define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
1186 #define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
1187 #define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
1189 /*
1190 * TX_PWR_CFG_3:
1191 */
1192 #define TX_PWR_CFG_3 0x1320
1193 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1194 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1195 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1196 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1197 #define TX_PWR_CFG_3_UNKNOWN1 FIELD32(0x000f0000)
1198 #define TX_PWR_CFG_3_UNKNOWN2 FIELD32(0x00f00000)
1199 #define TX_PWR_CFG_3_UNKNOWN3 FIELD32(0x0f000000)
1200 #define TX_PWR_CFG_3_UNKNOWN4 FIELD32(0xf0000000)
1201 /* bits for 3T devices */
1202 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1203 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1204 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1205 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1206 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1207 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1208 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1209 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1210 /* bits for new 2T devices */
1211 #define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
1212 #define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
1213 #define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
1214 #define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
1216 /*
1217 * TX_PWR_CFG_4:
1218 */
1219 #define TX_PWR_CFG_4 0x1324
1220 #define TX_PWR_CFG_4_UNKNOWN5 FIELD32(0x0000000f)
1221 #define TX_PWR_CFG_4_UNKNOWN6 FIELD32(0x000000f0)
1222 #define TX_PWR_CFG_4_UNKNOWN7 FIELD32(0x00000f00)
1223 #define TX_PWR_CFG_4_UNKNOWN8 FIELD32(0x0000f000)
1224 /* bits for 3T devices */
1225 #define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f)
1226 #define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
1227 #define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
1228 #define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
1229 /* bits for new 2T devices */
1230 #define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
1231 #define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
1233 /*
1234 * TX_PIN_CFG:
1235 */
1236 #define TX_PIN_CFG 0x1328
1237 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1238 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1239 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1240 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1241 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1242 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1243 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1244 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1245 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1246 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1247 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1248 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1249 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1250 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1251 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1252 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1253 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1254 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1255 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1256 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1257 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1258 #define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
1259 #define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
1260 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1261 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1262 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1263 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1264 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1265 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1266 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1267 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1269 /*
1270 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1271 */
1272 #define TX_BAND_CFG 0x132c
1273 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1274 #define TX_BAND_CFG_A FIELD32(0x00000002)
1275 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1277 /*
1278 * TX_SW_CFG0:
1279 */
1280 #define TX_SW_CFG0 0x1330
1282 /*
1283 * TX_SW_CFG1:
1284 */
1285 #define TX_SW_CFG1 0x1334
1287 /*
1288 * TX_SW_CFG2:
1289 */
1290 #define TX_SW_CFG2 0x1338
1292 /*
1293 * TXOP_THRES_CFG:
1294 */
1295 #define TXOP_THRES_CFG 0x133c
1297 /*
1298 * TXOP_CTRL_CFG:
1299 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1300 * AC_TRUN_EN: Enable/Disable truncation for AC change
1301 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1302 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1303 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1304 * RESERVED_TRUN_EN: Reserved
1305 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1306 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1307 * transmissions if extension CCA is clear).
1308 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1309 * EXT_CWMIN: CwMin for extension channel backoff
1310 * 0: Disabled
1311 *
1312 */
1313 #define TXOP_CTRL_CFG 0x1340
1314 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1315 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1316 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1317 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1318 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1319 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1320 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1321 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1322 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1323 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1325 /*
1326 * TX_RTS_CFG:
1327 * RTS_THRES: unit:byte
1328 * RTS_FBK_EN: enable rts rate fallback
1329 */
1330 #define TX_RTS_CFG 0x1344
1331 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1332 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1333 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1335 /*
1336 * TX_TIMEOUT_CFG:
1337 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1338 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1339 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1340 * it is recommended that:
1341 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1342 */
1343 #define TX_TIMEOUT_CFG 0x1348
1344 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1345 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1346 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1348 /*
1349 * TX_RTY_CFG:
1350 * SHORT_RTY_LIMIT: short retry limit
1351 * LONG_RTY_LIMIT: long retry limit
1352 * LONG_RTY_THRE: Long retry threshoold
1353 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1354 * 0:expired by retry limit, 1: expired by mpdu life timer
1355 * AGG_RTY_MODE: Aggregate MPDU retry mode
1356 * 0:expired by retry limit, 1: expired by mpdu life timer
1357 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1358 */
1359 #define TX_RTY_CFG 0x134c
1360 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1361 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1362 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1363 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1364 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1365 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1367 /*
1368 * TX_LINK_CFG:
1369 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1370 * MFB_ENABLE: TX apply remote MFB 1:enable
1371 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1372 * 0: not apply remote remote unsolicit (MFS=7)
1373 * TX_MRQ_EN: MCS request TX enable
1374 * TX_RDG_EN: RDG TX enable
1375 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1376 * REMOTE_MFB: remote MCS feedback
1377 * REMOTE_MFS: remote MCS feedback sequence number
1378 */
1379 #define TX_LINK_CFG 0x1350
1380 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1381 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1382 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1383 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1384 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1385 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1386 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1387 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1389 /*
1390 * HT_FBK_CFG0:
1391 */
1392 #define HT_FBK_CFG0 0x1354
1393 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1394 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1395 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1396 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1397 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1398 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1399 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1400 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1402 /*
1403 * HT_FBK_CFG1:
1404 */
1405 #define HT_FBK_CFG1 0x1358
1406 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1407 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1408 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1409 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1410 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1411 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1412 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1413 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1415 /*
1416 * LG_FBK_CFG0:
1417 */
1418 #define LG_FBK_CFG0 0x135c
1419 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1420 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1421 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1422 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1423 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1424 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1425 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1426 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1428 /*
1429 * LG_FBK_CFG1:
1430 */
1431 #define LG_FBK_CFG1 0x1360
1432 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1433 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1434 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1435 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1437 /*
1438 * CCK_PROT_CFG: CCK Protection
1439 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1440 * PROTECT_CTRL: Protection control frame type for CCK TX
1441 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1442 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1443 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1444 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1445 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1446 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1447 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1448 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1449 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1450 * RTS_TH_EN: RTS threshold enable on CCK TX
1451 */
1452 #define CCK_PROT_CFG 0x1364
1453 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1454 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1455 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1456 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1457 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1458 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1459 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1460 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1461 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1462 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1463 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1465 /*
1466 * OFDM_PROT_CFG: OFDM Protection
1467 */
1468 #define OFDM_PROT_CFG 0x1368
1469 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1470 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1471 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1472 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1473 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1474 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1475 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1476 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1477 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1478 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1479 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1481 /*
1482 * MM20_PROT_CFG: MM20 Protection
1483 */
1484 #define MM20_PROT_CFG 0x136c
1485 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1486 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1487 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1488 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1489 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1490 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1491 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1492 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1493 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1494 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1495 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1497 /*
1498 * MM40_PROT_CFG: MM40 Protection
1499 */
1500 #define MM40_PROT_CFG 0x1370
1501 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1502 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1503 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1504 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1505 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1506 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1507 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1508 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1509 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1510 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1511 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1513 /*
1514 * GF20_PROT_CFG: GF20 Protection
1515 */
1516 #define GF20_PROT_CFG 0x1374
1517 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1518 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1519 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1520 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1521 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1522 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1523 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1524 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1525 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1526 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1527 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1529 /*
1530 * GF40_PROT_CFG: GF40 Protection
1531 */
1532 #define GF40_PROT_CFG 0x1378
1533 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1534 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1535 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1536 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1537 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1538 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1539 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1540 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1541 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1542 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1543 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1545 /*
1546 * EXP_CTS_TIME:
1547 */
1548 #define EXP_CTS_TIME 0x137c
1550 /*
1551 * EXP_ACK_TIME:
1552 */
1553 #define EXP_ACK_TIME 0x1380
1555 /* TX_PWR_CFG_5 */
1556 #define TX_PWR_CFG_5 0x1384
1557 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1558 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1559 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1560 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1561 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1562 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1564 /* TX_PWR_CFG_6 */
1565 #define TX_PWR_CFG_6 0x1388
1566 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1567 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1568 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1569 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1570 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1571 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1573 /* TX_PWR_CFG_0_EXT */
1574 #define TX_PWR_CFG_0_EXT 0x1390
1575 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1576 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1577 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1578 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1580 /* TX_PWR_CFG_1_EXT */
1581 #define TX_PWR_CFG_1_EXT 0x1394
1582 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1583 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1584 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1585 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1587 /* TX_PWR_CFG_2_EXT */
1588 #define TX_PWR_CFG_2_EXT 0x1398
1589 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1590 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1591 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1592 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1594 /* TX_PWR_CFG_3_EXT */
1595 #define TX_PWR_CFG_3_EXT 0x139c
1596 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1597 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1598 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1599 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1601 /* TX_PWR_CFG_4_EXT */
1602 #define TX_PWR_CFG_4_EXT 0x13a0
1603 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1604 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1606 /* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
1607 * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
1608 */
1609 #define TX0_RF_GAIN_CORRECT 0x13a0
1610 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1611 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1612 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1613 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1615 #define TX1_RF_GAIN_CORRECT 0x13a4
1616 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1617 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1618 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1619 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1621 /* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
1622 * Format: 7-bit, signed value
1623 * Unit: 0.5 dB, Range: -20 dB to -5 dB
1624 */
1625 #define TX0_RF_GAIN_ATTEN 0x13a8
1626 #define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1627 #define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1628 #define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1629 #define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1630 #define TX1_RF_GAIN_ATTEN 0x13ac
1631 #define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1632 #define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1633 #define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1634 #define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1636 /* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
1637 * TX_ALC_LIMIT_n: TXn upper limit
1638 * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
1639 * Unit: 0.5 dB, Range: 0 to 23.5 dB
1640 */
1641 #define TX_ALC_CFG_0 0x13b0
1642 #define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
1643 #define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
1644 #define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
1645 #define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
1647 /* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
1648 * TX_TEMP_COMP: TX Power Temperature Compensation
1649 * Unit: 0.5 dB, Range: -10 dB to 10 dB
1650 * TXn_GAIN_FINE: TXn Gain Fine Adjustment
1651 * Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
1652 * RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after
1653 * deassertion of PA_PE.
1654 * Unit: 0.25 usec
1655 * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
1656 * RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE
1657 * deassertion if RF_TOS_DONE is missing.
1658 * Unit: 0.25 usec
1659 * RF_TOS_ENABLE: TX offset calibration enable
1660 * ROS_BUSY_EN: RX offset calibration busy enable
1661 */
1662 #define TX_ALC_CFG_1 0x13b4
1663 #define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
1664 #define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
1665 #define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
1666 #define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
1667 #define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
1668 #define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
1669 #define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
1670 #define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
1671 #define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
1673 /* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
1674 * Format: 5-bit signed values
1675 * Unit: 0.5 dB, Range: -8 dB to 7 dB
1676 */
1677 #define TX0_BB_GAIN_ATTEN 0x13c0
1678 #define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1679 #define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1680 #define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1681 #define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1682 #define TX1_BB_GAIN_ATTEN 0x13c4
1683 #define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1684 #define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1685 #define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1686 #define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1688 /* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
1689 #define TX_ALC_VGA3 0x13c8
1690 #define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
1691 #define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
1692 #define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
1693 #define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
1695 /* TX_PWR_CFG_7 */
1696 #define TX_PWR_CFG_7 0x13d4
1697 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1698 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1699 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1700 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1701 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1702 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1703 /* bits for new 2T devices */
1704 #define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
1705 #define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
1708 /* TX_PWR_CFG_8 */
1709 #define TX_PWR_CFG_8 0x13d8
1710 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1711 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1712 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1713 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1714 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1715 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1716 /* bits for new 2T devices */
1717 #define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
1720 /* TX_PWR_CFG_9 */
1721 #define TX_PWR_CFG_9 0x13dc
1722 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1723 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1724 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1725 /* bits for new 2T devices */
1726 #define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
1728 /*
1729 * RX_FILTER_CFG: RX configuration register.
1730 */
1731 #define RX_FILTER_CFG 0x1400
1732 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1733 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1734 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1735 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1736 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1737 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1738 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1739 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1740 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1741 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1742 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1743 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1744 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1745 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1746 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1747 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1748 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1750 /*
1751 * AUTO_RSP_CFG:
1752 * AUTORESPONDER: 0: disable, 1: enable
1753 * BAC_ACK_POLICY: 0:long, 1:short preamble
1754 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1755 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1756 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1757 * DUAL_CTS_EN: Power bit value in control frame
1758 * ACK_CTS_PSM_BIT:Power bit value in control frame
1759 */
1760 #define AUTO_RSP_CFG 0x1404
1761 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1762 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1763 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1764 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1765 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1766 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1767 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1769 /*
1770 * LEGACY_BASIC_RATE:
1771 */
1772 #define LEGACY_BASIC_RATE 0x1408
1774 /*
1775 * HT_BASIC_RATE:
1776 */
1777 #define HT_BASIC_RATE 0x140c
1779 /*
1780 * HT_CTRL_CFG:
1781 */
1782 #define HT_CTRL_CFG 0x1410
1784 /*
1785 * SIFS_COST_CFG:
1786 */
1787 #define SIFS_COST_CFG 0x1414
1789 /*
1790 * RX_PARSER_CFG:
1791 * Set NAV for all received frames
1792 */
1793 #define RX_PARSER_CFG 0x1418
1795 /*
1796 * TX_SEC_CNT0:
1797 */
1798 #define TX_SEC_CNT0 0x1500
1800 /*
1801 * RX_SEC_CNT0:
1802 */
1803 #define RX_SEC_CNT0 0x1504
1805 /*
1806 * CCMP_FC_MUTE:
1807 */
1808 #define CCMP_FC_MUTE 0x1508
1810 /*
1811 * TXOP_HLDR_ADDR0:
1812 */
1813 #define TXOP_HLDR_ADDR0 0x1600
1815 /*
1816 * TXOP_HLDR_ADDR1:
1817 */
1818 #define TXOP_HLDR_ADDR1 0x1604
1820 /*
1821 * TXOP_HLDR_ET:
1822 */
1823 #define TXOP_HLDR_ET 0x1608
1825 /*
1826 * QOS_CFPOLL_RA_DW0:
1827 */
1828 #define QOS_CFPOLL_RA_DW0 0x160c
1830 /*
1831 * QOS_CFPOLL_RA_DW1:
1832 */
1833 #define QOS_CFPOLL_RA_DW1 0x1610
1835 /*
1836 * QOS_CFPOLL_QC:
1837 */
1838 #define QOS_CFPOLL_QC 0x1614
1840 /*
1841 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1842 */
1843 #define RX_STA_CNT0 0x1700
1844 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1845 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1847 /*
1848 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1849 */
1850 #define RX_STA_CNT1 0x1704
1851 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1852 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1854 /*
1855 * RX_STA_CNT2:
1856 */
1857 #define RX_STA_CNT2 0x1708
1858 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1859 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1861 /*
1862 * TX_STA_CNT0: TX Beacon count
1863 */
1864 #define TX_STA_CNT0 0x170c
1865 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1866 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1868 /*
1869 * TX_STA_CNT1: TX tx count
1870 */
1871 #define TX_STA_CNT1 0x1710
1872 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1873 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1875 /*
1876 * TX_STA_CNT2: TX tx count
1877 */
1878 #define TX_STA_CNT2 0x1714
1879 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1880 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1882 /*
1883 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1884 *
1885 * This register is implemented as FIFO with 16 entries in the HW. Each
1886 * register read fetches the next tx result. If the FIFO is full because
1887 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1888 * triggered, the hw seems to simply drop further tx results.
1889 *
1890 * VALID: 1: this tx result is valid
1891 * 0: no valid tx result -> driver should stop reading
1892 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1893 * to match a frame with its tx result (even though the PID is
1894 * only 4 bits wide).
1895 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1896 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1897 * This identification number is calculated by ((idx % 3) + 1).
1898 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1899 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1900 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1901 * WCID: The wireless client ID.
1902 * MCS: The tx rate used during the last transmission of this frame, be it
1903 * successful or not.
1904 * PHYMODE: The phymode used for the transmission.
1905 */
1906 #define TX_STA_FIFO 0x1718
1907 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1908 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1909 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1910 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1911 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1912 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1913 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1914 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1915 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1916 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1917 #define TX_STA_FIFO_BW FIELD32(0x00800000)
1918 #define TX_STA_FIFO_SGI FIELD32(0x01000000)
1919 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1921 /*
1922 * TX_AGG_CNT: Debug counter
1923 */
1924 #define TX_AGG_CNT 0x171c
1925 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1926 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1928 /*
1929 * TX_AGG_CNT0:
1930 */
1931 #define TX_AGG_CNT0 0x1720
1932 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1933 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1935 /*
1936 * TX_AGG_CNT1:
1937 */
1938 #define TX_AGG_CNT1 0x1724
1939 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1940 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1942 /*
1943 * TX_AGG_CNT2:
1944 */
1945 #define TX_AGG_CNT2 0x1728
1946 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1947 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1949 /*
1950 * TX_AGG_CNT3:
1951 */
1952 #define TX_AGG_CNT3 0x172c
1953 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1954 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1956 /*
1957 * TX_AGG_CNT4:
1958 */
1959 #define TX_AGG_CNT4 0x1730
1960 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1961 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1963 /*
1964 * TX_AGG_CNT5:
1965 */
1966 #define TX_AGG_CNT5 0x1734
1967 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1968 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1970 /*
1971 * TX_AGG_CNT6:
1972 */
1973 #define TX_AGG_CNT6 0x1738
1974 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1975 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1977 /*
1978 * TX_AGG_CNT7:
1979 */
1980 #define TX_AGG_CNT7 0x173c
1981 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1982 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1984 /*
1985 * MPDU_DENSITY_CNT:
1986 * TX_ZERO_DEL: TX zero length delimiter count
1987 * RX_ZERO_DEL: RX zero length delimiter count
1988 */
1989 #define MPDU_DENSITY_CNT 0x1740
1990 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1991 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1993 /*
1994 * Security key table memory.
1995 *
1996 * The pairwise key table shares some memory with the beacon frame
1997 * buffers 6 and 7. That basically means that when beacon 6 & 7
1998 * are used we should only use the reduced pairwise key table which
1999 * has a maximum of 222 entries.
2000 *
2001 * ---------------------------------------------
2002 * |0x4000 | Pairwise Key | Reduced Pairwise |
2003 * | | Table | Key Table |
2004 * | | Size: 256 * 32 | Size: 222 * 32 |
2005 * |0x5BC0 | |-------------------
2006 * | | | Beacon 6 |
2007 * |0x5DC0 | |-------------------
2008 * | | | Beacon 7 |
2009 * |0x5FC0 | |-------------------
2010 * |0x5FFF | |
2011 * --------------------------
2012 *
2013 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
2014 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
2015 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
2016 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
2017 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
2018 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
2019 */
2020 #define MAC_WCID_BASE 0x1800
2021 #define PAIRWISE_KEY_TABLE_BASE 0x4000
2022 #define MAC_IVEIV_TABLE_BASE 0x6000
2023 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
2024 #define SHARED_KEY_TABLE_BASE 0x6c00
2025 #define SHARED_KEY_MODE_BASE 0x7000
2027 #define MAC_WCID_ENTRY(__idx) \
2028 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
2029 #define PAIRWISE_KEY_ENTRY(__idx) \
2030 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
2031 #define MAC_IVEIV_ENTRY(__idx) \
2032 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
2033 #define MAC_WCID_ATTR_ENTRY(__idx) \
2034 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
2035 #define SHARED_KEY_ENTRY(__idx) \
2036 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
2037 #define SHARED_KEY_MODE_ENTRY(__idx) \
2038 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
2055 /*
2056 * MAC_WCID_ATTRIBUTE:
2057 */
2058 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
2059 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
2060 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
2061 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
2062 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
2063 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
2064 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
2065 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
2067 /*
2068 * SHARED_KEY_MODE:
2069 */
2070 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
2071 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
2072 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
2073 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
2074 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
2075 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
2076 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
2077 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
2079 /*
2080 * HOST-MCU communication
2081 */
2083 /*
2084 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
2085 * CMD_TOKEN: Command id, 0xff disable status reporting.
2086 */
2087 #define H2M_MAILBOX_CSR 0x7010
2088 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
2089 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
2090 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
2091 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
2093 /*
2094 * H2M_MAILBOX_CID:
2095 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
2096 * If all slots are occupied status will be dropped.
2097 */
2098 #define H2M_MAILBOX_CID 0x7014
2099 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
2100 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
2101 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
2102 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
2104 /*
2105 * H2M_MAILBOX_STATUS:
2106 * Command status will be saved to same slot as command id.
2107 */
2108 #define H2M_MAILBOX_STATUS 0x701c
2110 /*
2111 * H2M_INT_SRC:
2112 */
2113 #define H2M_INT_SRC 0x7024
2115 /*
2116 * H2M_BBP_AGENT:
2117 */
2118 #define H2M_BBP_AGENT 0x7028
2120 /*
2121 * MCU_LEDCS: LED control for MCU Mailbox.
2122 */
2123 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
2124 #define MCU_LEDCS_POLARITY FIELD8(0x01)
2126 /*
2127 * HW_CS_CTS_BASE:
2128 * Carrier-sense CTS frame base address.
2129 * It's where mac stores carrier-sense frame for carrier-sense function.
2130 */
2131 #define HW_CS_CTS_BASE 0x7700
2133 /*
2134 * HW_DFS_CTS_BASE:
2135 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
2136 */
2137 #define HW_DFS_CTS_BASE 0x7780
2139 /*
2140 * TXRX control registers - base address 0x3000
2141 */
2143 /*
2144 * TXRX_CSR1:
2145 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
2146 */
2147 #define TXRX_CSR1 0x77d0
2149 /*
2150 * HW_DEBUG_SETTING_BASE:
2151 * since NULL frame won't be that long (256 byte)
2152 * We steal 16 tail bytes to save debugging settings
2153 */
2154 #define HW_DEBUG_SETTING_BASE 0x77f0
2155 #define HW_DEBUG_SETTING_BASE2 0x7770
2157 /*
2158 * HW_BEACON_BASE
2159 * In order to support maximum 8 MBSS and its maximum length
2160 * is 512 bytes for each beacon
2161 * Three section discontinue memory segments will be used.
2162 * 1. The original region for BCN 0~3
2163 * 2. Extract memory from FCE table for BCN 4~5
2164 * 3. Extract memory from Pair-wise key table for BCN 6~7
2165 * It occupied those memory of wcid 238~253 for BCN 6
2166 * and wcid 222~237 for BCN 7 (see Security key table memory
2167 * for more info).
2168 *
2169 * IMPORTANT NOTE: Not sure why legacy driver does this,
2170 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
2171 */
2172 #define HW_BEACON_BASE0 0x7800
2173 #define HW_BEACON_BASE1 0x7a00
2174 #define HW_BEACON_BASE2 0x7c00
2175 #define HW_BEACON_BASE3 0x7e00
2176 #define HW_BEACON_BASE4 0x7200
2177 #define HW_BEACON_BASE5 0x7400
2178 #define HW_BEACON_BASE6 0x5dc0
2179 #define HW_BEACON_BASE7 0x5bc0
2181 #define HW_BEACON_BASE(__index) \
2182 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2183 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2184 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2186 #define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64)
2188 /*
2189 * BBP registers.
2190 * The wordsize of the BBP is 8 bits.
2191 */
2193 /*
2194 * BBP 1: TX Antenna & Power Control
2195 * POWER_CTRL:
2196 * 0 - normal,
2197 * 1 - drop tx power by 6dBm,
2198 * 2 - drop tx power by 12dBm,
2199 * 3 - increase tx power by 6dBm
2200 */
2201 #define BBP1_TX_POWER_CTRL FIELD8(0x03)
2202 #define BBP1_TX_ANTENNA FIELD8(0x18)
2204 /*
2205 * BBP 3: RX Antenna
2206 */
2207 #define BBP3_RX_ADC FIELD8(0x03)
2208 #define BBP3_RX_ANTENNA FIELD8(0x18)
2209 #define BBP3_HT40_MINUS FIELD8(0x20)
2210 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
2211 #define BBP3_ADC_INIT_MODE FIELD8(0x80)
2213 /*
2214 * BBP 4: Bandwidth
2215 */
2216 #define BBP4_TX_BF FIELD8(0x01)
2217 #define BBP4_BANDWIDTH FIELD8(0x18)
2218 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
2220 /* BBP27 */
2221 #define BBP27_RX_CHAIN_SEL FIELD8(0x60)
2223 /*
2224 * BBP 47: Bandwidth
2225 */
2226 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
2227 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
2228 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
2229 #define BBP47_TSSI_ADC6 FIELD8(0x80)
2231 /*
2232 * BBP 49
2233 */
2234 #define BBP49_UPDATE_FLAG FIELD8(0x01)
2236 /*
2237 * BBP 105:
2238 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
2239 * - bit1: FEQ (Feed Forward Compensation) for independend streams
2240 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
2241 * stream)
2242 * - bit4: channel estimation updates based on remodulation of
2243 * L-SIG and HT-SIG symbols
2244 */
2245 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
2246 #define BBP105_FEQ FIELD8(0x02)
2247 #define BBP105_MLD FIELD8(0x04)
2248 #define BBP105_SIG_REMODULATION FIELD8(0x08)
2250 /*
2251 * BBP 109
2252 */
2253 #define BBP109_TX0_POWER FIELD8(0x0f)
2254 #define BBP109_TX1_POWER FIELD8(0xf0)
2256 /* BBP 110 */
2257 #define BBP110_TX2_POWER FIELD8(0x0f)
2260 /*
2261 * BBP 138: Unknown
2262 */
2263 #define BBP138_RX_ADC1 FIELD8(0x02)
2264 #define BBP138_RX_ADC2 FIELD8(0x04)
2265 #define BBP138_TX_DAC1 FIELD8(0x20)
2266 #define BBP138_TX_DAC2 FIELD8(0x40)
2268 /*
2269 * BBP 152: Rx Ant
2270 */
2271 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
2273 /*
2274 * BBP 254: unknown
2275 */
2276 #define BBP254_BIT7 FIELD8(0x80)
2278 /*
2279 * RFCSR registers
2280 * The wordsize of the RFCSR is 8 bits.
2281 */
2283 /*
2284 * RFCSR 1:
2285 */
2286 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2287 #define RFCSR1_PLL_PD FIELD8(0x02)
2288 #define RFCSR1_RX0_PD FIELD8(0x04)
2289 #define RFCSR1_TX0_PD FIELD8(0x08)
2290 #define RFCSR1_RX1_PD FIELD8(0x10)
2291 #define RFCSR1_TX1_PD FIELD8(0x20)
2292 #define RFCSR1_RX2_PD FIELD8(0x40)
2293 #define RFCSR1_TX2_PD FIELD8(0x80)
2294 #define RFCSR1_TX2_EN_MT7620 FIELD8(0x02)
2296 /*
2297 * RFCSR 2:
2298 */
2299 #define RFCSR2_RESCAL_EN FIELD8(0x80)
2300 #define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
2301 #define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
2303 /*
2304 * RFCSR 3:
2305 */
2306 #define RFCSR3_K FIELD8(0x0f)
2307 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2308 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2309 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2310 /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */
2311 #define RFCSR3_VCOCAL_EN FIELD8(0x80)
2312 /* Bits for RF3050 */
2313 #define RFCSR3_BIT1 FIELD8(0x02)
2314 #define RFCSR3_BIT2 FIELD8(0x04)
2315 #define RFCSR3_BIT3 FIELD8(0x08)
2316 #define RFCSR3_BIT4 FIELD8(0x10)
2317 #define RFCSR3_BIT5 FIELD8(0x20)
2319 /*
2320 * RFCSR 4:
2321 * VCOCAL_EN used by MT7620
2322 */
2323 #define RFCSR4_VCOCAL_EN FIELD8(0x80)
2325 /*
2326 * FRCSR 5:
2327 */
2328 #define RFCSR5_R1 FIELD8(0x0c)
2330 /*
2331 * RFCSR 6:
2332 */
2333 #define RFCSR6_R1 FIELD8(0x03)
2334 #define RFCSR6_R2 FIELD8(0x40)
2335 #define RFCSR6_TXDIV FIELD8(0x0c)
2336 /* bits for RF3053 */
2337 #define RFCSR6_VCO_IC FIELD8(0xc0)
2339 /*
2340 * RFCSR 7:
2341 */
2342 #define RFCSR7_RF_TUNING FIELD8(0x01)
2343 #define RFCSR7_BIT1 FIELD8(0x02)
2344 #define RFCSR7_BIT2 FIELD8(0x04)
2345 #define RFCSR7_BIT3 FIELD8(0x08)
2346 #define RFCSR7_BIT4 FIELD8(0x10)
2347 #define RFCSR7_BIT5 FIELD8(0x20)
2348 #define RFCSR7_BITS67 FIELD8(0xc0)
2350 /*
2351 * RFCSR 9:
2352 */
2353 #define RFCSR9_K FIELD8(0x0f)
2354 #define RFCSR9_N FIELD8(0x10)
2355 #define RFCSR9_UNKNOWN FIELD8(0x60)
2356 #define RFCSR9_MOD FIELD8(0x80)
2358 /*
2359 * RFCSR 11:
2360 */
2361 #define RFCSR11_R FIELD8(0x03)
2362 #define RFCSR11_PLL_MOD FIELD8(0x0c)
2363 #define RFCSR11_MOD FIELD8(0xc0)
2364 /* bits for RF3053 */
2365 /* TODO: verify RFCSR11_MOD usage on other chips */
2366 #define RFCSR11_PLL_IDOH FIELD8(0x40)
2369 /*
2370 * RFCSR 12:
2371 */
2372 #define RFCSR12_TX_POWER FIELD8(0x1f)
2373 #define RFCSR12_DR0 FIELD8(0xe0)
2375 /*
2376 * RFCSR 13:
2377 */
2378 #define RFCSR13_TX_POWER FIELD8(0x1f)
2379 #define RFCSR13_DR0 FIELD8(0xe0)
2380 #define RFCSR13_RDIV_MT7620 FIELD8(0x03)
2382 /*
2383 * RFCSR 15:
2384 */
2385 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
2387 /*
2388 * RFCSR 16:
2389 */
2390 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2391 #define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F)
2392 #define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0)
2394 /*
2395 * RFCSR 17:
2396 */
2397 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2398 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
2399 #define RFCSR17_R FIELD8(0x20)
2400 #define RFCSR17_CODE FIELD8(0x7f)
2402 /* RFCSR 18 */
2403 #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
2405 /* RFCSR 19 */
2406 #define RFCSR19_K FIELD8(0x03)
2408 /*
2409 * RFCSR 20:
2410 */
2411 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
2413 /*
2414 * RFCSR 21:
2415 */
2416 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
2417 #define RFCSR21_BIT1 FIELD8(0x01)
2418 #define RFCSR21_BIT8 FIELD8(0x80)
2420 /*
2421 * RFCSR 22:
2422 */
2423 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2424 #define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07)
2426 /*
2427 * RFCSR 23:
2428 */
2429 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2431 /*
2432 * RFCSR 24:
2433 */
2434 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2435 #define RFCSR24_TX_H20M FIELD8(0x20)
2436 #define RFCSR24_TX_CALIB FIELD8(0x7f)
2438 /*
2439 * RFCSR 27:
2440 */
2441 #define RFCSR27_R1 FIELD8(0x03)
2442 #define RFCSR27_R2 FIELD8(0x04)
2443 #define RFCSR27_R3 FIELD8(0x30)
2444 #define RFCSR27_R4 FIELD8(0x40)
2446 /*
2447 * RFCSR 28:
2448 */
2449 #define RFCSR28_CH11_HT40 FIELD8(0x04)
2451 /*
2452 * RFCSR 29:
2453 */
2454 #define RFCSR29_ADC6_TEST FIELD8(0x01)
2455 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2456 #define RFCSR29_RSSI_RESET FIELD8(0x04)
2457 #define RFCSR29_RSSI_ON FIELD8(0x08)
2458 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2459 #define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2461 /*
2462 * RFCSR 30:
2463 */
2464 #define RFCSR30_TX_H20M FIELD8(0x02)
2465 #define RFCSR30_RX_H20M FIELD8(0x04)
2466 #define RFCSR30_RX_VCM FIELD8(0x18)
2467 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2468 #define RF3322_RFCSR30_TX_H20M FIELD8(0x01)
2469 #define RF3322_RFCSR30_RX_H20M FIELD8(0x02)
2471 /*
2472 * RFCSR 31:
2473 */
2474 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2475 #define RFCSR31_RX_H20M FIELD8(0x20)
2476 #define RFCSR31_RX_CALIB FIELD8(0x7f)
2478 /* RFCSR 32 bits for RF3053 */
2479 #define RFCSR32_TX_AGC_FC FIELD8(0xf8)
2481 /* RFCSR 36 bits for RF3053 */
2482 #define RFCSR36_RF_BS FIELD8(0x80)
2484 /*
2485 * RFCSR 34:
2486 */
2487 #define RFCSR34_TX0_EXT_PA FIELD8(0x04)
2488 #define RFCSR34_TX1_EXT_PA FIELD8(0x08)
2490 /*
2491 * RFCSR 38:
2492 */
2493 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
2495 /*
2496 * RFCSR 39:
2497 */
2498 #define RFCSR39_RX_DIV FIELD8(0x40)
2499 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
2501 /*
2502 * RFCSR 41:
2503 */
2504 #define RFCSR41_BIT1 FIELD8(0x01)
2505 #define RFCSR41_BIT4 FIELD8(0x08)
2507 /*
2508 * RFCSR 42:
2509 */
2510 #define RFCSR42_BIT1 FIELD8(0x01)
2511 #define RFCSR42_BIT4 FIELD8(0x08)
2512 #define RFCSR42_TX2_EN_MT7620 FIELD8(0x40)
2514 /*
2515 * RFCSR 49:
2516 */
2517 #define RFCSR49_TX FIELD8(0x3f)
2518 #define RFCSR49_EP FIELD8(0xc0)
2519 /* bits for RT3593 */
2520 #define RFCSR49_TX_LO1_IC FIELD8(0x1c)
2521 #define RFCSR49_TX_DIV FIELD8(0x20)
2523 /*
2524 * RFCSR 50:
2525 */
2526 #define RFCSR50_TX FIELD8(0x3f)
2527 #define RFCSR50_TX0_EXT_PA FIELD8(0x02)
2528 #define RFCSR50_TX1_EXT_PA FIELD8(0x10)
2529 #define RFCSR50_EP FIELD8(0xc0)
2530 /* bits for RT3593 */
2531 #define RFCSR50_TX_LO1_EN FIELD8(0x20)
2532 #define RFCSR50_TX_LO2_EN FIELD8(0x10)
2534 /* RFCSR 51 */
2535 /* bits for RT3593 */
2536 #define RFCSR51_BITS01 FIELD8(0x03)
2537 #define RFCSR51_BITS24 FIELD8(0x1c)
2538 #define RFCSR51_BITS57 FIELD8(0xe0)
2540 #define RFCSR53_TX_POWER FIELD8(0x3f)
2541 #define RFCSR53_UNKNOWN FIELD8(0xc0)
2543 #define RFCSR54_TX_POWER FIELD8(0x3f)
2544 #define RFCSR54_UNKNOWN FIELD8(0xc0)
2546 #define RFCSR55_TX_POWER FIELD8(0x3f)
2547 #define RFCSR55_UNKNOWN FIELD8(0xc0)
2549 #define RFCSR57_DRV_CC FIELD8(0xfc)
2552 /*
2553 * RF registers
2554 */
2556 /*
2557 * RF 2
2558 */
2559 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2560 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2561 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2563 /*
2564 * RF 3
2565 */
2566 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2567 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2568 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2570 /*
2571 * RF 4
2572 */
2573 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2574 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2575 #define RF4_TXPOWER_A FIELD32(0x00000780)
2576 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2577 #define RF4_HT40 FIELD32(0x00200000)
2579 /*
2580 * EEPROM content.
2581 * The wordsize of the EEPROM is 16 bits.
2582 */
2586 EEPROM_VERSION,
2587 EEPROM_MAC_ADDR_0,
2588 EEPROM_MAC_ADDR_1,
2589 EEPROM_MAC_ADDR_2,
2590 EEPROM_NIC_CONF0,
2591 EEPROM_NIC_CONF1,
2592 EEPROM_FREQ,
2593 EEPROM_LED_AG_CONF,
2594 EEPROM_LED_ACT_CONF,
2595 EEPROM_LED_POLARITY,
2596 EEPROM_NIC_CONF2,
2597 EEPROM_LNA,
2598 EEPROM_RSSI_BG,
2599 EEPROM_RSSI_BG2,
2600 EEPROM_TXMIXER_GAIN_BG,
2601 EEPROM_RSSI_A,
2602 EEPROM_RSSI_A2,
2603 EEPROM_TXMIXER_GAIN_A,
2604 EEPROM_EIRP_MAX_TX_POWER,
2605 EEPROM_TXPOWER_DELTA,
2606 EEPROM_TXPOWER_BG1,
2607 EEPROM_TXPOWER_BG2,
2608 EEPROM_TSSI_BOUND_BG1,
2609 EEPROM_TSSI_BOUND_BG2,
2610 EEPROM_TSSI_BOUND_BG3,
2611 EEPROM_TSSI_BOUND_BG4,
2612 EEPROM_TSSI_BOUND_BG5,
2613 EEPROM_TXPOWER_A1,
2614 EEPROM_TXPOWER_A2,
2615 EEPROM_TXPOWER_INIT,
2616 EEPROM_TSSI_BOUND_A1,
2617 EEPROM_TSSI_BOUND_A2,
2618 EEPROM_TSSI_BOUND_A3,
2619 EEPROM_TSSI_BOUND_A4,
2620 EEPROM_TSSI_BOUND_A5,
2621 EEPROM_TXPOWER_BYRATE,
2622 EEPROM_BBP_START,
2624 /* IDs for extended EEPROM format used by three-chain devices */
2625 EEPROM_EXT_LNA2,
2626 EEPROM_EXT_TXPOWER_BG3,
2627 EEPROM_EXT_TXPOWER_A3,
2629 /* New values must be added before this */
2630 EEPROM_WORD_COUNT
2631 };
2633 /*
2634 * EEPROM Version
2635 */
2636 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
2637 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
2639 /*
2640 * HW MAC address.
2641 */
2642 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2643 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2644 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2645 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2646 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2647 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2649 /*
2650 * EEPROM NIC Configuration 0
2651 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2652 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2653 * RF_TYPE: RFIC type
2654 */
2655 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2656 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2657 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2659 /*
2660 * EEPROM NIC Configuration 1
2661 * HW_RADIO: 0: disable, 1: enable
2662 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2663 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2664 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2665 * CARDBUS_ACCEL: 0: enable, 1: disable
2666 * BW40M_SB_2G: 0: disable, 1: enable
2667 * BW40M_SB_5G: 0: disable, 1: enable
2668 * WPS_PBC: 0: disable, 1: enable
2669 * BW40M_2G: 0: enable, 1: disable
2670 * BW40M_5G: 0: enable, 1: disable
2671 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2672 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2673 * 10: Main antenna, 11: Aux antenna
2674 * INTERNAL_TX_ALC: 0: disable, 1: enable
2675 * BT_COEXIST: 0: disable, 1: enable
2676 * DAC_TEST: 0: disable, 1: enable
2677 * EXTERNAL_TX0_PA: 0: disable, 1: enable (only on RT3352)
2678 * EXTERNAL_TX1_PA: 0: disable, 1: enable (only on RT3352)
2679 */
2680 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2681 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2682 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2683 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2684 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2685 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2686 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2687 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2688 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2689 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2690 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2691 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2692 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2693 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2694 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2695 #define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 FIELD16(0x4000)
2696 #define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 FIELD16(0x8000)
2698 /*
2699 * EEPROM frequency
2700 */
2701 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2702 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2703 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2705 /*
2706 * EEPROM LED
2707 * POLARITY_RDY_G: Polarity RDY_G setting.
2708 * POLARITY_RDY_A: Polarity RDY_A setting.
2709 * POLARITY_ACT: Polarity ACT setting.
2710 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2711 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2712 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2713 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2714 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2715 * LED_MODE: Led mode.
2716 */
2717 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2718 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2719 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2720 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2721 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2722 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2723 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2724 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2725 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2727 /*
2728 * EEPROM NIC Configuration 2
2729 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2730 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2731 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2732 */
2733 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2734 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2735 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2737 /*
2738 * EEPROM LNA
2739 */
2740 #define EEPROM_LNA_BG FIELD16(0x00ff)
2741 #define EEPROM_LNA_A0 FIELD16(0xff00)
2743 /*
2744 * EEPROM RSSI BG offset
2745 */
2746 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2747 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2749 /*
2750 * EEPROM RSSI BG2 offset
2751 */
2752 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2753 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2755 /*
2756 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2757 */
2758 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2760 /*
2761 * EEPROM RSSI A offset
2762 */
2763 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2764 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2766 /*
2767 * EEPROM RSSI A2 offset
2768 */
2769 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2770 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2772 /*
2773 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2774 */
2775 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2777 /*
2778 * EEPROM EIRP Maximum TX power values(unit: dbm)
2779 */
2780 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2781 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2783 /*
2784 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2785 * This is delta in 40MHZ.
2786 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2787 * TYPE: 1: Plus the delta value, 0: minus the delta value
2788 * ENABLE: enable tx power compensation for 40BW
2789 */
2790 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2791 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2792 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2793 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2794 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2795 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2797 /*
2798 * EEPROM TXPOWER 802.11BG
2799 */
2800 #define EEPROM_TXPOWER_BG_SIZE 7
2801 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2802 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2804 /*
2805 * EEPROM temperature compensation boundaries 802.11BG
2806 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2807 * reduced by (agc_step * -4)
2808 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2809 * reduced by (agc_step * -3)
2810 */
2811 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2812 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2814 /*
2815 * EEPROM temperature compensation boundaries 802.11BG
2816 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2817 * reduced by (agc_step * -2)
2818 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2819 * reduced by (agc_step * -1)
2820 */
2821 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2822 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2824 /*
2825 * EEPROM temperature compensation boundaries 802.11BG
2826 * REF: Reference TSSI value, no tx power changes needed
2827 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2828 * increased by (agc_step * 1)
2829 */
2830 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2831 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2833 /*
2834 * EEPROM temperature compensation boundaries 802.11BG
2835 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2836 * increased by (agc_step * 2)
2837 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2838 * increased by (agc_step * 3)
2839 */
2840 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2841 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2843 /*
2844 * EEPROM temperature compensation boundaries 802.11BG
2845 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2846 * increased by (agc_step * 4)
2847 * AGC_STEP: Temperature compensation step.
2848 */
2849 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2850 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2852 /*
2853 * EEPROM TXPOWER 802.11A
2854 */
2855 #define EEPROM_TXPOWER_A_SIZE 6
2856 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2857 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2859 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */
2860 #define EEPROM_TXPOWER_ALC FIELD8(0x1f)
2861 #define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0)
2863 /*
2864 * EEPROM temperature compensation boundaries 802.11A
2865 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2866 * reduced by (agc_step * -4)
2867 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2868 * reduced by (agc_step * -3)
2869 */
2870 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2871 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2873 /*
2874 * EEPROM temperature compensation boundaries 802.11A
2875 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2876 * reduced by (agc_step * -2)
2877 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2878 * reduced by (agc_step * -1)
2879 */
2880 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2881 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2883 /*
2884 * EEPROM temperature compensation boundaries 802.11A
2885 * REF: Reference TSSI value, no tx power changes needed
2886 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2887 * increased by (agc_step * 1)
2888 */
2889 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2890 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2892 /*
2893 * EEPROM temperature compensation boundaries 802.11A
2894 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2895 * increased by (agc_step * 2)
2896 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2897 * increased by (agc_step * 3)
2898 */
2899 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2900 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2902 /*
2903 * EEPROM temperature compensation boundaries 802.11A
2904 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2905 * increased by (agc_step * 4)
2906 * AGC_STEP: Temperature compensation step.
2907 */
2908 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2909 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2911 /*
2912 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2913 */
2914 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2916 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2917 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2918 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2919 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2921 /*
2922 * EEPROM BBP.
2923 */
2924 #define EEPROM_BBP_SIZE 16
2925 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2926 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2928 /* EEPROM_EXT_LNA2 */
2929 #define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff)
2930 #define EEPROM_EXT_LNA2_A2 FIELD16(0xff00)
2932 /*
2933 * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2934 */
2936 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2937 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2938 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2939 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2940 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2941 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2942 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2943 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2944 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2945 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2946 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2947 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2948 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2949 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2950 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2951 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2952 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2953 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2954 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2955 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2956 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2957 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2958 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2959 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2960 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2961 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2962 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2963 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2964 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2965 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2966 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2967 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2968 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2969 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2970 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2971 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2972 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2973 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2974 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2975 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2976 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2977 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2978 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2979 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2980 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2981 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2982 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2983 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2984 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2985 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2987 /*
2988 * MCU mailbox commands.
2989 * MCU_SLEEP - go to power-save mode.
2990 * arg1: 1: save as much power as possible, 0: save less power.
2991 * status: 1: success, 2: already asleep,
2992 * 3: maybe MAC is busy so can't finish this task.
2993 * MCU_RADIO_OFF
2994 * arg0: 0: do power-saving, NOT turn off radio.
2995 */
2996 #define MCU_SLEEP 0x30
2997 #define MCU_WAKEUP 0x31
2998 #define MCU_RADIO_OFF 0x35
2999 #define MCU_CURRENT 0x36
3000 #define MCU_LED 0x50
3001 #define MCU_LED_STRENGTH 0x51
3002 #define MCU_LED_AG_CONF 0x52
3003 #define MCU_LED_ACT_CONF 0x53
3004 #define MCU_LED_LED_POLARITY 0x54
3005 #define MCU_RADAR 0x60
3006 #define MCU_BOOT_SIGNAL 0x72
3007 #define MCU_ANT_SELECT 0X73
3008 #define MCU_FREQ_OFFSET 0x74
3009 #define MCU_BBP_SIGNAL 0x80
3010 #define MCU_POWER_SAVE 0x83
3011 #define MCU_BAND_SELECT 0x91
3013 /*
3014 * MCU mailbox tokens
3015 */
3016 #define TOKEN_SLEEP 1
3017 #define TOKEN_RADIO_OFF 2
3018 #define TOKEN_WAKEUP 3
3021 /*
3022 * DMA descriptor defines.
3023 */
3025 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
3026 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
3028 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
3029 #define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
3030 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
3032 /*
3033 * TX WI structure
3034 */
3036 /*
3037 * Word0
3038 * FRAG: 1 To inform TKIP engine this is a fragment.
3039 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
3040 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
3041 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
3042 * duplicate the frame to both channels).
3043 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
3044 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
3045 * aggregate consecutive frames with the same RA and QoS TID. If
3046 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
3047 * directly after a frame B with AMPDU=1, frame A might still
3048 * get aggregated into the AMPDU started by frame B. So, setting
3049 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
3050 * MPDU, it can still end up in an AMPDU if the previous frame
3051 * was tagged as AMPDU.
3052 */
3053 #define TXWI_W0_FRAG FIELD32(0x00000001)
3054 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
3055 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
3056 #define TXWI_W0_TS FIELD32(0x00000008)
3057 #define TXWI_W0_AMPDU FIELD32(0x00000010)
3058 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
3059 #define TXWI_W0_TX_OP FIELD32(0x00000300)
3060 #define TXWI_W0_MCS FIELD32(0x007f0000)
3061 #define TXWI_W0_BW FIELD32(0x00800000)
3062 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
3063 #define TXWI_W0_STBC FIELD32(0x06000000)
3064 #define TXWI_W0_IFS FIELD32(0x08000000)
3065 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
3067 /*
3068 * Word1
3069 * ACK: 0: No Ack needed, 1: Ack needed
3070 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
3071 * BW_WIN_SIZE: BA windows size of the recipient
3072 * WIRELESS_CLI_ID: Client ID for WCID table access
3073 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
3074 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
3075 * frame was processed. If multiple frames are aggregated together
3076 * (AMPDU==1) the reported tx status will always contain the packet
3077 * id of the first frame. 0: Don't report tx status for this frame.
3078 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
3079 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
3080 * This identification number is calculated by ((idx % 3) + 1).
3081 * The (+1) is required to prevent PACKETID to become 0.
3082 */
3083 #define TXWI_W1_ACK FIELD32(0x00000001)
3084 #define TXWI_W1_NSEQ FIELD32(0x00000002)
3085 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
3086 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
3087 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3088 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
3089 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
3090 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
3092 /*
3093 * Word2
3094 */
3095 #define TXWI_W2_IV FIELD32(0xffffffff)
3097 /*
3098 * Word3
3099 */
3100 #define TXWI_W3_EIV FIELD32(0xffffffff)
3102 /*
3103 * RX WI structure
3104 */
3106 /*
3107 * Word0
3108 */
3109 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
3110 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
3111 #define RXWI_W0_BSSID FIELD32(0x00001c00)
3112 #define RXWI_W0_UDF FIELD32(0x0000e000)
3113 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3114 #define RXWI_W0_TID FIELD32(0xf0000000)
3116 /*
3117 * Word1
3118 */
3119 #define RXWI_W1_FRAG FIELD32(0x0000000f)
3120 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
3121 #define RXWI_W1_MCS FIELD32(0x007f0000)
3122 #define RXWI_W1_BW FIELD32(0x00800000)
3123 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
3124 #define RXWI_W1_STBC FIELD32(0x06000000)
3125 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
3127 /*
3128 * Word2
3129 */
3130 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
3131 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
3132 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
3134 /*
3135 * Word3
3136 */
3137 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
3138 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
3140 /*
3141 * Macros for converting txpower from EEPROM to mac80211 value
3142 * and from mac80211 value to register value.
3143 */
3144 #define MIN_G_TXPOWER 0
3145 #define MIN_A_TXPOWER -7
3146 #define MAX_G_TXPOWER 31
3147 #define MAX_A_TXPOWER 15
3148 #define DEFAULT_TXPOWER 5
3150 #define MIN_A_TXPOWER_3593 0
3151 #define MAX_A_TXPOWER_3593 31
3153 #define TXPOWER_G_FROM_DEV(__txpower) \
3154 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
3156 #define TXPOWER_A_FROM_DEV(__txpower) \
3157 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
3159 /*
3160 * Board's maximun TX power limitation
3161 */
3162 #define EIRP_MAX_TX_POWER_LIMIT 0x50
3164 /*
3165 * Number of TBTT intervals after which we have to adjust
3166 * the hw beacon timer.
3167 */
3168 #define BCN_TBTT_OFFSET 64