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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
bloba03b5284a050952448f806d3e74cc164bea5a4a1
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30 /*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
35 #include <linux/crc-ccitt.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
39
40 #include "rt2x00.h"
41 #include "rt2800lib.h"
42 #include "rt2800.h"
43
44 /*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60 #define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
64 (__reg))
65 #define WAIT_FOR_RF(__dev, __reg) \
66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
67 #define WAIT_FOR_MCU(__dev, __reg) \
68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
69 H2M_MAILBOX_CSR_OWNER, (__reg))
70
71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 {
73 /* check for rt2872 on SoC */
74 if (!rt2x00_is_soc(rt2x00dev) ||
75 !rt2x00_rt(rt2x00dev, RT2872))
76 return false;
77
78 /* we know for sure that these rf chipsets are used on rt305x boards */
79 if (rt2x00_rf(rt2x00dev, RF3020) ||
80 rt2x00_rf(rt2x00dev, RF3021) ||
81 rt2x00_rf(rt2x00dev, RF3022))
82 return true;
83
84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
85 return false;
86 }
87
88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
89 const unsigned int word, const u8 value)
90 {
91 u32 reg;
92
93 mutex_lock(&rt2x00dev->csr_mutex);
94
95 /*
96 * Wait until the BBP becomes available, afterwards we
97 * can safely write the new data into the register.
98 */
99 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
100 reg = 0;
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
105 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
106
107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
108 }
109
110 mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112
113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
114 {
115 u32 reg;
116 u8 value;
117
118 mutex_lock(&rt2x00dev->csr_mutex);
119
120 /*
121 * Wait until the BBP becomes available, afterwards we
122 * can safely write the read request into the register.
123 * After the data has been written, we wait until hardware
124 * returns the correct value, if at any time the register
125 * doesn't become available in time, reg will be 0xffffffff
126 * which means we return 0xff to the caller.
127 */
128 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
129 reg = 0;
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
133 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
134
135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136
137 WAIT_FOR_BBP(rt2x00dev, &reg);
138 }
139
140 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141
142 mutex_unlock(&rt2x00dev->csr_mutex);
143
144 return value;
145 }
146
147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
148 const unsigned int word, const u8 value)
149 {
150 u32 reg;
151
152 mutex_lock(&rt2x00dev->csr_mutex);
153
154 /*
155 * Wait until the RFCSR becomes available, afterwards we
156 * can safely write the new data into the register.
157 */
158 switch (rt2x00dev->chip.rt) {
159 case RT6352:
160 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
161 reg = 0;
162 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
163 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
164 word);
165 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
166 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
167
168 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
169 }
170 break;
171
172 default:
173 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
174 reg = 0;
175 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
176 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
178 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179
180 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
181 }
182 break;
183 }
184
185 mutex_unlock(&rt2x00dev->csr_mutex);
186 }
187
188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
189 const unsigned int reg, const u8 value)
190 {
191 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
192 }
193
194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
195 const unsigned int reg, const u8 value)
196 {
197 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
198 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
199 }
200
201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
202 const unsigned int reg, const u8 value)
203 {
204 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
205 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
206 }
207
208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
209 const unsigned int word)
210 {
211 u32 reg;
212 u8 value;
213
214 mutex_lock(&rt2x00dev->csr_mutex);
215
216 /*
217 * Wait until the RFCSR becomes available, afterwards we
218 * can safely write the read request into the register.
219 * After the data has been written, we wait until hardware
220 * returns the correct value, if at any time the register
221 * doesn't become available in time, reg will be 0xffffffff
222 * which means we return 0xff to the caller.
223 */
224 switch (rt2x00dev->chip.rt) {
225 case RT6352:
226 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
227 reg = 0;
228 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
229 word);
230 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
231 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
232
233 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
234
235 WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
236 }
237
238 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
239 break;
240
241 default:
242 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
243 reg = 0;
244 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
245 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
246 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
247
248 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
249
250 WAIT_FOR_RFCSR(rt2x00dev, &reg);
251 }
252
253 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
254 break;
255 }
256
257 mutex_unlock(&rt2x00dev->csr_mutex);
258
259 return value;
260 }
261
262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
263 const unsigned int reg)
264 {
265 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
266 }
267
268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
269 const unsigned int word, const u32 value)
270 {
271 u32 reg;
272
273 mutex_lock(&rt2x00dev->csr_mutex);
274
275 /*
276 * Wait until the RF becomes available, afterwards we
277 * can safely write the new data into the register.
278 */
279 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
280 reg = 0;
281 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
282 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
283 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
284 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
285
286 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
287 rt2x00_rf_write(rt2x00dev, word, value);
288 }
289
290 mutex_unlock(&rt2x00dev->csr_mutex);
291 }
292
293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
294 [EEPROM_CHIP_ID] = 0x0000,
295 [EEPROM_VERSION] = 0x0001,
296 [EEPROM_MAC_ADDR_0] = 0x0002,
297 [EEPROM_MAC_ADDR_1] = 0x0003,
298 [EEPROM_MAC_ADDR_2] = 0x0004,
299 [EEPROM_NIC_CONF0] = 0x001a,
300 [EEPROM_NIC_CONF1] = 0x001b,
301 [EEPROM_FREQ] = 0x001d,
302 [EEPROM_LED_AG_CONF] = 0x001e,
303 [EEPROM_LED_ACT_CONF] = 0x001f,
304 [EEPROM_LED_POLARITY] = 0x0020,
305 [EEPROM_NIC_CONF2] = 0x0021,
306 [EEPROM_LNA] = 0x0022,
307 [EEPROM_RSSI_BG] = 0x0023,
308 [EEPROM_RSSI_BG2] = 0x0024,
309 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
310 [EEPROM_RSSI_A] = 0x0025,
311 [EEPROM_RSSI_A2] = 0x0026,
312 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
313 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
314 [EEPROM_TXPOWER_DELTA] = 0x0028,
315 [EEPROM_TXPOWER_BG1] = 0x0029,
316 [EEPROM_TXPOWER_BG2] = 0x0030,
317 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
318 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
319 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
320 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
321 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
322 [EEPROM_TXPOWER_A1] = 0x003c,
323 [EEPROM_TXPOWER_A2] = 0x0053,
324 [EEPROM_TXPOWER_INIT] = 0x0068,
325 [EEPROM_TSSI_BOUND_A1] = 0x006a,
326 [EEPROM_TSSI_BOUND_A2] = 0x006b,
327 [EEPROM_TSSI_BOUND_A3] = 0x006c,
328 [EEPROM_TSSI_BOUND_A4] = 0x006d,
329 [EEPROM_TSSI_BOUND_A5] = 0x006e,
330 [EEPROM_TXPOWER_BYRATE] = 0x006f,
331 [EEPROM_BBP_START] = 0x0078,
332 };
333
334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
335 [EEPROM_CHIP_ID] = 0x0000,
336 [EEPROM_VERSION] = 0x0001,
337 [EEPROM_MAC_ADDR_0] = 0x0002,
338 [EEPROM_MAC_ADDR_1] = 0x0003,
339 [EEPROM_MAC_ADDR_2] = 0x0004,
340 [EEPROM_NIC_CONF0] = 0x001a,
341 [EEPROM_NIC_CONF1] = 0x001b,
342 [EEPROM_NIC_CONF2] = 0x001c,
343 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
344 [EEPROM_FREQ] = 0x0022,
345 [EEPROM_LED_AG_CONF] = 0x0023,
346 [EEPROM_LED_ACT_CONF] = 0x0024,
347 [EEPROM_LED_POLARITY] = 0x0025,
348 [EEPROM_LNA] = 0x0026,
349 [EEPROM_EXT_LNA2] = 0x0027,
350 [EEPROM_RSSI_BG] = 0x0028,
351 [EEPROM_RSSI_BG2] = 0x0029,
352 [EEPROM_RSSI_A] = 0x002a,
353 [EEPROM_RSSI_A2] = 0x002b,
354 [EEPROM_TXPOWER_BG1] = 0x0030,
355 [EEPROM_TXPOWER_BG2] = 0x0037,
356 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
357 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
358 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
359 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
360 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
361 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
362 [EEPROM_TXPOWER_A1] = 0x004b,
363 [EEPROM_TXPOWER_A2] = 0x0065,
364 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
365 [EEPROM_TSSI_BOUND_A1] = 0x009a,
366 [EEPROM_TSSI_BOUND_A2] = 0x009b,
367 [EEPROM_TSSI_BOUND_A3] = 0x009c,
368 [EEPROM_TSSI_BOUND_A4] = 0x009d,
369 [EEPROM_TSSI_BOUND_A5] = 0x009e,
370 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
371 };
372
373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
374 const enum rt2800_eeprom_word word)
375 {
376 const unsigned int *map;
377 unsigned int index;
378
379 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
380 "%s: invalid EEPROM word %d\n",
381 wiphy_name(rt2x00dev->hw->wiphy), word))
382 return 0;
383
384 if (rt2x00_rt(rt2x00dev, RT3593))
385 map = rt2800_eeprom_map_ext;
386 else
387 map = rt2800_eeprom_map;
388
389 index = map[word];
390
391 /* Index 0 is valid only for EEPROM_CHIP_ID.
392 * Otherwise it means that the offset of the
393 * given word is not initialized in the map,
394 * or that the field is not usable on the
395 * actual chipset.
396 */
397 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
398 "%s: invalid access of EEPROM word %d\n",
399 wiphy_name(rt2x00dev->hw->wiphy), word);
400
401 return index;
402 }
403
404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
405 const enum rt2800_eeprom_word word)
406 {
407 unsigned int index;
408
409 index = rt2800_eeprom_word_index(rt2x00dev, word);
410 return rt2x00_eeprom_addr(rt2x00dev, index);
411 }
412
413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
414 const enum rt2800_eeprom_word word)
415 {
416 unsigned int index;
417
418 index = rt2800_eeprom_word_index(rt2x00dev, word);
419 return rt2x00_eeprom_read(rt2x00dev, index);
420 }
421
422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
423 const enum rt2800_eeprom_word word, u16 data)
424 {
425 unsigned int index;
426
427 index = rt2800_eeprom_word_index(rt2x00dev, word);
428 rt2x00_eeprom_write(rt2x00dev, index, data);
429 }
430
431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
432 const enum rt2800_eeprom_word array,
433 unsigned int offset)
434 {
435 unsigned int index;
436
437 index = rt2800_eeprom_word_index(rt2x00dev, array);
438 return rt2x00_eeprom_read(rt2x00dev, index + offset);
439 }
440
441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
442 {
443 u32 reg;
444 int i, count;
445
446 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
447 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
448 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
449 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
450 rt2x00_set_field32(&reg, WLAN_EN, 1);
451 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
452
453 udelay(REGISTER_BUSY_DELAY);
454
455 count = 0;
456 do {
457 /*
458 * Check PLL_LD & XTAL_RDY.
459 */
460 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
461 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
462 if (rt2x00_get_field32(reg, PLL_LD) &&
463 rt2x00_get_field32(reg, XTAL_RDY))
464 break;
465 udelay(REGISTER_BUSY_DELAY);
466 }
467
468 if (i >= REGISTER_BUSY_COUNT) {
469
470 if (count >= 10)
471 return -EIO;
472
473 rt2800_register_write(rt2x00dev, 0x58, 0x018);
474 udelay(REGISTER_BUSY_DELAY);
475 rt2800_register_write(rt2x00dev, 0x58, 0x418);
476 udelay(REGISTER_BUSY_DELAY);
477 rt2800_register_write(rt2x00dev, 0x58, 0x618);
478 udelay(REGISTER_BUSY_DELAY);
479 count++;
480 } else {
481 count = 0;
482 }
483
484 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
485 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
486 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
487 rt2x00_set_field32(&reg, WLAN_RESET, 1);
488 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
489 udelay(10);
490 rt2x00_set_field32(&reg, WLAN_RESET, 0);
491 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
492 udelay(10);
493 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
494 } while (count != 0);
495
496 return 0;
497 }
498
499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
500 const u8 command, const u8 token,
501 const u8 arg0, const u8 arg1)
502 {
503 u32 reg;
504
505 /*
506 * SOC devices don't support MCU requests.
507 */
508 if (rt2x00_is_soc(rt2x00dev))
509 return;
510
511 mutex_lock(&rt2x00dev->csr_mutex);
512
513 /*
514 * Wait until the MCU becomes available, afterwards we
515 * can safely write the new data into the register.
516 */
517 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
518 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
519 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
520 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
521 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
522 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
523
524 reg = 0;
525 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
526 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
527 }
528
529 mutex_unlock(&rt2x00dev->csr_mutex);
530 }
531 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
532
533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
534 {
535 unsigned int i = 0;
536 u32 reg;
537
538 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
539 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
540 if (reg && reg != ~0)
541 return 0;
542 msleep(1);
543 }
544
545 rt2x00_err(rt2x00dev, "Unstable hardware\n");
546 return -EBUSY;
547 }
548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
549
550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
551 {
552 unsigned int i;
553 u32 reg;
554
555 /*
556 * Some devices are really slow to respond here. Wait a whole second
557 * before timing out.
558 */
559 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
560 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
561 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
562 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
563 return 0;
564
565 msleep(10);
566 }
567
568 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
569 return -EACCES;
570 }
571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
572
573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
574 {
575 u32 reg;
576
577 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
578 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
579 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
580 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
581 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
582 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
583 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
584 }
585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
586
587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
588 unsigned short *txwi_size,
589 unsigned short *rxwi_size)
590 {
591 switch (rt2x00dev->chip.rt) {
592 case RT3593:
593 *txwi_size = TXWI_DESC_SIZE_4WORDS;
594 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
595 break;
596
597 case RT5592:
598 case RT6352:
599 *txwi_size = TXWI_DESC_SIZE_5WORDS;
600 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
601 break;
602
603 default:
604 *txwi_size = TXWI_DESC_SIZE_4WORDS;
605 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
606 break;
607 }
608 }
609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
610
611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
612 {
613 u16 fw_crc;
614 u16 crc;
615
616 /*
617 * The last 2 bytes in the firmware array are the crc checksum itself,
618 * this means that we should never pass those 2 bytes to the crc
619 * algorithm.
620 */
621 fw_crc = (data[len - 2] << 8 | data[len - 1]);
622
623 /*
624 * Use the crc ccitt algorithm.
625 * This will return the same value as the legacy driver which
626 * used bit ordering reversion on the both the firmware bytes
627 * before input input as well as on the final output.
628 * Obviously using crc ccitt directly is much more efficient.
629 */
630 crc = crc_ccitt(~0, data, len - 2);
631
632 /*
633 * There is a small difference between the crc-itu-t + bitrev and
634 * the crc-ccitt crc calculation. In the latter method the 2 bytes
635 * will be swapped, use swab16 to convert the crc to the correct
636 * value.
637 */
638 crc = swab16(crc);
639
640 return fw_crc == crc;
641 }
642
643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
644 const u8 *data, const size_t len)
645 {
646 size_t offset = 0;
647 size_t fw_len;
648 bool multiple;
649
650 /*
651 * PCI(e) & SOC devices require firmware with a length
652 * of 8kb. USB devices require firmware files with a length
653 * of 4kb. Certain USB chipsets however require different firmware,
654 * which Ralink only provides attached to the original firmware
655 * file. Thus for USB devices, firmware files have a length
656 * which is a multiple of 4kb. The firmware for rt3290 chip also
657 * have a length which is a multiple of 4kb.
658 */
659 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
660 fw_len = 4096;
661 else
662 fw_len = 8192;
663
664 multiple = true;
665 /*
666 * Validate the firmware length
667 */
668 if (len != fw_len && (!multiple || (len % fw_len) != 0))
669 return FW_BAD_LENGTH;
670
671 /*
672 * Check if the chipset requires one of the upper parts
673 * of the firmware.
674 */
675 if (rt2x00_is_usb(rt2x00dev) &&
676 !rt2x00_rt(rt2x00dev, RT2860) &&
677 !rt2x00_rt(rt2x00dev, RT2872) &&
678 !rt2x00_rt(rt2x00dev, RT3070) &&
679 ((len / fw_len) == 1))
680 return FW_BAD_VERSION;
681
682 /*
683 * 8kb firmware files must be checked as if it were
684 * 2 separate firmware files.
685 */
686 while (offset < len) {
687 if (!rt2800_check_firmware_crc(data + offset, fw_len))
688 return FW_BAD_CRC;
689
690 offset += fw_len;
691 }
692
693 return FW_OK;
694 }
695 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
696
697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
698 const u8 *data, const size_t len)
699 {
700 unsigned int i;
701 u32 reg;
702 int retval;
703
704 if (rt2x00_rt(rt2x00dev, RT3290)) {
705 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
706 if (retval)
707 return -EBUSY;
708 }
709
710 /*
711 * If driver doesn't wake up firmware here,
712 * rt2800_load_firmware will hang forever when interface is up again.
713 */
714 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
715
716 /*
717 * Wait for stable hardware.
718 */
719 if (rt2800_wait_csr_ready(rt2x00dev))
720 return -EBUSY;
721
722 if (rt2x00_is_pci(rt2x00dev)) {
723 if (rt2x00_rt(rt2x00dev, RT3290) ||
724 rt2x00_rt(rt2x00dev, RT3572) ||
725 rt2x00_rt(rt2x00dev, RT5390) ||
726 rt2x00_rt(rt2x00dev, RT5392)) {
727 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
728 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
729 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
730 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
731 }
732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
733 }
734
735 rt2800_disable_wpdma(rt2x00dev);
736
737 /*
738 * Write firmware to the device.
739 */
740 rt2800_drv_write_firmware(rt2x00dev, data, len);
741
742 /*
743 * Wait for device to stabilize.
744 */
745 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
746 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
747 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
748 break;
749 msleep(1);
750 }
751
752 if (i == REGISTER_BUSY_COUNT) {
753 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
754 return -EBUSY;
755 }
756
757 /*
758 * Disable DMA, will be reenabled later when enabling
759 * the radio.
760 */
761 rt2800_disable_wpdma(rt2x00dev);
762
763 /*
764 * Initialize firmware.
765 */
766 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
767 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
768 if (rt2x00_is_usb(rt2x00dev)) {
769 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
770 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
771 }
772 msleep(1);
773
774 return 0;
775 }
776 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
777
778 void rt2800_write_tx_data(struct queue_entry *entry,
779 struct txentry_desc *txdesc)
780 {
781 __le32 *txwi = rt2800_drv_get_txwi(entry);
782 u32 word;
783 int i;
784
785 /*
786 * Initialize TX Info descriptor
787 */
788 word = rt2x00_desc_read(txwi, 0);
789 rt2x00_set_field32(&word, TXWI_W0_FRAG,
790 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
791 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
792 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
793 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
794 rt2x00_set_field32(&word, TXWI_W0_TS,
795 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
796 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
797 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
798 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
799 txdesc->u.ht.mpdu_density);
800 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
801 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
802 rt2x00_set_field32(&word, TXWI_W0_BW,
803 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
804 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
805 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
806 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
807 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
808 rt2x00_desc_write(txwi, 0, word);
809
810 word = rt2x00_desc_read(txwi, 1);
811 rt2x00_set_field32(&word, TXWI_W1_ACK,
812 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
813 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
814 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
815 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
816 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
817 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
818 txdesc->key_idx : txdesc->u.ht.wcid);
819 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
820 txdesc->length);
821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
822 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
823 rt2x00_desc_write(txwi, 1, word);
824
825 /*
826 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
827 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
828 * When TXD_W3_WIV is set to 1 it will use the IV data
829 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
830 * crypto entry in the registers should be used to encrypt the frame.
831 *
832 * Nulify all remaining words as well, we don't know how to program them.
833 */
834 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
835 _rt2x00_desc_write(txwi, i, 0);
836 }
837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
838
839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
840 {
841 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
842 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
843 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
844 u16 eeprom;
845 u8 offset0;
846 u8 offset1;
847 u8 offset2;
848
849 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
850 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
851 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
852 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
853 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
854 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
855 } else {
856 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
857 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
858 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
859 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
860 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
861 }
862
863 /*
864 * Convert the value from the descriptor into the RSSI value
865 * If the value in the descriptor is 0, it is considered invalid
866 * and the default (extremely low) rssi value is assumed
867 */
868 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
869 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
870 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
871
872 /*
873 * mac80211 only accepts a single RSSI value. Calculating the
874 * average doesn't deliver a fair answer either since -60:-60 would
875 * be considered equally good as -50:-70 while the second is the one
876 * which gives less energy...
877 */
878 rssi0 = max(rssi0, rssi1);
879 return (int)max(rssi0, rssi2);
880 }
881
882 void rt2800_process_rxwi(struct queue_entry *entry,
883 struct rxdone_entry_desc *rxdesc)
884 {
885 __le32 *rxwi = (__le32 *) entry->skb->data;
886 u32 word;
887
888 word = rt2x00_desc_read(rxwi, 0);
889
890 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
891 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
892
893 word = rt2x00_desc_read(rxwi, 1);
894
895 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
896 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
897
898 if (rt2x00_get_field32(word, RXWI_W1_BW))
899 rxdesc->bw = RATE_INFO_BW_40;
900
901 /*
902 * Detect RX rate, always use MCS as signal type.
903 */
904 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
905 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
906 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
907
908 /*
909 * Mask of 0x8 bit to remove the short preamble flag.
910 */
911 if (rxdesc->rate_mode == RATE_MODE_CCK)
912 rxdesc->signal &= ~0x8;
913
914 word = rt2x00_desc_read(rxwi, 2);
915
916 /*
917 * Convert descriptor AGC value to RSSI value.
918 */
919 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
920 /*
921 * Remove RXWI descriptor from start of the buffer.
922 */
923 skb_pull(entry->skb, entry->queue->winfo_size);
924 }
925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
926
927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
928 u32 status, enum nl80211_band band)
929 {
930 u8 flags = 0;
931 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
932
933 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
934 case RATE_MODE_HT_GREENFIELD:
935 flags |= IEEE80211_TX_RC_GREEN_FIELD;
936 /* fall through */
937 case RATE_MODE_HT_MIX:
938 flags |= IEEE80211_TX_RC_MCS;
939 break;
940 case RATE_MODE_OFDM:
941 if (band == NL80211_BAND_2GHZ)
942 idx += 4;
943 break;
944 case RATE_MODE_CCK:
945 if (idx >= 8)
946 idx -= 8;
947 break;
948 }
949
950 if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
951 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
952
953 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
954 flags |= IEEE80211_TX_RC_SHORT_GI;
955
956 skbdesc->tx_rate_idx = idx;
957 skbdesc->tx_rate_flags = flags;
958 }
959
960 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
961 {
962 __le32 *txwi;
963 u32 word;
964 int wcid, ack, pid;
965 int tx_wcid, tx_ack, tx_pid, is_agg;
966
967 /*
968 * This frames has returned with an IO error,
969 * so the status report is not intended for this
970 * frame.
971 */
972 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
973 return false;
974
975 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
976 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
977 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
978 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
979
980 /*
981 * Validate if this TX status report is intended for
982 * this entry by comparing the WCID/ACK/PID fields.
983 */
984 txwi = rt2800_drv_get_txwi(entry);
985
986 word = rt2x00_desc_read(txwi, 1);
987 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
988 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
989 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
990
991 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
992 rt2x00_dbg(entry->queue->rt2x00dev,
993 "TX status report missed for queue %d entry %d\n",
994 entry->queue->qid, entry->entry_idx);
995 return false;
996 }
997
998 return true;
999 }
1000
1001 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
1002 bool match)
1003 {
1004 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1005 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1006 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1007 struct txdone_entry_desc txdesc;
1008 u32 word;
1009 u16 mcs, real_mcs;
1010 int aggr, ampdu, wcid, ack_req;
1011
1012 /*
1013 * Obtain the status about this packet.
1014 */
1015 txdesc.flags = 0;
1016 word = rt2x00_desc_read(txwi, 0);
1017
1018 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1019 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1020
1021 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1022 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1023 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1024 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1025
1026 /*
1027 * If a frame was meant to be sent as a single non-aggregated MPDU
1028 * but ended up in an aggregate the used tx rate doesn't correlate
1029 * with the one specified in the TXWI as the whole aggregate is sent
1030 * with the same rate.
1031 *
1032 * For example: two frames are sent to rt2x00, the first one sets
1033 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1034 * and requests MCS15. If the hw aggregates both frames into one
1035 * AMDPU the tx status for both frames will contain MCS7 although
1036 * the frame was sent successfully.
1037 *
1038 * Hence, replace the requested rate with the real tx rate to not
1039 * confuse the rate control algortihm by providing clearly wrong
1040 * data.
1041 *
1042 * FIXME: if we do not find matching entry, we tell that frame was
1043 * posted without any retries. We need to find a way to fix that
1044 * and provide retry count.
1045 */
1046 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1047 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1048 mcs = real_mcs;
1049 }
1050
1051 if (aggr == 1 || ampdu == 1)
1052 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1053
1054 if (!ack_req)
1055 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1056
1057 /*
1058 * Ralink has a retry mechanism using a global fallback
1059 * table. We setup this fallback table to try the immediate
1060 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1061 * always contains the MCS used for the last transmission, be
1062 * it successful or not.
1063 */
1064 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1065 /*
1066 * Transmission succeeded. The number of retries is
1067 * mcs - real_mcs
1068 */
1069 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1070 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1071 } else {
1072 /*
1073 * Transmission failed. The number of retries is
1074 * always 7 in this case (for a total number of 8
1075 * frames sent).
1076 */
1077 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1078 txdesc.retry = rt2x00dev->long_retry;
1079 }
1080
1081 /*
1082 * the frame was retried at least once
1083 * -> hw used fallback rates
1084 */
1085 if (txdesc.retry)
1086 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1087
1088 if (!match) {
1089 /* RCU assures non-null sta will not be freed by mac80211. */
1090 rcu_read_lock();
1091 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1092 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1093 else
1094 skbdesc->sta = NULL;
1095 rt2x00lib_txdone_nomatch(entry, &txdesc);
1096 rcu_read_unlock();
1097 } else {
1098 rt2x00lib_txdone(entry, &txdesc);
1099 }
1100 }
1101 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1102
1103 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
1104 {
1105 struct data_queue *queue;
1106 struct queue_entry *entry;
1107 u32 reg;
1108 u8 qid;
1109 bool match;
1110
1111 while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1112 /*
1113 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1114 * guaranteed to be one of the TX QIDs .
1115 */
1116 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1117 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1118
1119 if (unlikely(rt2x00queue_empty(queue))) {
1120 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1121 qid);
1122 break;
1123 }
1124
1125 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1126
1127 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1128 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1129 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1130 entry->entry_idx, qid);
1131 break;
1132 }
1133
1134 match = rt2800_txdone_entry_check(entry, reg);
1135 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1136 }
1137 }
1138 EXPORT_SYMBOL_GPL(rt2800_txdone);
1139
1140 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1141 struct queue_entry *entry)
1142 {
1143 bool ret;
1144 unsigned long tout;
1145
1146 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1147 return false;
1148
1149 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1150 tout = msecs_to_jiffies(50);
1151 else
1152 tout = msecs_to_jiffies(2000);
1153
1154 ret = time_after(jiffies, entry->last_action + tout);
1155 if (unlikely(ret))
1156 rt2x00_dbg(entry->queue->rt2x00dev,
1157 "TX status timeout for entry %d in queue %d\n",
1158 entry->entry_idx, entry->queue->qid);
1159 return ret;
1160 }
1161
1162 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1163 {
1164 struct data_queue *queue;
1165 struct queue_entry *entry;
1166
1167 if (!test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) {
1168 unsigned long tout = msecs_to_jiffies(1000);
1169
1170 if (time_before(jiffies, rt2x00dev->last_nostatus_check + tout))
1171 return false;
1172 }
1173
1174 rt2x00dev->last_nostatus_check = jiffies;
1175
1176 tx_queue_for_each(rt2x00dev, queue) {
1177 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1178 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1179 return true;
1180 }
1181
1182 return false;
1183 }
1184 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1185
1186 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1187 {
1188 struct data_queue *queue;
1189 struct queue_entry *entry;
1190
1191 /*
1192 * Process any trailing TX status reports for IO failures,
1193 * we loop until we find the first non-IO error entry. This
1194 * can either be a frame which is free, is being uploaded,
1195 * or has completed the upload but didn't have an entry
1196 * in the TX_STAT_FIFO register yet.
1197 */
1198 tx_queue_for_each(rt2x00dev, queue) {
1199 while (!rt2x00queue_empty(queue)) {
1200 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1201
1202 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1203 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1204 break;
1205
1206 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1207 rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1208 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1209 else
1210 break;
1211 }
1212 }
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1215
1216 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1217 unsigned int index)
1218 {
1219 return HW_BEACON_BASE(index);
1220 }
1221
1222 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1223 unsigned int index)
1224 {
1225 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1226 }
1227
1228 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1229 {
1230 struct data_queue *queue = rt2x00dev->bcn;
1231 struct queue_entry *entry;
1232 int i, bcn_num = 0;
1233 u64 off, reg = 0;
1234 u32 bssid_dw1;
1235
1236 /*
1237 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1238 */
1239 for (i = 0; i < queue->limit; i++) {
1240 entry = &queue->entries[i];
1241 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1242 continue;
1243 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1244 reg |= off << (8 * bcn_num);
1245 bcn_num++;
1246 }
1247
1248 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1249 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1250
1251 /*
1252 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1253 */
1254 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1255 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1256 bcn_num > 0 ? bcn_num - 1 : 0);
1257 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1258 }
1259
1260 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1261 {
1262 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1263 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1264 unsigned int beacon_base;
1265 unsigned int padding_len;
1266 u32 orig_reg, reg;
1267 const int txwi_desc_size = entry->queue->winfo_size;
1268
1269 /*
1270 * Disable beaconing while we are reloading the beacon data,
1271 * otherwise we might be sending out invalid data.
1272 */
1273 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1274 orig_reg = reg;
1275 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1276 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1277
1278 /*
1279 * Add space for the TXWI in front of the skb.
1280 */
1281 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1282
1283 /*
1284 * Register descriptor details in skb frame descriptor.
1285 */
1286 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1287 skbdesc->desc = entry->skb->data;
1288 skbdesc->desc_len = txwi_desc_size;
1289
1290 /*
1291 * Add the TXWI for the beacon to the skb.
1292 */
1293 rt2800_write_tx_data(entry, txdesc);
1294
1295 /*
1296 * Dump beacon to userspace through debugfs.
1297 */
1298 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1299
1300 /*
1301 * Write entire beacon with TXWI and padding to register.
1302 */
1303 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1304 if (padding_len && skb_pad(entry->skb, padding_len)) {
1305 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1306 /* skb freed by skb_pad() on failure */
1307 entry->skb = NULL;
1308 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1309 return;
1310 }
1311
1312 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1313
1314 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1315 entry->skb->len + padding_len);
1316 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1317
1318 /*
1319 * Change global beacons settings.
1320 */
1321 rt2800_update_beacons_setup(rt2x00dev);
1322
1323 /*
1324 * Restore beaconing state.
1325 */
1326 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1327
1328 /*
1329 * Clean up beacon skb.
1330 */
1331 dev_kfree_skb_any(entry->skb);
1332 entry->skb = NULL;
1333 }
1334 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1335
1336 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1337 unsigned int index)
1338 {
1339 int i;
1340 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1341 unsigned int beacon_base;
1342
1343 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1344
1345 /*
1346 * For the Beacon base registers we only need to clear
1347 * the whole TXWI which (when set to 0) will invalidate
1348 * the entire beacon.
1349 */
1350 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1351 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1352 }
1353
1354 void rt2800_clear_beacon(struct queue_entry *entry)
1355 {
1356 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1357 u32 orig_reg, reg;
1358
1359 /*
1360 * Disable beaconing while we are reloading the beacon data,
1361 * otherwise we might be sending out invalid data.
1362 */
1363 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1364 reg = orig_reg;
1365 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1366 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1367
1368 /*
1369 * Clear beacon.
1370 */
1371 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1372 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1373
1374 /*
1375 * Change global beacons settings.
1376 */
1377 rt2800_update_beacons_setup(rt2x00dev);
1378 /*
1379 * Restore beaconing state.
1380 */
1381 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1382 }
1383 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1384
1385 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1386 const struct rt2x00debug rt2800_rt2x00debug = {
1387 .owner = THIS_MODULE,
1388 .csr = {
1389 .read = rt2800_register_read,
1390 .write = rt2800_register_write,
1391 .flags = RT2X00DEBUGFS_OFFSET,
1392 .word_base = CSR_REG_BASE,
1393 .word_size = sizeof(u32),
1394 .word_count = CSR_REG_SIZE / sizeof(u32),
1395 },
1396 .eeprom = {
1397 /* NOTE: The local EEPROM access functions can't
1398 * be used here, use the generic versions instead.
1399 */
1400 .read = rt2x00_eeprom_read,
1401 .write = rt2x00_eeprom_write,
1402 .word_base = EEPROM_BASE,
1403 .word_size = sizeof(u16),
1404 .word_count = EEPROM_SIZE / sizeof(u16),
1405 },
1406 .bbp = {
1407 .read = rt2800_bbp_read,
1408 .write = rt2800_bbp_write,
1409 .word_base = BBP_BASE,
1410 .word_size = sizeof(u8),
1411 .word_count = BBP_SIZE / sizeof(u8),
1412 },
1413 .rf = {
1414 .read = rt2x00_rf_read,
1415 .write = rt2800_rf_write,
1416 .word_base = RF_BASE,
1417 .word_size = sizeof(u32),
1418 .word_count = RF_SIZE / sizeof(u32),
1419 },
1420 .rfcsr = {
1421 .read = rt2800_rfcsr_read,
1422 .write = rt2800_rfcsr_write,
1423 .word_base = RFCSR_BASE,
1424 .word_size = sizeof(u8),
1425 .word_count = RFCSR_SIZE / sizeof(u8),
1426 },
1427 };
1428 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1429 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1430
1431 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1432 {
1433 u32 reg;
1434
1435 if (rt2x00_rt(rt2x00dev, RT3290)) {
1436 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1437 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1438 } else {
1439 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1440 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1441 }
1442 }
1443 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1444
1445 #ifdef CONFIG_RT2X00_LIB_LEDS
1446 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1447 enum led_brightness brightness)
1448 {
1449 struct rt2x00_led *led =
1450 container_of(led_cdev, struct rt2x00_led, led_dev);
1451 unsigned int enabled = brightness != LED_OFF;
1452 unsigned int bg_mode =
1453 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1454 unsigned int polarity =
1455 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1456 EEPROM_FREQ_LED_POLARITY);
1457 unsigned int ledmode =
1458 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1459 EEPROM_FREQ_LED_MODE);
1460 u32 reg;
1461
1462 /* Check for SoC (SOC devices don't support MCU requests) */
1463 if (rt2x00_is_soc(led->rt2x00dev)) {
1464 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1465
1466 /* Set LED Polarity */
1467 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1468
1469 /* Set LED Mode */
1470 if (led->type == LED_TYPE_RADIO) {
1471 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1472 enabled ? 3 : 0);
1473 } else if (led->type == LED_TYPE_ASSOC) {
1474 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1475 enabled ? 3 : 0);
1476 } else if (led->type == LED_TYPE_QUALITY) {
1477 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1478 enabled ? 3 : 0);
1479 }
1480
1481 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1482
1483 } else {
1484 if (led->type == LED_TYPE_RADIO) {
1485 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1486 enabled ? 0x20 : 0);
1487 } else if (led->type == LED_TYPE_ASSOC) {
1488 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1489 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1490 } else if (led->type == LED_TYPE_QUALITY) {
1491 /*
1492 * The brightness is divided into 6 levels (0 - 5),
1493 * The specs tell us the following levels:
1494 * 0, 1 ,3, 7, 15, 31
1495 * to determine the level in a simple way we can simply
1496 * work with bitshifting:
1497 * (1 << level) - 1
1498 */
1499 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1500 (1 << brightness / (LED_FULL / 6)) - 1,
1501 polarity);
1502 }
1503 }
1504 }
1505
1506 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1507 struct rt2x00_led *led, enum led_type type)
1508 {
1509 led->rt2x00dev = rt2x00dev;
1510 led->type = type;
1511 led->led_dev.brightness_set = rt2800_brightness_set;
1512 led->flags = LED_INITIALIZED;
1513 }
1514 #endif /* CONFIG_RT2X00_LIB_LEDS */
1515
1516 /*
1517 * Configuration handlers.
1518 */
1519 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1520 const u8 *address,
1521 int wcid)
1522 {
1523 struct mac_wcid_entry wcid_entry;
1524 u32 offset;
1525
1526 offset = MAC_WCID_ENTRY(wcid);
1527
1528 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1529 if (address)
1530 memcpy(wcid_entry.mac, address, ETH_ALEN);
1531
1532 rt2800_register_multiwrite(rt2x00dev, offset,
1533 &wcid_entry, sizeof(wcid_entry));
1534 }
1535
1536 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1537 {
1538 u32 offset;
1539 offset = MAC_WCID_ATTR_ENTRY(wcid);
1540 rt2800_register_write(rt2x00dev, offset, 0);
1541 }
1542
1543 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1544 int wcid, u32 bssidx)
1545 {
1546 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1547 u32 reg;
1548
1549 /*
1550 * The BSS Idx numbers is split in a main value of 3 bits,
1551 * and a extended field for adding one additional bit to the value.
1552 */
1553 reg = rt2800_register_read(rt2x00dev, offset);
1554 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1555 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1556 (bssidx & 0x8) >> 3);
1557 rt2800_register_write(rt2x00dev, offset, reg);
1558 }
1559
1560 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1561 struct rt2x00lib_crypto *crypto,
1562 struct ieee80211_key_conf *key)
1563 {
1564 struct mac_iveiv_entry iveiv_entry;
1565 u32 offset;
1566 u32 reg;
1567
1568 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1569
1570 if (crypto->cmd == SET_KEY) {
1571 reg = rt2800_register_read(rt2x00dev, offset);
1572 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1573 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1574 /*
1575 * Both the cipher as the BSS Idx numbers are split in a main
1576 * value of 3 bits, and a extended field for adding one additional
1577 * bit to the value.
1578 */
1579 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1580 (crypto->cipher & 0x7));
1581 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1582 (crypto->cipher & 0x8) >> 3);
1583 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1584 rt2800_register_write(rt2x00dev, offset, reg);
1585 } else {
1586 /* Delete the cipher without touching the bssidx */
1587 reg = rt2800_register_read(rt2x00dev, offset);
1588 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1589 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1590 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1591 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1592 rt2800_register_write(rt2x00dev, offset, reg);
1593 }
1594
1595 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1596
1597 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1598 if ((crypto->cipher == CIPHER_TKIP) ||
1599 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1600 (crypto->cipher == CIPHER_AES))
1601 iveiv_entry.iv[3] |= 0x20;
1602 iveiv_entry.iv[3] |= key->keyidx << 6;
1603 rt2800_register_multiwrite(rt2x00dev, offset,
1604 &iveiv_entry, sizeof(iveiv_entry));
1605 }
1606
1607 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1608 struct rt2x00lib_crypto *crypto,
1609 struct ieee80211_key_conf *key)
1610 {
1611 struct hw_key_entry key_entry;
1612 struct rt2x00_field32 field;
1613 u32 offset;
1614 u32 reg;
1615
1616 if (crypto->cmd == SET_KEY) {
1617 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1618
1619 memcpy(key_entry.key, crypto->key,
1620 sizeof(key_entry.key));
1621 memcpy(key_entry.tx_mic, crypto->tx_mic,
1622 sizeof(key_entry.tx_mic));
1623 memcpy(key_entry.rx_mic, crypto->rx_mic,
1624 sizeof(key_entry.rx_mic));
1625
1626 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1627 rt2800_register_multiwrite(rt2x00dev, offset,
1628 &key_entry, sizeof(key_entry));
1629 }
1630
1631 /*
1632 * The cipher types are stored over multiple registers
1633 * starting with SHARED_KEY_MODE_BASE each word will have
1634 * 32 bits and contains the cipher types for 2 bssidx each.
1635 * Using the correct defines correctly will cause overhead,
1636 * so just calculate the correct offset.
1637 */
1638 field.bit_offset = 4 * (key->hw_key_idx % 8);
1639 field.bit_mask = 0x7 << field.bit_offset;
1640
1641 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1642
1643 reg = rt2800_register_read(rt2x00dev, offset);
1644 rt2x00_set_field32(&reg, field,
1645 (crypto->cmd == SET_KEY) * crypto->cipher);
1646 rt2800_register_write(rt2x00dev, offset, reg);
1647
1648 /*
1649 * Update WCID information
1650 */
1651 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1652 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1653 crypto->bssidx);
1654 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1655
1656 return 0;
1657 }
1658 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1659
1660 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1661 struct rt2x00lib_crypto *crypto,
1662 struct ieee80211_key_conf *key)
1663 {
1664 struct hw_key_entry key_entry;
1665 u32 offset;
1666
1667 if (crypto->cmd == SET_KEY) {
1668 /*
1669 * Allow key configuration only for STAs that are
1670 * known by the hw.
1671 */
1672 if (crypto->wcid > WCID_END)
1673 return -ENOSPC;
1674 key->hw_key_idx = crypto->wcid;
1675
1676 memcpy(key_entry.key, crypto->key,
1677 sizeof(key_entry.key));
1678 memcpy(key_entry.tx_mic, crypto->tx_mic,
1679 sizeof(key_entry.tx_mic));
1680 memcpy(key_entry.rx_mic, crypto->rx_mic,
1681 sizeof(key_entry.rx_mic));
1682
1683 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1684 rt2800_register_multiwrite(rt2x00dev, offset,
1685 &key_entry, sizeof(key_entry));
1686 }
1687
1688 /*
1689 * Update WCID information
1690 */
1691 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1692
1693 return 0;
1694 }
1695 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1696
1697 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1698 {
1699 u8 i, max_psdu;
1700 u32 reg;
1701 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1702
1703 for (i = 0; i < 3; i++)
1704 if (drv_data->ampdu_factor_cnt[i] > 0)
1705 break;
1706
1707 max_psdu = min(drv_data->max_psdu, i);
1708
1709 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1710 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1711 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1712 }
1713
1714 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1715 struct ieee80211_sta *sta)
1716 {
1717 struct rt2x00_dev *rt2x00dev = hw->priv;
1718 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1719 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1720 int wcid;
1721
1722 /*
1723 * Limit global maximum TX AMPDU length to smallest value of all
1724 * connected stations. In AP mode this can be suboptimal, but we
1725 * do not have a choice if some connected STA is not capable to
1726 * receive the same amount of data like the others.
1727 */
1728 if (sta->ht_cap.ht_supported) {
1729 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1730 rt2800_set_max_psdu_len(rt2x00dev);
1731 }
1732
1733 /*
1734 * Search for the first free WCID entry and return the corresponding
1735 * index.
1736 */
1737 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1738
1739 /*
1740 * Store selected wcid even if it is invalid so that we can
1741 * later decide if the STA is uploaded into the hw.
1742 */
1743 sta_priv->wcid = wcid;
1744
1745 /*
1746 * No space left in the device, however, we can still communicate
1747 * with the STA -> No error.
1748 */
1749 if (wcid > WCID_END)
1750 return 0;
1751
1752 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1753 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1754
1755 /*
1756 * Clean up WCID attributes and write STA address to the device.
1757 */
1758 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1759 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1760 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1761 rt2x00lib_get_bssidx(rt2x00dev, vif));
1762 return 0;
1763 }
1764 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1765
1766 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1767 struct ieee80211_sta *sta)
1768 {
1769 struct rt2x00_dev *rt2x00dev = hw->priv;
1770 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1771 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1772 int wcid = sta_priv->wcid;
1773
1774 if (sta->ht_cap.ht_supported) {
1775 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1776 rt2800_set_max_psdu_len(rt2x00dev);
1777 }
1778
1779 if (wcid > WCID_END)
1780 return 0;
1781 /*
1782 * Remove WCID entry, no need to clean the attributes as they will
1783 * get renewed when the WCID is reused.
1784 */
1785 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1786 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1787 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1788
1789 return 0;
1790 }
1791 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1792
1793 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1794 const unsigned int filter_flags)
1795 {
1796 u32 reg;
1797
1798 /*
1799 * Start configuration steps.
1800 * Note that the version error will always be dropped
1801 * and broadcast frames will always be accepted since
1802 * there is no filter for it at this time.
1803 */
1804 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1805 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1806 !(filter_flags & FIF_FCSFAIL));
1807 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1808 !(filter_flags & FIF_PLCPFAIL));
1809 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1810 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1811 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1812 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1813 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1814 !(filter_flags & FIF_ALLMULTI));
1815 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1816 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1817 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1818 !(filter_flags & FIF_CONTROL));
1819 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1820 !(filter_flags & FIF_CONTROL));
1821 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1822 !(filter_flags & FIF_CONTROL));
1823 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1824 !(filter_flags & FIF_CONTROL));
1825 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1826 !(filter_flags & FIF_CONTROL));
1827 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1828 !(filter_flags & FIF_PSPOLL));
1829 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1830 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1831 !(filter_flags & FIF_CONTROL));
1832 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1833 !(filter_flags & FIF_CONTROL));
1834 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1835 }
1836 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1837
1838 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1839 struct rt2x00intf_conf *conf, const unsigned int flags)
1840 {
1841 u32 reg;
1842 bool update_bssid = false;
1843
1844 if (flags & CONFIG_UPDATE_TYPE) {
1845 /*
1846 * Enable synchronisation.
1847 */
1848 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1849 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1850 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1851
1852 if (conf->sync == TSF_SYNC_AP_NONE) {
1853 /*
1854 * Tune beacon queue transmit parameters for AP mode
1855 */
1856 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1857 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1858 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1859 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1860 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1861 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1862 } else {
1863 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1864 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1865 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1866 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1867 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1868 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1869 }
1870 }
1871
1872 if (flags & CONFIG_UPDATE_MAC) {
1873 if (flags & CONFIG_UPDATE_TYPE &&
1874 conf->sync == TSF_SYNC_AP_NONE) {
1875 /*
1876 * The BSSID register has to be set to our own mac
1877 * address in AP mode.
1878 */
1879 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1880 update_bssid = true;
1881 }
1882
1883 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1884 reg = le32_to_cpu(conf->mac[1]);
1885 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1886 conf->mac[1] = cpu_to_le32(reg);
1887 }
1888
1889 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1890 conf->mac, sizeof(conf->mac));
1891 }
1892
1893 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1894 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1895 reg = le32_to_cpu(conf->bssid[1]);
1896 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1897 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1898 conf->bssid[1] = cpu_to_le32(reg);
1899 }
1900
1901 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1902 conf->bssid, sizeof(conf->bssid));
1903 }
1904 }
1905 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1906
1907 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1908 struct rt2x00lib_erp *erp)
1909 {
1910 bool any_sta_nongf = !!(erp->ht_opmode &
1911 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1912 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1913 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1914 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1915 u32 reg;
1916
1917 /* default protection rate for HT20: OFDM 24M */
1918 mm20_rate = gf20_rate = 0x4004;
1919
1920 /* default protection rate for HT40: duplicate OFDM 24M */
1921 mm40_rate = gf40_rate = 0x4084;
1922
1923 switch (protection) {
1924 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1925 /*
1926 * All STAs in this BSS are HT20/40 but there might be
1927 * STAs not supporting greenfield mode.
1928 * => Disable protection for HT transmissions.
1929 */
1930 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1931
1932 break;
1933 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1934 /*
1935 * All STAs in this BSS are HT20 or HT20/40 but there
1936 * might be STAs not supporting greenfield mode.
1937 * => Protect all HT40 transmissions.
1938 */
1939 mm20_mode = gf20_mode = 0;
1940 mm40_mode = gf40_mode = 1;
1941
1942 break;
1943 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1944 /*
1945 * Nonmember protection:
1946 * According to 802.11n we _should_ protect all
1947 * HT transmissions (but we don't have to).
1948 *
1949 * But if cts_protection is enabled we _shall_ protect
1950 * all HT transmissions using a CCK rate.
1951 *
1952 * And if any station is non GF we _shall_ protect
1953 * GF transmissions.
1954 *
1955 * We decide to protect everything
1956 * -> fall through to mixed mode.
1957 */
1958 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1959 /*
1960 * Legacy STAs are present
1961 * => Protect all HT transmissions.
1962 */
1963 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
1964
1965 /*
1966 * If erp protection is needed we have to protect HT
1967 * transmissions with CCK 11M long preamble.
1968 */
1969 if (erp->cts_protection) {
1970 /* don't duplicate RTS/CTS in CCK mode */
1971 mm20_rate = mm40_rate = 0x0003;
1972 gf20_rate = gf40_rate = 0x0003;
1973 }
1974 break;
1975 }
1976
1977 /* check for STAs not supporting greenfield mode */
1978 if (any_sta_nongf)
1979 gf20_mode = gf40_mode = 1;
1980
1981 /* Update HT protection config */
1982 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
1983 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1984 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1985 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1986
1987 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
1988 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1989 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1990 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1991
1992 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
1993 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1994 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1995 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1996
1997 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
1998 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1999 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2000 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2001 }
2002
2003 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2004 u32 changed)
2005 {
2006 u32 reg;
2007
2008 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2009 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2010 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2011 !!erp->short_preamble);
2012 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2013 }
2014
2015 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2016 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2017 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2018 erp->cts_protection ? 2 : 0);
2019 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2020 }
2021
2022 if (changed & BSS_CHANGED_BASIC_RATES) {
2023 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2024 0xff0 | erp->basic_rates);
2025 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2026 }
2027
2028 if (changed & BSS_CHANGED_ERP_SLOT) {
2029 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2030 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2031 erp->slot_time);
2032 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2033
2034 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2035 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2036 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2037 }
2038
2039 if (changed & BSS_CHANGED_BEACON_INT) {
2040 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2041 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2042 erp->beacon_int * 16);
2043 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2044 }
2045
2046 if (changed & BSS_CHANGED_HT)
2047 rt2800_config_ht_opmode(rt2x00dev, erp);
2048 }
2049 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2050
2051 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2052 {
2053 u32 reg;
2054 u16 eeprom;
2055 u8 led_ctrl, led_g_mode, led_r_mode;
2056
2057 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2058 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2059 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2060 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2061 } else {
2062 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2063 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2064 }
2065 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2066
2067 reg = rt2800_register_read(rt2x00dev, LED_CFG);
2068 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2069 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2070 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2071 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2072 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2073 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2074 if (led_ctrl == 0 || led_ctrl > 0x40) {
2075 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2076 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2077 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2078 } else {
2079 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2080 (led_g_mode << 2) | led_r_mode, 1);
2081 }
2082 }
2083 }
2084
2085 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2086 enum antenna ant)
2087 {
2088 u32 reg;
2089 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2090 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2091
2092 if (rt2x00_is_pci(rt2x00dev)) {
2093 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2094 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2095 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2096 } else if (rt2x00_is_usb(rt2x00dev))
2097 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2098 eesk_pin, 0);
2099
2100 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2101 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2102 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2103 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2104 }
2105
2106 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2107 {
2108 u8 r1;
2109 u8 r3;
2110 u16 eeprom;
2111
2112 r1 = rt2800_bbp_read(rt2x00dev, 1);
2113 r3 = rt2800_bbp_read(rt2x00dev, 3);
2114
2115 if (rt2x00_rt(rt2x00dev, RT3572) &&
2116 rt2x00_has_cap_bt_coexist(rt2x00dev))
2117 rt2800_config_3572bt_ant(rt2x00dev);
2118
2119 /*
2120 * Configure the TX antenna.
2121 */
2122 switch (ant->tx_chain_num) {
2123 case 1:
2124 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2125 break;
2126 case 2:
2127 if (rt2x00_rt(rt2x00dev, RT3572) &&
2128 rt2x00_has_cap_bt_coexist(rt2x00dev))
2129 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2130 else
2131 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2132 break;
2133 case 3:
2134 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2135 break;
2136 }
2137
2138 /*
2139 * Configure the RX antenna.
2140 */
2141 switch (ant->rx_chain_num) {
2142 case 1:
2143 if (rt2x00_rt(rt2x00dev, RT3070) ||
2144 rt2x00_rt(rt2x00dev, RT3090) ||
2145 rt2x00_rt(rt2x00dev, RT3352) ||
2146 rt2x00_rt(rt2x00dev, RT3390)) {
2147 eeprom = rt2800_eeprom_read(rt2x00dev,
2148 EEPROM_NIC_CONF1);
2149 if (rt2x00_get_field16(eeprom,
2150 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2151 rt2800_set_ant_diversity(rt2x00dev,
2152 rt2x00dev->default_ant.rx);
2153 }
2154 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2155 break;
2156 case 2:
2157 if (rt2x00_rt(rt2x00dev, RT3572) &&
2158 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2159 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2160 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2161 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2162 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2163 } else {
2164 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2165 }
2166 break;
2167 case 3:
2168 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2169 break;
2170 }
2171
2172 rt2800_bbp_write(rt2x00dev, 3, r3);
2173 rt2800_bbp_write(rt2x00dev, 1, r1);
2174
2175 if (rt2x00_rt(rt2x00dev, RT3593)) {
2176 if (ant->rx_chain_num == 1)
2177 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2178 else
2179 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2180 }
2181 }
2182 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2183
2184 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2185 struct rt2x00lib_conf *libconf)
2186 {
2187 u16 eeprom;
2188 short lna_gain;
2189
2190 if (libconf->rf.channel <= 14) {
2191 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2192 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2193 } else if (libconf->rf.channel <= 64) {
2194 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2195 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2196 } else if (libconf->rf.channel <= 128) {
2197 if (rt2x00_rt(rt2x00dev, RT3593)) {
2198 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2199 lna_gain = rt2x00_get_field16(eeprom,
2200 EEPROM_EXT_LNA2_A1);
2201 } else {
2202 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2203 lna_gain = rt2x00_get_field16(eeprom,
2204 EEPROM_RSSI_BG2_LNA_A1);
2205 }
2206 } else {
2207 if (rt2x00_rt(rt2x00dev, RT3593)) {
2208 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2209 lna_gain = rt2x00_get_field16(eeprom,
2210 EEPROM_EXT_LNA2_A2);
2211 } else {
2212 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2213 lna_gain = rt2x00_get_field16(eeprom,
2214 EEPROM_RSSI_A2_LNA_A2);
2215 }
2216 }
2217
2218 rt2x00dev->lna_gain = lna_gain;
2219 }
2220
2221 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2222 {
2223 return clk_get_rate(rt2x00dev->clk) == 20000000;
2224 }
2225
2226 #define FREQ_OFFSET_BOUND 0x5f
2227
2228 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2229 {
2230 u8 freq_offset, prev_freq_offset;
2231 u8 rfcsr, prev_rfcsr;
2232
2233 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2234 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2235
2236 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2237 prev_rfcsr = rfcsr;
2238
2239 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2240 if (rfcsr == prev_rfcsr)
2241 return;
2242
2243 if (rt2x00_is_usb(rt2x00dev)) {
2244 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2245 freq_offset, prev_rfcsr);
2246 return;
2247 }
2248
2249 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2250 while (prev_freq_offset != freq_offset) {
2251 if (prev_freq_offset < freq_offset)
2252 prev_freq_offset++;
2253 else
2254 prev_freq_offset--;
2255
2256 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2257 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2258
2259 usleep_range(1000, 1500);
2260 }
2261 }
2262
2263 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2264 struct ieee80211_conf *conf,
2265 struct rf_channel *rf,
2266 struct channel_info *info)
2267 {
2268 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2269
2270 if (rt2x00dev->default_ant.tx_chain_num == 1)
2271 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2272
2273 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2274 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2275 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2276 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2277 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2278
2279 if (rf->channel > 14) {
2280 /*
2281 * When TX power is below 0, we should increase it by 7 to
2282 * make it a positive value (Minimum value is -7).
2283 * However this means that values between 0 and 7 have
2284 * double meaning, and we should set a 7DBm boost flag.
2285 */
2286 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2287 (info->default_power1 >= 0));
2288
2289 if (info->default_power1 < 0)
2290 info->default_power1 += 7;
2291
2292 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2293
2294 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2295 (info->default_power2 >= 0));
2296
2297 if (info->default_power2 < 0)
2298 info->default_power2 += 7;
2299
2300 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2301 } else {
2302 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2303 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2304 }
2305
2306 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2307
2308 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2309 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2310 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2311 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2312
2313 udelay(200);
2314
2315 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2316 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2317 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2318 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2319
2320 udelay(200);
2321
2322 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2323 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2324 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2325 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2326 }
2327
2328 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2329 struct ieee80211_conf *conf,
2330 struct rf_channel *rf,
2331 struct channel_info *info)
2332 {
2333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2334 u8 rfcsr, calib_tx, calib_rx;
2335
2336 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2337
2338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2339 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2340 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2341
2342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2343 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2344 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2345
2346 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2347 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2348 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2349
2350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2351 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2352 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2353
2354 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2355 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2356 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2357 rt2x00dev->default_ant.rx_chain_num <= 1);
2358 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2359 rt2x00dev->default_ant.rx_chain_num <= 2);
2360 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2361 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2362 rt2x00dev->default_ant.tx_chain_num <= 1);
2363 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2364 rt2x00dev->default_ant.tx_chain_num <= 2);
2365 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2366
2367 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2368 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2369 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2370
2371 if (rt2x00_rt(rt2x00dev, RT3390)) {
2372 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2373 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2374 } else {
2375 if (conf_is_ht40(conf)) {
2376 calib_tx = drv_data->calibration_bw40;
2377 calib_rx = drv_data->calibration_bw40;
2378 } else {
2379 calib_tx = drv_data->calibration_bw20;
2380 calib_rx = drv_data->calibration_bw20;
2381 }
2382 }
2383
2384 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2385 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2386 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2387
2388 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2389 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2390 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2391
2392 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2393 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2394 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2395
2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2397 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2398 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2399
2400 usleep_range(1000, 1500);
2401
2402 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2403 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2404 }
2405
2406 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2407 struct ieee80211_conf *conf,
2408 struct rf_channel *rf,
2409 struct channel_info *info)
2410 {
2411 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2412 u8 rfcsr;
2413 u32 reg;
2414
2415 if (rf->channel <= 14) {
2416 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2417 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2418 } else {
2419 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2420 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2421 }
2422
2423 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2424 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2425
2426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2427 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2428 if (rf->channel <= 14)
2429 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2430 else
2431 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2432 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2433
2434 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2435 if (rf->channel <= 14)
2436 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2437 else
2438 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2439 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2440
2441 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2442 if (rf->channel <= 14) {
2443 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2444 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2445 info->default_power1);
2446 } else {
2447 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2448 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2449 (info->default_power1 & 0x3) |
2450 ((info->default_power1 & 0xC) << 1));
2451 }
2452 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2453
2454 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2455 if (rf->channel <= 14) {
2456 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2457 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2458 info->default_power2);
2459 } else {
2460 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2461 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2462 (info->default_power2 & 0x3) |
2463 ((info->default_power2 & 0xC) << 1));
2464 }
2465 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2466
2467 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2468 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2469 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2470 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2471 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2472 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2473 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2474 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2475 if (rf->channel <= 14) {
2476 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2477 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2478 }
2479 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2480 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2481 } else {
2482 switch (rt2x00dev->default_ant.tx_chain_num) {
2483 case 1:
2484 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2485 /* fall through */
2486 case 2:
2487 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2488 break;
2489 }
2490
2491 switch (rt2x00dev->default_ant.rx_chain_num) {
2492 case 1:
2493 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2494 /* fall through */
2495 case 2:
2496 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2497 break;
2498 }
2499 }
2500 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2501
2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2503 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2504 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2505
2506 if (conf_is_ht40(conf)) {
2507 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2508 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2509 } else {
2510 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2511 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2512 }
2513
2514 if (rf->channel <= 14) {
2515 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2516 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2517 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2518 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2519 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2520 rfcsr = 0x4c;
2521 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2522 drv_data->txmixer_gain_24g);
2523 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2524 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2525 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2526 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2527 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2528 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2529 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2530 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2531 } else {
2532 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2533 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2534 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2535 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2536 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2537 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2538 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2539 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2540 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2541 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2542 rfcsr = 0x7a;
2543 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2544 drv_data->txmixer_gain_5g);
2545 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2546 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2547 if (rf->channel <= 64) {
2548 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2549 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2550 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2551 } else if (rf->channel <= 128) {
2552 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2553 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2554 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2555 } else {
2556 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2557 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2558 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2559 }
2560 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2561 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2562 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2563 }
2564
2565 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2566 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2567 if (rf->channel <= 14)
2568 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2569 else
2570 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2571 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2572
2573 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2574 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2575 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2576 }
2577
2578 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2579 struct ieee80211_conf *conf,
2580 struct rf_channel *rf,
2581 struct channel_info *info)
2582 {
2583 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2584 u8 txrx_agc_fc;
2585 u8 txrx_h20m;
2586 u8 rfcsr;
2587 u8 bbp;
2588 const bool txbf_enabled = false; /* TODO */
2589
2590 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2591 bbp = rt2800_bbp_read(rt2x00dev, 109);
2592 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2593 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2594 rt2800_bbp_write(rt2x00dev, 109, bbp);
2595
2596 bbp = rt2800_bbp_read(rt2x00dev, 110);
2597 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2598 rt2800_bbp_write(rt2x00dev, 110, bbp);
2599
2600 if (rf->channel <= 14) {
2601 /* Restore BBP 25 & 26 for 2.4 GHz */
2602 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2603 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2604 } else {
2605 /* Hard code BBP 25 & 26 for 5GHz */
2606
2607 /* Enable IQ Phase correction */
2608 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2609 /* Setup IQ Phase correction value */
2610 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2611 }
2612
2613 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2614 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2615
2616 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2617 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2618 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2619
2620 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2621 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2622 if (rf->channel <= 14)
2623 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2624 else
2625 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2626 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2627
2628 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2629 if (rf->channel <= 14) {
2630 rfcsr = 0;
2631 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2632 info->default_power1 & 0x1f);
2633 } else {
2634 if (rt2x00_is_usb(rt2x00dev))
2635 rfcsr = 0x40;
2636
2637 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2638 ((info->default_power1 & 0x18) << 1) |
2639 (info->default_power1 & 7));
2640 }
2641 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2642
2643 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2644 if (rf->channel <= 14) {
2645 rfcsr = 0;
2646 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2647 info->default_power2 & 0x1f);
2648 } else {
2649 if (rt2x00_is_usb(rt2x00dev))
2650 rfcsr = 0x40;
2651
2652 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2653 ((info->default_power2 & 0x18) << 1) |
2654 (info->default_power2 & 7));
2655 }
2656 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2657
2658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2659 if (rf->channel <= 14) {
2660 rfcsr = 0;
2661 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2662 info->default_power3 & 0x1f);
2663 } else {
2664 if (rt2x00_is_usb(rt2x00dev))
2665 rfcsr = 0x40;
2666
2667 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2668 ((info->default_power3 & 0x18) << 1) |
2669 (info->default_power3 & 7));
2670 }
2671 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2672
2673 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2674 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2675 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2676 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2677 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2678 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2679 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2680 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2681 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2682
2683 switch (rt2x00dev->default_ant.tx_chain_num) {
2684 case 3:
2685 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2686 /* fallthrough */
2687 case 2:
2688 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2689 /* fallthrough */
2690 case 1:
2691 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2692 break;
2693 }
2694
2695 switch (rt2x00dev->default_ant.rx_chain_num) {
2696 case 3:
2697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2698 /* fallthrough */
2699 case 2:
2700 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2701 /* fallthrough */
2702 case 1:
2703 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2704 break;
2705 }
2706 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2707
2708 rt2800_freq_cal_mode1(rt2x00dev);
2709
2710 if (conf_is_ht40(conf)) {
2711 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2712 RFCSR24_TX_AGC_FC);
2713 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2714 RFCSR24_TX_H20M);
2715 } else {
2716 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2717 RFCSR24_TX_AGC_FC);
2718 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2719 RFCSR24_TX_H20M);
2720 }
2721
2722 /* NOTE: the reference driver does not writes the new value
2723 * back to RFCSR 32
2724 */
2725 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2726 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2727
2728 if (rf->channel <= 14)
2729 rfcsr = 0xa0;
2730 else
2731 rfcsr = 0x80;
2732 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2733
2734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2735 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2736 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2737 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2738
2739 /* Band selection */
2740 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2741 if (rf->channel <= 14)
2742 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2743 else
2744 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2745 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2746
2747 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2748 if (rf->channel <= 14)
2749 rfcsr = 0x3c;
2750 else
2751 rfcsr = 0x20;
2752 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2753
2754 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2755 if (rf->channel <= 14)
2756 rfcsr = 0x1a;
2757 else
2758 rfcsr = 0x12;
2759 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2760
2761 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2762 if (rf->channel >= 1 && rf->channel <= 14)
2763 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2764 else if (rf->channel >= 36 && rf->channel <= 64)
2765 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2766 else if (rf->channel >= 100 && rf->channel <= 128)
2767 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2768 else
2769 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2770 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2771
2772 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2773 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2774 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2775
2776 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2777
2778 if (rf->channel <= 14) {
2779 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2780 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2781 } else {
2782 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2783 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2784 }
2785
2786 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2787 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2788 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2789
2790 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2791 if (rf->channel <= 14) {
2792 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2793 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2794 } else {
2795 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2796 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2797 }
2798 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2799
2800 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2801 if (rf->channel <= 14)
2802 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2803 else
2804 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2805
2806 if (txbf_enabled)
2807 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2808
2809 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2810
2811 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2812 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2813 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2814
2815 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2816 if (rf->channel <= 14)
2817 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2818 else
2819 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2820 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2821
2822 if (rf->channel <= 14) {
2823 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2824 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2825 } else {
2826 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2827 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2828 }
2829
2830 /* Initiate VCO calibration */
2831 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2832 if (rf->channel <= 14) {
2833 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2834 } else {
2835 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2836 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2837 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2838 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2839 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2840 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2841 }
2842 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2843
2844 if (rf->channel >= 1 && rf->channel <= 14) {
2845 rfcsr = 0x23;
2846 if (txbf_enabled)
2847 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2848 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2849
2850 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2851 } else if (rf->channel >= 36 && rf->channel <= 64) {
2852 rfcsr = 0x36;
2853 if (txbf_enabled)
2854 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2855 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2856
2857 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2858 } else if (rf->channel >= 100 && rf->channel <= 128) {
2859 rfcsr = 0x32;
2860 if (txbf_enabled)
2861 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2862 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2863
2864 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2865 } else {
2866 rfcsr = 0x30;
2867 if (txbf_enabled)
2868 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2869 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2870
2871 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2872 }
2873 }
2874
2875 #define POWER_BOUND 0x27
2876 #define POWER_BOUND_5G 0x2b
2877
2878 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2879 struct ieee80211_conf *conf,
2880 struct rf_channel *rf,
2881 struct channel_info *info)
2882 {
2883 u8 rfcsr;
2884
2885 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2886 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2887 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2888 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2889 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2890
2891 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2892 if (info->default_power1 > POWER_BOUND)
2893 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2894 else
2895 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2896 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2897
2898 rt2800_freq_cal_mode1(rt2x00dev);
2899
2900 if (rf->channel <= 14) {
2901 if (rf->channel == 6)
2902 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2903 else
2904 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2905
2906 if (rf->channel >= 1 && rf->channel <= 6)
2907 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2908 else if (rf->channel >= 7 && rf->channel <= 11)
2909 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2910 else if (rf->channel >= 12 && rf->channel <= 14)
2911 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2912 }
2913 }
2914
2915 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2916 struct ieee80211_conf *conf,
2917 struct rf_channel *rf,
2918 struct channel_info *info)
2919 {
2920 u8 rfcsr;
2921
2922 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2923 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2924
2925 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2926 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2927 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2928
2929 if (info->default_power1 > POWER_BOUND)
2930 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2931 else
2932 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2933
2934 if (info->default_power2 > POWER_BOUND)
2935 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2936 else
2937 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2938
2939 rt2800_freq_cal_mode1(rt2x00dev);
2940
2941 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2942 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2943 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2944
2945 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2946 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2947 else
2948 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2949
2950 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2951 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2952 else
2953 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2954
2955 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2956 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2957
2958 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2959
2960 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2961 }
2962
2963 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2964 struct ieee80211_conf *conf,
2965 struct rf_channel *rf,
2966 struct channel_info *info)
2967 {
2968 u8 rfcsr;
2969 int idx = rf->channel-1;
2970
2971 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2972 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2973 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2974 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2975 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2976
2977 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2978 if (info->default_power1 > POWER_BOUND)
2979 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2980 else
2981 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2982 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2983
2984 if (rt2x00_rt(rt2x00dev, RT5392)) {
2985 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2986 if (info->default_power2 > POWER_BOUND)
2987 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2988 else
2989 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2990 info->default_power2);
2991 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2992 }
2993
2994 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2995 if (rt2x00_rt(rt2x00dev, RT5392)) {
2996 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2997 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2998 }
2999 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3000 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3001 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3002 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3003 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3004
3005 rt2800_freq_cal_mode1(rt2x00dev);
3006
3007 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3009 /* r55/r59 value array of channel 1~14 */
3010 static const char r55_bt_rev[] = {0x83, 0x83,
3011 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3012 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3013 static const char r59_bt_rev[] = {0x0e, 0x0e,
3014 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3015 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3016
3017 rt2800_rfcsr_write(rt2x00dev, 55,
3018 r55_bt_rev[idx]);
3019 rt2800_rfcsr_write(rt2x00dev, 59,
3020 r59_bt_rev[idx]);
3021 } else {
3022 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3023 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3024 0x88, 0x88, 0x86, 0x85, 0x84};
3025
3026 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3027 }
3028 } else {
3029 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3030 static const char r55_nonbt_rev[] = {0x23, 0x23,
3031 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3032 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3033 static const char r59_nonbt_rev[] = {0x07, 0x07,
3034 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3035 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3036
3037 rt2800_rfcsr_write(rt2x00dev, 55,
3038 r55_nonbt_rev[idx]);
3039 rt2800_rfcsr_write(rt2x00dev, 59,
3040 r59_nonbt_rev[idx]);
3041 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3042 rt2x00_rt(rt2x00dev, RT5392) ||
3043 rt2x00_rt(rt2x00dev, RT6352)) {
3044 static const char r59_non_bt[] = {0x8f, 0x8f,
3045 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3046 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3047
3048 rt2800_rfcsr_write(rt2x00dev, 59,
3049 r59_non_bt[idx]);
3050 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3051 static const char r59_non_bt[] = {0x0b, 0x0b,
3052 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3053 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3054
3055 rt2800_rfcsr_write(rt2x00dev, 59,
3056 r59_non_bt[idx]);
3057 }
3058 }
3059 }
3060
3061 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3062 struct ieee80211_conf *conf,
3063 struct rf_channel *rf,
3064 struct channel_info *info)
3065 {
3066 u8 rfcsr, ep_reg;
3067 u32 reg;
3068 int power_bound;
3069
3070 /* TODO */
3071 const bool is_11b = false;
3072 const bool is_type_ep = false;
3073
3074 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3075 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3076 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3077 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3078
3079 /* Order of values on rf_channel entry: N, K, mod, R */
3080 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3081
3082 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3083 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3084 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3085 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3086 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3087
3088 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3089 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3090 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3091 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3092
3093 if (rf->channel <= 14) {
3094 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3095 /* FIXME: RF11 owerwrite ? */
3096 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3097 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3098 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3099 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3100 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3101 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3102 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3103 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3104 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3105 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3106 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3107 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3108 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3109 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3110 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3111 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3112 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3113 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3114 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3115 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3116 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3117 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3118 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3119 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3120 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3121 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3122 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3123 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3124
3125 /* TODO RF27 <- tssi */
3126
3127 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3128 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3129 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3130
3131 if (is_11b) {
3132 /* CCK */
3133 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3134 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3135 if (is_type_ep)
3136 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3137 else
3138 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3139 } else {
3140 /* OFDM */
3141 if (is_type_ep)
3142 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3143 else
3144 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3145 }
3146
3147 power_bound = POWER_BOUND;
3148 ep_reg = 0x2;
3149 } else {
3150 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3151 /* FIMXE: RF11 overwrite */
3152 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3153 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3154 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3155 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3156 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3157 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3158 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3159 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3160 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3161 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3162 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3163 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3164 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3165 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3166
3167 /* TODO RF27 <- tssi */
3168
3169 if (rf->channel >= 36 && rf->channel <= 64) {
3170
3171 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3172 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3173 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3174 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3175 if (rf->channel <= 50)
3176 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3177 else if (rf->channel >= 52)
3178 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3179 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3180 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3181 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3182 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3183 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3184 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3185 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3186 if (rf->channel <= 50) {
3187 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3188 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3189 } else if (rf->channel >= 52) {
3190 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3191 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3192 }
3193
3194 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3195 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3196 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3197
3198 } else if (rf->channel >= 100 && rf->channel <= 165) {
3199
3200 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3201 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3202 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3203 if (rf->channel <= 153) {
3204 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3205 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3206 } else if (rf->channel >= 155) {
3207 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3208 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3209 }
3210 if (rf->channel <= 138) {
3211 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3212 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3213 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3214 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3215 } else if (rf->channel >= 140) {
3216 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3217 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3218 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3219 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3220 }
3221 if (rf->channel <= 124)
3222 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3223 else if (rf->channel >= 126)
3224 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3225 if (rf->channel <= 138)
3226 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3227 else if (rf->channel >= 140)
3228 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3229 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3230 if (rf->channel <= 138)
3231 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3232 else if (rf->channel >= 140)
3233 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3234 if (rf->channel <= 128)
3235 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3236 else if (rf->channel >= 130)
3237 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3238 if (rf->channel <= 116)
3239 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3240 else if (rf->channel >= 118)
3241 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3242 if (rf->channel <= 138)
3243 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3244 else if (rf->channel >= 140)
3245 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3246 if (rf->channel <= 116)
3247 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3248 else if (rf->channel >= 118)
3249 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3250 }
3251
3252 power_bound = POWER_BOUND_5G;
3253 ep_reg = 0x3;
3254 }
3255
3256 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3257 if (info->default_power1 > power_bound)
3258 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3259 else
3260 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3261 if (is_type_ep)
3262 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3263 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3264
3265 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3266 if (info->default_power2 > power_bound)
3267 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3268 else
3269 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3270 if (is_type_ep)
3271 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3272 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3273
3274 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3275 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3276 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3277
3278 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3279 rt2x00dev->default_ant.tx_chain_num >= 1);
3280 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3281 rt2x00dev->default_ant.tx_chain_num == 2);
3282 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3283
3284 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3285 rt2x00dev->default_ant.rx_chain_num >= 1);
3286 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3287 rt2x00dev->default_ant.rx_chain_num == 2);
3288 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3289
3290 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3291 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3292
3293 if (conf_is_ht40(conf))
3294 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3295 else
3296 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3297
3298 if (!is_11b) {
3299 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3300 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3301 }
3302
3303 /* TODO proper frequency adjustment */
3304 rt2800_freq_cal_mode1(rt2x00dev);
3305
3306 /* TODO merge with others */
3307 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3308 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3309 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3310
3311 /* BBP settings */
3312 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3313 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3314 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3315
3316 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3317 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3318 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3319 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3320
3321 /* GLRT band configuration */
3322 rt2800_bbp_write(rt2x00dev, 195, 128);
3323 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3324 rt2800_bbp_write(rt2x00dev, 195, 129);
3325 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3326 rt2800_bbp_write(rt2x00dev, 195, 130);
3327 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3328 rt2800_bbp_write(rt2x00dev, 195, 131);
3329 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3330 rt2800_bbp_write(rt2x00dev, 195, 133);
3331 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3332 rt2800_bbp_write(rt2x00dev, 195, 124);
3333 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3334 }
3335
3336 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3337 struct ieee80211_conf *conf,
3338 struct rf_channel *rf,
3339 struct channel_info *info)
3340 {
3341 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3342 u8 rx_agc_fc, tx_agc_fc;
3343 u8 rfcsr;
3344
3345 /* Frequeny plan setting */
3346 /* Rdiv setting (set 0x03 if Xtal==20)
3347 * R13[1:0]
3348 */
3349 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3350 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3351 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3352 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3353
3354 /* N setting
3355 * R20[7:0] in rf->rf1
3356 * R21[0] always 0
3357 */
3358 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3359 rfcsr = (rf->rf1 & 0x00ff);
3360 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3361
3362 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3363 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3364 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3365
3366 /* K setting (always 0)
3367 * R16[3:0] (RF PLL freq selection)
3368 */
3369 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3370 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3371 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3372
3373 /* D setting (always 0)
3374 * R22[2:0] (D=15, R22[2:0]=<111>)
3375 */
3376 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3377 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3378 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3379
3380 /* Ksd setting
3381 * Ksd: R17<7:0> in rf->rf2
3382 * R18<7:0> in rf->rf3
3383 * R19<1:0> in rf->rf4
3384 */
3385 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3386 rfcsr = rf->rf2;
3387 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3388
3389 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3390 rfcsr = rf->rf3;
3391 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3392
3393 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3394 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3395 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3396
3397 /* Default: XO=20MHz , SDM mode */
3398 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3399 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3400 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3401
3402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3403 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3404 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3405
3406 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3407 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3408 rt2x00dev->default_ant.tx_chain_num != 1);
3409 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3410
3411 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3412 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3413 rt2x00dev->default_ant.tx_chain_num != 1);
3414 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3415 rt2x00dev->default_ant.rx_chain_num != 1);
3416 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3417
3418 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3419 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3420 rt2x00dev->default_ant.tx_chain_num != 1);
3421 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3422
3423 /* RF for DC Cal BW */
3424 if (conf_is_ht40(conf)) {
3425 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3426 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3427 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3428 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3429 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3430 } else {
3431 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3432 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3433 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3434 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3435 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3436 }
3437
3438 if (conf_is_ht40(conf)) {
3439 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3440 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3441 } else {
3442 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3443 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3444 }
3445
3446 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3447 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3448 conf_is_ht40(conf) && (rf->channel == 11));
3449 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3450
3451 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3452 if (conf_is_ht40(conf)) {
3453 rx_agc_fc = drv_data->rx_calibration_bw40;
3454 tx_agc_fc = drv_data->tx_calibration_bw40;
3455 } else {
3456 rx_agc_fc = drv_data->rx_calibration_bw20;
3457 tx_agc_fc = drv_data->tx_calibration_bw20;
3458 }
3459 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3460 rfcsr &= (~0x3F);
3461 rfcsr |= rx_agc_fc;
3462 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3463 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3464 rfcsr &= (~0x3F);
3465 rfcsr |= rx_agc_fc;
3466 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3467 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3468 rfcsr &= (~0x3F);
3469 rfcsr |= rx_agc_fc;
3470 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3471 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3472 rfcsr &= (~0x3F);
3473 rfcsr |= rx_agc_fc;
3474 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3475
3476 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3477 rfcsr &= (~0x3F);
3478 rfcsr |= tx_agc_fc;
3479 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3480 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3481 rfcsr &= (~0x3F);
3482 rfcsr |= tx_agc_fc;
3483 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3484 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3485 rfcsr &= (~0x3F);
3486 rfcsr |= tx_agc_fc;
3487 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3488 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3489 rfcsr &= (~0x3F);
3490 rfcsr |= tx_agc_fc;
3491 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3492 }
3493 }
3494
3495 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3496 struct ieee80211_channel *chan,
3497 int power_level) {
3498 u16 eeprom, target_power, max_power;
3499 u32 mac_sys_ctrl, mac_status;
3500 u32 reg;
3501 u8 bbp;
3502 int i;
3503
3504 /* hardware unit is 0.5dBm, limited to 23.5dBm */
3505 power_level *= 2;
3506 if (power_level > 0x2f)
3507 power_level = 0x2f;
3508
3509 max_power = chan->max_power * 2;
3510 if (max_power > 0x2f)
3511 max_power = 0x2f;
3512
3513 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3514 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3515 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3516 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3517 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3518
3519 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3520 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3521 /* init base power by eeprom target power */
3522 target_power = rt2800_eeprom_read(rt2x00dev,
3523 EEPROM_TXPOWER_INIT);
3524 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3525 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3526 }
3527 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3528
3529 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3530 rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3531 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3532
3533 /* Save MAC SYS CTRL registers */
3534 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3535 /* Disable Tx/Rx */
3536 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3537 /* Check MAC Tx/Rx idle */
3538 for (i = 0; i < 10000; i++) {
3539 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3540 if (mac_status & 0x3)
3541 usleep_range(50, 200);
3542 else
3543 break;
3544 }
3545
3546 if (i == 10000)
3547 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3548
3549 if (chan->center_freq > 2457) {
3550 bbp = rt2800_bbp_read(rt2x00dev, 30);
3551 bbp = 0x40;
3552 rt2800_bbp_write(rt2x00dev, 30, bbp);
3553 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3554 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3555 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3556 else
3557 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3558 } else {
3559 bbp = rt2800_bbp_read(rt2x00dev, 30);
3560 bbp = 0x1f;
3561 rt2800_bbp_write(rt2x00dev, 30, bbp);
3562 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3563 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3564 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3565 else
3566 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3567 }
3568 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3569
3570 rt2800_vco_calibration(rt2x00dev);
3571 }
3572
3573 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3574 const unsigned int word,
3575 const u8 value)
3576 {
3577 u8 chain, reg;
3578
3579 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3580 reg = rt2800_bbp_read(rt2x00dev, 27);
3581 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3582 rt2800_bbp_write(rt2x00dev, 27, reg);
3583
3584 rt2800_bbp_write(rt2x00dev, word, value);
3585 }
3586 }
3587
3588 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3589 {
3590 u8 cal;
3591
3592 /* TX0 IQ Gain */
3593 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3594 if (channel <= 14)
3595 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3596 else if (channel >= 36 && channel <= 64)
3597 cal = rt2x00_eeprom_byte(rt2x00dev,
3598 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3599 else if (channel >= 100 && channel <= 138)
3600 cal = rt2x00_eeprom_byte(rt2x00dev,
3601 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3602 else if (channel >= 140 && channel <= 165)
3603 cal = rt2x00_eeprom_byte(rt2x00dev,
3604 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3605 else
3606 cal = 0;
3607 rt2800_bbp_write(rt2x00dev, 159, cal);
3608
3609 /* TX0 IQ Phase */
3610 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3611 if (channel <= 14)
3612 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3613 else if (channel >= 36 && channel <= 64)
3614 cal = rt2x00_eeprom_byte(rt2x00dev,
3615 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3616 else if (channel >= 100 && channel <= 138)
3617 cal = rt2x00_eeprom_byte(rt2x00dev,
3618 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3619 else if (channel >= 140 && channel <= 165)
3620 cal = rt2x00_eeprom_byte(rt2x00dev,
3621 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3622 else
3623 cal = 0;
3624 rt2800_bbp_write(rt2x00dev, 159, cal);
3625
3626 /* TX1 IQ Gain */
3627 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3628 if (channel <= 14)
3629 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3630 else if (channel >= 36 && channel <= 64)
3631 cal = rt2x00_eeprom_byte(rt2x00dev,
3632 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3633 else if (channel >= 100 && channel <= 138)
3634 cal = rt2x00_eeprom_byte(rt2x00dev,
3635 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3636 else if (channel >= 140 && channel <= 165)
3637 cal = rt2x00_eeprom_byte(rt2x00dev,
3638 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3639 else
3640 cal = 0;
3641 rt2800_bbp_write(rt2x00dev, 159, cal);
3642
3643 /* TX1 IQ Phase */
3644 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3645 if (channel <= 14)
3646 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3647 else if (channel >= 36 && channel <= 64)
3648 cal = rt2x00_eeprom_byte(rt2x00dev,
3649 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3650 else if (channel >= 100 && channel <= 138)
3651 cal = rt2x00_eeprom_byte(rt2x00dev,
3652 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3653 else if (channel >= 140 && channel <= 165)
3654 cal = rt2x00_eeprom_byte(rt2x00dev,
3655 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3656 else
3657 cal = 0;
3658 rt2800_bbp_write(rt2x00dev, 159, cal);
3659
3660 /* FIXME: possible RX0, RX1 callibration ? */
3661
3662 /* RF IQ compensation control */
3663 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3664 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3665 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3666
3667 /* RF IQ imbalance compensation control */
3668 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3669 cal = rt2x00_eeprom_byte(rt2x00dev,
3670 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3671 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3672 }
3673
3674 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3675 unsigned int channel,
3676 char txpower)
3677 {
3678 if (rt2x00_rt(rt2x00dev, RT3593))
3679 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3680
3681 if (channel <= 14)
3682 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3683
3684 if (rt2x00_rt(rt2x00dev, RT3593))
3685 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3686 MAX_A_TXPOWER_3593);
3687 else
3688 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3689 }
3690
3691 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3692 struct ieee80211_conf *conf,
3693 struct rf_channel *rf,
3694 struct channel_info *info)
3695 {
3696 u32 reg;
3697 u32 tx_pin;
3698 u8 bbp, rfcsr;
3699
3700 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3701 info->default_power1);
3702 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3703 info->default_power2);
3704 if (rt2x00dev->default_ant.tx_chain_num > 2)
3705 info->default_power3 =
3706 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3707 info->default_power3);
3708
3709 switch (rt2x00dev->chip.rf) {
3710 case RF2020:
3711 case RF3020:
3712 case RF3021:
3713 case RF3022:
3714 case RF3320:
3715 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3716 break;
3717 case RF3052:
3718 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3719 break;
3720 case RF3053:
3721 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3722 break;
3723 case RF3290:
3724 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3725 break;
3726 case RF3322:
3727 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3728 break;
3729 case RF3070:
3730 case RF5350:
3731 case RF5360:
3732 case RF5362:
3733 case RF5370:
3734 case RF5372:
3735 case RF5390:
3736 case RF5392:
3737 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3738 break;
3739 case RF5592:
3740 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3741 break;
3742 case RF7620:
3743 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3744 break;
3745 default:
3746 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3747 }
3748
3749 if (rt2x00_rf(rt2x00dev, RF3070) ||
3750 rt2x00_rf(rt2x00dev, RF3290) ||
3751 rt2x00_rf(rt2x00dev, RF3322) ||
3752 rt2x00_rf(rt2x00dev, RF5350) ||
3753 rt2x00_rf(rt2x00dev, RF5360) ||
3754 rt2x00_rf(rt2x00dev, RF5362) ||
3755 rt2x00_rf(rt2x00dev, RF5370) ||
3756 rt2x00_rf(rt2x00dev, RF5372) ||
3757 rt2x00_rf(rt2x00dev, RF5390) ||
3758 rt2x00_rf(rt2x00dev, RF5392)) {
3759 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3760 if (rt2x00_rf(rt2x00dev, RF3322)) {
3761 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3762 conf_is_ht40(conf));
3763 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3764 conf_is_ht40(conf));
3765 } else {
3766 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3767 conf_is_ht40(conf));
3768 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3769 conf_is_ht40(conf));
3770 }
3771 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3772
3773 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3774 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3775 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3776 }
3777
3778 /*
3779 * Change BBP settings
3780 */
3781
3782 if (rt2x00_rt(rt2x00dev, RT3352)) {
3783 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3784 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3785 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3786
3787 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3788 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3789 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3790 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3791 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3792 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3793 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3794 if (rf->channel > 14) {
3795 /* Disable CCK Packet detection on 5GHz */
3796 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3797 } else {
3798 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3799 }
3800
3801 if (conf_is_ht40(conf))
3802 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3803 else
3804 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3805
3806 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3807 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3808 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3809 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3810 } else {
3811 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3812 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3813 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3814 rt2800_bbp_write(rt2x00dev, 86, 0);
3815 }
3816
3817 if (rf->channel <= 14) {
3818 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3819 !rt2x00_rt(rt2x00dev, RT5392) &&
3820 !rt2x00_rt(rt2x00dev, RT6352)) {
3821 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3822 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3823 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3824 } else {
3825 if (rt2x00_rt(rt2x00dev, RT3593))
3826 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3827 else
3828 rt2800_bbp_write(rt2x00dev, 82, 0x84);
3829 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3830 }
3831 if (rt2x00_rt(rt2x00dev, RT3593))
3832 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3833 }
3834
3835 } else {
3836 if (rt2x00_rt(rt2x00dev, RT3572))
3837 rt2800_bbp_write(rt2x00dev, 82, 0x94);
3838 else if (rt2x00_rt(rt2x00dev, RT3593))
3839 rt2800_bbp_write(rt2x00dev, 82, 0x82);
3840 else if (!rt2x00_rt(rt2x00dev, RT6352))
3841 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3842
3843 if (rt2x00_rt(rt2x00dev, RT3593))
3844 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3845
3846 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3847 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3848 else
3849 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3850 }
3851
3852 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
3853 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3854 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3855 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3856 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3857
3858 if (rt2x00_rt(rt2x00dev, RT3572))
3859 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3860
3861 if (rt2x00_rt(rt2x00dev, RT6352)) {
3862 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
3863 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
3864 } else {
3865 tx_pin = 0;
3866 }
3867
3868 switch (rt2x00dev->default_ant.tx_chain_num) {
3869 case 3:
3870 /* Turn on tertiary PAs */
3871 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3872 rf->channel > 14);
3873 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3874 rf->channel <= 14);
3875 /* fall-through */
3876 case 2:
3877 /* Turn on secondary PAs */
3878 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3879 rf->channel > 14);
3880 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3881 rf->channel <= 14);
3882 /* fall-through */
3883 case 1:
3884 /* Turn on primary PAs */
3885 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3886 rf->channel > 14);
3887 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3888 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3889 else
3890 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3891 rf->channel <= 14);
3892 break;
3893 }
3894
3895 switch (rt2x00dev->default_ant.rx_chain_num) {
3896 case 3:
3897 /* Turn on tertiary LNAs */
3898 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN,
3899 rf->channel > 14);
3900 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN,
3901 rf->channel <= 14);
3902 /* fall-through */
3903 case 2:
3904 /* Turn on secondary LNAs */
3905 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN,
3906 rf->channel > 14);
3907 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN,
3908 rf->channel <= 14);
3909 /* fall-through */
3910 case 1:
3911 /* Turn on primary LNAs */
3912 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN,
3913 rf->channel > 14);
3914 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN,
3915 rf->channel <= 14);
3916 break;
3917 }
3918
3919 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3920 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3921
3922 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3923
3924 if (rt2x00_rt(rt2x00dev, RT3572)) {
3925 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3926
3927 /* AGC init */
3928 if (rf->channel <= 14)
3929 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3930 else
3931 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3932
3933 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3934 }
3935
3936 if (rt2x00_rt(rt2x00dev, RT3593)) {
3937 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
3938
3939 /* Band selection */
3940 if (rt2x00_is_usb(rt2x00dev) ||
3941 rt2x00_is_pcie(rt2x00dev)) {
3942 /* GPIO #8 controls all paths */
3943 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3944 if (rf->channel <= 14)
3945 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3946 else
3947 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3948 }
3949
3950 /* LNA PE control. */
3951 if (rt2x00_is_usb(rt2x00dev)) {
3952 /* GPIO #4 controls PE0 and PE1,
3953 * GPIO #7 controls PE2
3954 */
3955 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3956 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3957
3958 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3959 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3960 } else if (rt2x00_is_pcie(rt2x00dev)) {
3961 /* GPIO #4 controls PE0, PE1 and PE2 */
3962 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3963 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3964 }
3965
3966 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3967
3968 /* AGC init */
3969 if (rf->channel <= 14)
3970 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3971 else
3972 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3973
3974 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3975
3976 usleep_range(1000, 1500);
3977 }
3978
3979 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
3980 reg = 0x10;
3981 if (!conf_is_ht40(conf)) {
3982 if (rt2x00_rt(rt2x00dev, RT6352) &&
3983 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3984 reg |= 0x5;
3985 } else {
3986 reg |= 0xa;
3987 }
3988 }
3989 rt2800_bbp_write(rt2x00dev, 195, 141);
3990 rt2800_bbp_write(rt2x00dev, 196, reg);
3991
3992 /* AGC init.
3993 * Despite the vendor driver using different values here for
3994 * RT6352 chip, we use 0x1c for now. This may have to be changed
3995 * once TSSI got implemented.
3996 */
3997 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
3998 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3999
4000 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4001 }
4002
4003 bbp = rt2800_bbp_read(rt2x00dev, 4);
4004 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4005 rt2800_bbp_write(rt2x00dev, 4, bbp);
4006
4007 bbp = rt2800_bbp_read(rt2x00dev, 3);
4008 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4009 rt2800_bbp_write(rt2x00dev, 3, bbp);
4010
4011 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4012 if (conf_is_ht40(conf)) {
4013 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4014 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4015 rt2800_bbp_write(rt2x00dev, 73, 0x16);
4016 } else {
4017 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4018 rt2800_bbp_write(rt2x00dev, 70, 0x08);
4019 rt2800_bbp_write(rt2x00dev, 73, 0x11);
4020 }
4021 }
4022
4023 usleep_range(1000, 1500);
4024
4025 /*
4026 * Clear channel statistic counters
4027 */
4028 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4029 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4030 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4031
4032 /*
4033 * Clear update flag
4034 */
4035 if (rt2x00_rt(rt2x00dev, RT3352) ||
4036 rt2x00_rt(rt2x00dev, RT5350)) {
4037 bbp = rt2800_bbp_read(rt2x00dev, 49);
4038 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4039 rt2800_bbp_write(rt2x00dev, 49, bbp);
4040 }
4041 }
4042
4043 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4044 {
4045 u8 tssi_bounds[9];
4046 u8 current_tssi;
4047 u16 eeprom;
4048 u8 step;
4049 int i;
4050
4051 /*
4052 * First check if temperature compensation is supported.
4053 */
4054 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4055 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4056 return 0;
4057
4058 /*
4059 * Read TSSI boundaries for temperature compensation from
4060 * the EEPROM.
4061 *
4062 * Array idx 0 1 2 3 4 5 6 7 8
4063 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
4064 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4065 */
4066 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4067 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4068 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4069 EEPROM_TSSI_BOUND_BG1_MINUS4);
4070 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4071 EEPROM_TSSI_BOUND_BG1_MINUS3);
4072
4073 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4074 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4075 EEPROM_TSSI_BOUND_BG2_MINUS2);
4076 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4077 EEPROM_TSSI_BOUND_BG2_MINUS1);
4078
4079 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4080 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4081 EEPROM_TSSI_BOUND_BG3_REF);
4082 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4083 EEPROM_TSSI_BOUND_BG3_PLUS1);
4084
4085 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4086 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4087 EEPROM_TSSI_BOUND_BG4_PLUS2);
4088 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4089 EEPROM_TSSI_BOUND_BG4_PLUS3);
4090
4091 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4092 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4093 EEPROM_TSSI_BOUND_BG5_PLUS4);
4094
4095 step = rt2x00_get_field16(eeprom,
4096 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4097 } else {
4098 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4099 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4100 EEPROM_TSSI_BOUND_A1_MINUS4);
4101 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4102 EEPROM_TSSI_BOUND_A1_MINUS3);
4103
4104 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4105 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4106 EEPROM_TSSI_BOUND_A2_MINUS2);
4107 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4108 EEPROM_TSSI_BOUND_A2_MINUS1);
4109
4110 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4111 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4112 EEPROM_TSSI_BOUND_A3_REF);
4113 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4114 EEPROM_TSSI_BOUND_A3_PLUS1);
4115
4116 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4117 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4118 EEPROM_TSSI_BOUND_A4_PLUS2);
4119 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4120 EEPROM_TSSI_BOUND_A4_PLUS3);
4121
4122 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4123 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4124 EEPROM_TSSI_BOUND_A5_PLUS4);
4125
4126 step = rt2x00_get_field16(eeprom,
4127 EEPROM_TSSI_BOUND_A5_AGC_STEP);
4128 }
4129
4130 /*
4131 * Check if temperature compensation is supported.
4132 */
4133 if (tssi_bounds[4] == 0xff || step == 0xff)
4134 return 0;
4135
4136 /*
4137 * Read current TSSI (BBP 49).
4138 */
4139 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4140
4141 /*
4142 * Compare TSSI value (BBP49) with the compensation boundaries
4143 * from the EEPROM and increase or decrease tx power.
4144 */
4145 for (i = 0; i <= 3; i++) {
4146 if (current_tssi > tssi_bounds[i])
4147 break;
4148 }
4149
4150 if (i == 4) {
4151 for (i = 8; i >= 5; i--) {
4152 if (current_tssi < tssi_bounds[i])
4153 break;
4154 }
4155 }
4156
4157 return (i - 4) * step;
4158 }
4159
4160 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4161 enum nl80211_band band)
4162 {
4163 u16 eeprom;
4164 u8 comp_en;
4165 u8 comp_type;
4166 int comp_value = 0;
4167
4168 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4169
4170 /*
4171 * HT40 compensation not required.
4172 */
4173 if (eeprom == 0xffff ||
4174 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4175 return 0;
4176
4177 if (band == NL80211_BAND_2GHZ) {
4178 comp_en = rt2x00_get_field16(eeprom,
4179 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4180 if (comp_en) {
4181 comp_type = rt2x00_get_field16(eeprom,
4182 EEPROM_TXPOWER_DELTA_TYPE_2G);
4183 comp_value = rt2x00_get_field16(eeprom,
4184 EEPROM_TXPOWER_DELTA_VALUE_2G);
4185 if (!comp_type)
4186 comp_value = -comp_value;
4187 }
4188 } else {
4189 comp_en = rt2x00_get_field16(eeprom,
4190 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4191 if (comp_en) {
4192 comp_type = rt2x00_get_field16(eeprom,
4193 EEPROM_TXPOWER_DELTA_TYPE_5G);
4194 comp_value = rt2x00_get_field16(eeprom,
4195 EEPROM_TXPOWER_DELTA_VALUE_5G);
4196 if (!comp_type)
4197 comp_value = -comp_value;
4198 }
4199 }
4200
4201 return comp_value;
4202 }
4203
4204 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4205 int power_level, int max_power)
4206 {
4207 int delta;
4208
4209 if (rt2x00_has_cap_power_limit(rt2x00dev))
4210 return 0;
4211
4212 /*
4213 * XXX: We don't know the maximum transmit power of our hardware since
4214 * the EEPROM doesn't expose it. We only know that we are calibrated
4215 * to 100% tx power.
4216 *
4217 * Hence, we assume the regulatory limit that cfg80211 calulated for
4218 * the current channel is our maximum and if we are requested to lower
4219 * the value we just reduce our tx power accordingly.
4220 */
4221 delta = power_level - max_power;
4222 return min(delta, 0);
4223 }
4224
4225 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4226 enum nl80211_band band, int power_level,
4227 u8 txpower, int delta)
4228 {
4229 u16 eeprom;
4230 u8 criterion;
4231 u8 eirp_txpower;
4232 u8 eirp_txpower_criterion;
4233 u8 reg_limit;
4234
4235 if (rt2x00_rt(rt2x00dev, RT3593))
4236 return min_t(u8, txpower, 0xc);
4237
4238 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4239 /*
4240 * Check if eirp txpower exceed txpower_limit.
4241 * We use OFDM 6M as criterion and its eirp txpower
4242 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4243 * .11b data rate need add additional 4dbm
4244 * when calculating eirp txpower.
4245 */
4246 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4247 EEPROM_TXPOWER_BYRATE,
4248 1);
4249 criterion = rt2x00_get_field16(eeprom,
4250 EEPROM_TXPOWER_BYRATE_RATE0);
4251
4252 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4253
4254 if (band == NL80211_BAND_2GHZ)
4255 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4256 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4257 else
4258 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4259 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4260
4261 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4262 (is_rate_b ? 4 : 0) + delta;
4263
4264 reg_limit = (eirp_txpower > power_level) ?
4265 (eirp_txpower - power_level) : 0;
4266 } else
4267 reg_limit = 0;
4268
4269 txpower = max(0, txpower + delta - reg_limit);
4270 return min_t(u8, txpower, 0xc);
4271 }
4272
4273
4274 enum {
4275 TX_PWR_CFG_0_IDX,
4276 TX_PWR_CFG_1_IDX,
4277 TX_PWR_CFG_2_IDX,
4278 TX_PWR_CFG_3_IDX,
4279 TX_PWR_CFG_4_IDX,
4280 TX_PWR_CFG_5_IDX,
4281 TX_PWR_CFG_6_IDX,
4282 TX_PWR_CFG_7_IDX,
4283 TX_PWR_CFG_8_IDX,
4284 TX_PWR_CFG_9_IDX,
4285 TX_PWR_CFG_0_EXT_IDX,
4286 TX_PWR_CFG_1_EXT_IDX,
4287 TX_PWR_CFG_2_EXT_IDX,
4288 TX_PWR_CFG_3_EXT_IDX,
4289 TX_PWR_CFG_4_EXT_IDX,
4290 TX_PWR_CFG_IDX_COUNT,
4291 };
4292
4293 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4294 struct ieee80211_channel *chan,
4295 int power_level)
4296 {
4297 u8 txpower;
4298 u16 eeprom;
4299 u32 regs[TX_PWR_CFG_IDX_COUNT];
4300 unsigned int offset;
4301 enum nl80211_band band = chan->band;
4302 int delta;
4303 int i;
4304
4305 memset(regs, '\0', sizeof(regs));
4306
4307 /* TODO: adapt TX power reduction from the rt28xx code */
4308
4309 /* calculate temperature compensation delta */
4310 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4311
4312 if (band == NL80211_BAND_5GHZ)
4313 offset = 16;
4314 else
4315 offset = 0;
4316
4317 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4318 offset += 8;
4319
4320 /* read the next four txpower values */
4321 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4322 offset);
4323
4324 /* CCK 1MBS,2MBS */
4325 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4326 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4327 txpower, delta);
4328 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4329 TX_PWR_CFG_0_CCK1_CH0, txpower);
4330 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4331 TX_PWR_CFG_0_CCK1_CH1, txpower);
4332 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4333 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4334
4335 /* CCK 5.5MBS,11MBS */
4336 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4337 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4338 txpower, delta);
4339 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4340 TX_PWR_CFG_0_CCK5_CH0, txpower);
4341 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4342 TX_PWR_CFG_0_CCK5_CH1, txpower);
4343 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4344 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4345
4346 /* OFDM 6MBS,9MBS */
4347 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4348 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4349 txpower, delta);
4350 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4351 TX_PWR_CFG_0_OFDM6_CH0, txpower);
4352 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4353 TX_PWR_CFG_0_OFDM6_CH1, txpower);
4354 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4355 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4356
4357 /* OFDM 12MBS,18MBS */
4358 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4359 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4360 txpower, delta);
4361 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4362 TX_PWR_CFG_0_OFDM12_CH0, txpower);
4363 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4364 TX_PWR_CFG_0_OFDM12_CH1, txpower);
4365 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4366 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4367
4368 /* read the next four txpower values */
4369 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4370 offset + 1);
4371
4372 /* OFDM 24MBS,36MBS */
4373 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4374 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4375 txpower, delta);
4376 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4377 TX_PWR_CFG_1_OFDM24_CH0, txpower);
4378 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4379 TX_PWR_CFG_1_OFDM24_CH1, txpower);
4380 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4381 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4382
4383 /* OFDM 48MBS */
4384 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4385 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4386 txpower, delta);
4387 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4388 TX_PWR_CFG_1_OFDM48_CH0, txpower);
4389 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4390 TX_PWR_CFG_1_OFDM48_CH1, txpower);
4391 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4392 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4393
4394 /* OFDM 54MBS */
4395 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4396 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4397 txpower, delta);
4398 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4399 TX_PWR_CFG_7_OFDM54_CH0, txpower);
4400 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4401 TX_PWR_CFG_7_OFDM54_CH1, txpower);
4402 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4403 TX_PWR_CFG_7_OFDM54_CH2, txpower);
4404
4405 /* read the next four txpower values */
4406 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4407 offset + 2);
4408
4409 /* MCS 0,1 */
4410 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4411 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4412 txpower, delta);
4413 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4414 TX_PWR_CFG_1_MCS0_CH0, txpower);
4415 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4416 TX_PWR_CFG_1_MCS0_CH1, txpower);
4417 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4418 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4419
4420 /* MCS 2,3 */
4421 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4422 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4423 txpower, delta);
4424 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4425 TX_PWR_CFG_1_MCS2_CH0, txpower);
4426 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4427 TX_PWR_CFG_1_MCS2_CH1, txpower);
4428 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4429 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4430
4431 /* MCS 4,5 */
4432 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4433 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4434 txpower, delta);
4435 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4436 TX_PWR_CFG_2_MCS4_CH0, txpower);
4437 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4438 TX_PWR_CFG_2_MCS4_CH1, txpower);
4439 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4440 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4441
4442 /* MCS 6 */
4443 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4444 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4445 txpower, delta);
4446 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4447 TX_PWR_CFG_2_MCS6_CH0, txpower);
4448 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4449 TX_PWR_CFG_2_MCS6_CH1, txpower);
4450 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4451 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4452
4453 /* read the next four txpower values */
4454 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4455 offset + 3);
4456
4457 /* MCS 7 */
4458 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4459 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4460 txpower, delta);
4461 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4462 TX_PWR_CFG_7_MCS7_CH0, txpower);
4463 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4464 TX_PWR_CFG_7_MCS7_CH1, txpower);
4465 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4466 TX_PWR_CFG_7_MCS7_CH2, txpower);
4467
4468 /* MCS 8,9 */
4469 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4470 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4471 txpower, delta);
4472 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4473 TX_PWR_CFG_2_MCS8_CH0, txpower);
4474 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4475 TX_PWR_CFG_2_MCS8_CH1, txpower);
4476 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4477 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4478
4479 /* MCS 10,11 */
4480 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4481 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4482 txpower, delta);
4483 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4484 TX_PWR_CFG_2_MCS10_CH0, txpower);
4485 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4486 TX_PWR_CFG_2_MCS10_CH1, txpower);
4487 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4488 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4489
4490 /* MCS 12,13 */
4491 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4492 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4493 txpower, delta);
4494 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4495 TX_PWR_CFG_3_MCS12_CH0, txpower);
4496 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4497 TX_PWR_CFG_3_MCS12_CH1, txpower);
4498 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4499 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4500
4501 /* read the next four txpower values */
4502 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4503 offset + 4);
4504
4505 /* MCS 14 */
4506 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4507 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4508 txpower, delta);
4509 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4510 TX_PWR_CFG_3_MCS14_CH0, txpower);
4511 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4512 TX_PWR_CFG_3_MCS14_CH1, txpower);
4513 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4514 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4515
4516 /* MCS 15 */
4517 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4518 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4519 txpower, delta);
4520 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4521 TX_PWR_CFG_8_MCS15_CH0, txpower);
4522 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4523 TX_PWR_CFG_8_MCS15_CH1, txpower);
4524 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4525 TX_PWR_CFG_8_MCS15_CH2, txpower);
4526
4527 /* MCS 16,17 */
4528 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4529 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4530 txpower, delta);
4531 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4532 TX_PWR_CFG_5_MCS16_CH0, txpower);
4533 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4534 TX_PWR_CFG_5_MCS16_CH1, txpower);
4535 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4536 TX_PWR_CFG_5_MCS16_CH2, txpower);
4537
4538 /* MCS 18,19 */
4539 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4540 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4541 txpower, delta);
4542 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4543 TX_PWR_CFG_5_MCS18_CH0, txpower);
4544 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4545 TX_PWR_CFG_5_MCS18_CH1, txpower);
4546 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4547 TX_PWR_CFG_5_MCS18_CH2, txpower);
4548
4549 /* read the next four txpower values */
4550 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4551 offset + 5);
4552
4553 /* MCS 20,21 */
4554 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4555 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4556 txpower, delta);
4557 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4558 TX_PWR_CFG_6_MCS20_CH0, txpower);
4559 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4560 TX_PWR_CFG_6_MCS20_CH1, txpower);
4561 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4562 TX_PWR_CFG_6_MCS20_CH2, txpower);
4563
4564 /* MCS 22 */
4565 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4566 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4567 txpower, delta);
4568 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4569 TX_PWR_CFG_6_MCS22_CH0, txpower);
4570 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4571 TX_PWR_CFG_6_MCS22_CH1, txpower);
4572 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4573 TX_PWR_CFG_6_MCS22_CH2, txpower);
4574
4575 /* MCS 23 */
4576 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4577 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4578 txpower, delta);
4579 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4580 TX_PWR_CFG_8_MCS23_CH0, txpower);
4581 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4582 TX_PWR_CFG_8_MCS23_CH1, txpower);
4583 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4584 TX_PWR_CFG_8_MCS23_CH2, txpower);
4585
4586 /* read the next four txpower values */
4587 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4588 offset + 6);
4589
4590 /* STBC, MCS 0,1 */
4591 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4592 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4593 txpower, delta);
4594 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4595 TX_PWR_CFG_3_STBC0_CH0, txpower);
4596 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4597 TX_PWR_CFG_3_STBC0_CH1, txpower);
4598 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4599 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4600
4601 /* STBC, MCS 2,3 */
4602 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4603 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4604 txpower, delta);
4605 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4606 TX_PWR_CFG_3_STBC2_CH0, txpower);
4607 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4608 TX_PWR_CFG_3_STBC2_CH1, txpower);
4609 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4610 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4611
4612 /* STBC, MCS 4,5 */
4613 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4614 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4615 txpower, delta);
4616 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4617 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4618 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4619 txpower);
4620
4621 /* STBC, MCS 6 */
4622 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4623 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4624 txpower, delta);
4625 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4626 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4627 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4628 txpower);
4629
4630 /* read the next four txpower values */
4631 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4632 offset + 7);
4633
4634 /* STBC, MCS 7 */
4635 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4636 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4637 txpower, delta);
4638 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4639 TX_PWR_CFG_9_STBC7_CH0, txpower);
4640 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4641 TX_PWR_CFG_9_STBC7_CH1, txpower);
4642 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4643 TX_PWR_CFG_9_STBC7_CH2, txpower);
4644
4645 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4646 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4647 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4648 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4649 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4650 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4651 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4652 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4653 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4654 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4655
4656 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4657 regs[TX_PWR_CFG_0_EXT_IDX]);
4658 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4659 regs[TX_PWR_CFG_1_EXT_IDX]);
4660 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4661 regs[TX_PWR_CFG_2_EXT_IDX]);
4662 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4663 regs[TX_PWR_CFG_3_EXT_IDX]);
4664 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4665 regs[TX_PWR_CFG_4_EXT_IDX]);
4666
4667 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4668 rt2x00_dbg(rt2x00dev,
4669 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4670 (band == NL80211_BAND_5GHZ) ? '5' : '2',
4671 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4672 '4' : '2',
4673 (i > TX_PWR_CFG_9_IDX) ?
4674 (i - TX_PWR_CFG_9_IDX - 1) : i,
4675 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4676 (unsigned long) regs[i]);
4677 }
4678
4679 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4680 struct ieee80211_channel *chan,
4681 int power_level)
4682 {
4683 u32 reg, pwreg;
4684 u16 eeprom;
4685 u32 data, gdata;
4686 u8 t, i;
4687 enum nl80211_band band = chan->band;
4688 int delta;
4689
4690 /* Warn user if bw_comp is set in EEPROM */
4691 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4692
4693 if (delta)
4694 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4695 delta);
4696
4697 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4698 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4699 * driver does as well, though it looks kinda wrong.
4700 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4701 * the hardware has a problem handling 0x20, and as the code initially
4702 * used a fixed offset between HT20 and HT40 rates they had to work-
4703 * around that issue and most likely just forgot about it later on.
4704 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4705 * however, the corresponding EEPROM value is not respected by the
4706 * vendor driver, so maybe this is rather being taken care of the
4707 * TXALC and the driver doesn't need to handle it...?
4708 * Though this is all very awkward, just do as they did, as that's what
4709 * board vendors expected when they populated the EEPROM...
4710 */
4711 for (i = 0; i < 5; i++) {
4712 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4713 EEPROM_TXPOWER_BYRATE,
4714 i * 2);
4715
4716 data = eeprom;
4717
4718 t = eeprom & 0x3f;
4719 if (t == 32)
4720 t++;
4721
4722 gdata = t;
4723
4724 t = (eeprom & 0x3f00) >> 8;
4725 if (t == 32)
4726 t++;
4727
4728 gdata |= (t << 8);
4729
4730 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4731 EEPROM_TXPOWER_BYRATE,
4732 (i * 2) + 1);
4733
4734 t = eeprom & 0x3f;
4735 if (t == 32)
4736 t++;
4737
4738 gdata |= (t << 16);
4739
4740 t = (eeprom & 0x3f00) >> 8;
4741 if (t == 32)
4742 t++;
4743
4744 gdata |= (t << 24);
4745 data |= (eeprom << 16);
4746
4747 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4748 /* HT20 */
4749 if (data != 0xffffffff)
4750 rt2800_register_write(rt2x00dev,
4751 TX_PWR_CFG_0 + (i * 4),
4752 data);
4753 } else {
4754 /* HT40 */
4755 if (gdata != 0xffffffff)
4756 rt2800_register_write(rt2x00dev,
4757 TX_PWR_CFG_0 + (i * 4),
4758 gdata);
4759 }
4760 }
4761
4762 /* Aparently Ralink ran out of space in the BYRATE calibration section
4763 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4764 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4765 * power-offsets more space would be needed. Ralink decided to keep the
4766 * EEPROM layout untouched and rather have some shared values covering
4767 * multiple bitrates.
4768 * Populate the registers not covered by the EEPROM in the same way the
4769 * vendor driver does.
4770 */
4771
4772 /* For OFDM 54MBS use value from OFDM 48MBS */
4773 pwreg = 0;
4774 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
4775 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4776 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4777
4778 /* For MCS 7 use value from MCS 6 */
4779 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
4780 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4781 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4782 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4783
4784 /* For MCS 15 use value from MCS 14 */
4785 pwreg = 0;
4786 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
4787 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4788 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4789 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4790
4791 /* For STBC MCS 7 use value from STBC MCS 6 */
4792 pwreg = 0;
4793 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
4794 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4795 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4796 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4797
4798 rt2800_config_alc(rt2x00dev, chan, power_level);
4799
4800 /* TODO: temperature compensation code! */
4801 }
4802
4803 /*
4804 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4805 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4806 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4807 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4808 * Reference per rate transmit power values are located in the EEPROM at
4809 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4810 * current conditions (i.e. band, bandwidth, temperature, user settings).
4811 */
4812 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4813 struct ieee80211_channel *chan,
4814 int power_level)
4815 {
4816 u8 txpower, r1;
4817 u16 eeprom;
4818 u32 reg, offset;
4819 int i, is_rate_b, delta, power_ctrl;
4820 enum nl80211_band band = chan->band;
4821
4822 /*
4823 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4824 * value read from EEPROM (different for 2GHz and for 5GHz).
4825 */
4826 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4827
4828 /*
4829 * Calculate temperature compensation. Depends on measurement of current
4830 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4831 * to temperature or maybe other factors) is smaller or bigger than
4832 * expected. We adjust it, based on TSSI reference and boundaries values
4833 * provided in EEPROM.
4834 */
4835 switch (rt2x00dev->chip.rt) {
4836 case RT2860:
4837 case RT2872:
4838 case RT2883:
4839 case RT3070:
4840 case RT3071:
4841 case RT3090:
4842 case RT3572:
4843 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4844 break;
4845 default:
4846 /* TODO: temperature compensation code for other chips. */
4847 break;
4848 }
4849
4850 /*
4851 * Decrease power according to user settings, on devices with unknown
4852 * maximum tx power. For other devices we take user power_level into
4853 * consideration on rt2800_compensate_txpower().
4854 */
4855 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4856 chan->max_power);
4857
4858 /*
4859 * BBP_R1 controls TX power for all rates, it allow to set the following
4860 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4861 *
4862 * TODO: we do not use +6 dBm option to do not increase power beyond
4863 * regulatory limit, however this could be utilized for devices with
4864 * CAPABILITY_POWER_LIMIT.
4865 */
4866 if (delta <= -12) {
4867 power_ctrl = 2;
4868 delta += 12;
4869 } else if (delta <= -6) {
4870 power_ctrl = 1;
4871 delta += 6;
4872 } else {
4873 power_ctrl = 0;
4874 }
4875 r1 = rt2800_bbp_read(rt2x00dev, 1);
4876 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4877 rt2800_bbp_write(rt2x00dev, 1, r1);
4878
4879 offset = TX_PWR_CFG_0;
4880
4881 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4882 /* just to be safe */
4883 if (offset > TX_PWR_CFG_4)
4884 break;
4885
4886 reg = rt2800_register_read(rt2x00dev, offset);
4887
4888 /* read the next four txpower values */
4889 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4890 EEPROM_TXPOWER_BYRATE,
4891 i);
4892
4893 is_rate_b = i ? 0 : 1;
4894 /*
4895 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4896 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4897 * TX_PWR_CFG_4: unknown
4898 */
4899 txpower = rt2x00_get_field16(eeprom,
4900 EEPROM_TXPOWER_BYRATE_RATE0);
4901 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4902 power_level, txpower, delta);
4903 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4904
4905 /*
4906 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4907 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4908 * TX_PWR_CFG_4: unknown
4909 */
4910 txpower = rt2x00_get_field16(eeprom,
4911 EEPROM_TXPOWER_BYRATE_RATE1);
4912 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4913 power_level, txpower, delta);
4914 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4915
4916 /*
4917 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4918 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4919 * TX_PWR_CFG_4: unknown
4920 */
4921 txpower = rt2x00_get_field16(eeprom,
4922 EEPROM_TXPOWER_BYRATE_RATE2);
4923 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4924 power_level, txpower, delta);
4925 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4926
4927 /*
4928 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4929 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4930 * TX_PWR_CFG_4: unknown
4931 */
4932 txpower = rt2x00_get_field16(eeprom,
4933 EEPROM_TXPOWER_BYRATE_RATE3);
4934 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4935 power_level, txpower, delta);
4936 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4937
4938 /* read the next four txpower values */
4939 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4940 EEPROM_TXPOWER_BYRATE,
4941 i + 1);
4942
4943 is_rate_b = 0;
4944 /*
4945 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4946 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4947 * TX_PWR_CFG_4: unknown
4948 */
4949 txpower = rt2x00_get_field16(eeprom,
4950 EEPROM_TXPOWER_BYRATE_RATE0);
4951 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4952 power_level, txpower, delta);
4953 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4954
4955 /*
4956 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4957 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4958 * TX_PWR_CFG_4: unknown
4959 */
4960 txpower = rt2x00_get_field16(eeprom,
4961 EEPROM_TXPOWER_BYRATE_RATE1);
4962 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4963 power_level, txpower, delta);
4964 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4965
4966 /*
4967 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4968 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4969 * TX_PWR_CFG_4: unknown
4970 */
4971 txpower = rt2x00_get_field16(eeprom,
4972 EEPROM_TXPOWER_BYRATE_RATE2);
4973 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4974 power_level, txpower, delta);
4975 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4976
4977 /*
4978 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4979 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4980 * TX_PWR_CFG_4: unknown
4981 */
4982 txpower = rt2x00_get_field16(eeprom,
4983 EEPROM_TXPOWER_BYRATE_RATE3);
4984 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4985 power_level, txpower, delta);
4986 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4987
4988 rt2800_register_write(rt2x00dev, offset, reg);
4989
4990 /* next TX_PWR_CFG register */
4991 offset += 4;
4992 }
4993 }
4994
4995 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4996 struct ieee80211_channel *chan,
4997 int power_level)
4998 {
4999 if (rt2x00_rt(rt2x00dev, RT3593))
5000 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5001 else if (rt2x00_rt(rt2x00dev, RT6352))
5002 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5003 else
5004 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5005 }
5006
5007 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5008 {
5009 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5010 rt2x00dev->tx_power);
5011 }
5012 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5013
5014 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5015 {
5016 u32 tx_pin;
5017 u8 rfcsr;
5018 unsigned long min_sleep = 0;
5019
5020 /*
5021 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5022 * designed to be controlled in oscillation frequency by a voltage
5023 * input. Maybe the temperature will affect the frequency of
5024 * oscillation to be shifted. The VCO calibration will be called
5025 * periodically to adjust the frequency to be precision.
5026 */
5027
5028 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5029 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5030 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5031
5032 switch (rt2x00dev->chip.rf) {
5033 case RF2020:
5034 case RF3020:
5035 case RF3021:
5036 case RF3022:
5037 case RF3320:
5038 case RF3052:
5039 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5040 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5041 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5042 break;
5043 case RF3053:
5044 case RF3070:
5045 case RF3290:
5046 case RF5350:
5047 case RF5360:
5048 case RF5362:
5049 case RF5370:
5050 case RF5372:
5051 case RF5390:
5052 case RF5392:
5053 case RF5592:
5054 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5055 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5056 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5057 min_sleep = 1000;
5058 break;
5059 case RF7620:
5060 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5061 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5062 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5063 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5064 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5065 min_sleep = 2000;
5066 break;
5067 default:
5068 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5069 rt2x00dev->chip.rf);
5070 return;
5071 }
5072
5073 if (min_sleep > 0)
5074 usleep_range(min_sleep, min_sleep * 2);
5075
5076 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5077 if (rt2x00dev->rf_channel <= 14) {
5078 switch (rt2x00dev->default_ant.tx_chain_num) {
5079 case 3:
5080 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5081 /* fall through */
5082 case 2:
5083 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5084 /* fall through */
5085 case 1:
5086 default:
5087 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5088 break;
5089 }
5090 } else {
5091 switch (rt2x00dev->default_ant.tx_chain_num) {
5092 case 3:
5093 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5094 /* fall through */
5095 case 2:
5096 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5097 /* fall through */
5098 case 1:
5099 default:
5100 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5101 break;
5102 }
5103 }
5104 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5105
5106 if (rt2x00_rt(rt2x00dev, RT6352)) {
5107 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5108 rt2800_bbp_write(rt2x00dev, 91, 0x07);
5109 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5110 rt2800_bbp_write(rt2x00dev, 195, 128);
5111 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5112 rt2800_bbp_write(rt2x00dev, 195, 170);
5113 rt2800_bbp_write(rt2x00dev, 196, 0x12);
5114 rt2800_bbp_write(rt2x00dev, 195, 171);
5115 rt2800_bbp_write(rt2x00dev, 196, 0x10);
5116 } else {
5117 rt2800_bbp_write(rt2x00dev, 91, 0x06);
5118 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5119 rt2800_bbp_write(rt2x00dev, 195, 128);
5120 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5121 rt2800_bbp_write(rt2x00dev, 195, 170);
5122 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5123 rt2800_bbp_write(rt2x00dev, 195, 171);
5124 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5125 }
5126
5127 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5128 rt2800_bbp_write(rt2x00dev, 75, 0x68);
5129 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5130 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5131 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5132 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5133 }
5134
5135 /* On 11A, We should delay and wait RF/BBP to be stable
5136 * and the appropriate time should be 1000 micro seconds
5137 * 2005/06/05 - On 11G, we also need this delay time.
5138 * Otherwise it's difficult to pass the WHQL.
5139 */
5140 usleep_range(1000, 1500);
5141 }
5142 }
5143 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5144
5145 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5146 struct rt2x00lib_conf *libconf)
5147 {
5148 u32 reg;
5149
5150 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5151 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5152 libconf->conf->short_frame_max_tx_count);
5153 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5154 libconf->conf->long_frame_max_tx_count);
5155 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5156 }
5157
5158 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5159 struct rt2x00lib_conf *libconf)
5160 {
5161 enum dev_state state =
5162 (libconf->conf->flags & IEEE80211_CONF_PS) ?
5163 STATE_SLEEP : STATE_AWAKE;
5164 u32 reg;
5165
5166 if (state == STATE_SLEEP) {
5167 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5168
5169 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5170 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5171 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5172 libconf->conf->listen_interval - 1);
5173 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5174 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5175
5176 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5177 } else {
5178 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5179 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5180 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5181 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5182 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5183
5184 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5185 }
5186 }
5187
5188 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5189 struct rt2x00lib_conf *libconf,
5190 const unsigned int flags)
5191 {
5192 /* Always recalculate LNA gain before changing configuration */
5193 rt2800_config_lna_gain(rt2x00dev, libconf);
5194
5195 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5196 rt2800_config_channel(rt2x00dev, libconf->conf,
5197 &libconf->rf, &libconf->channel);
5198 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5199 libconf->conf->power_level);
5200 }
5201 if (flags & IEEE80211_CONF_CHANGE_POWER)
5202 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5203 libconf->conf->power_level);
5204 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5205 rt2800_config_retry_limit(rt2x00dev, libconf);
5206 if (flags & IEEE80211_CONF_CHANGE_PS)
5207 rt2800_config_ps(rt2x00dev, libconf);
5208 }
5209 EXPORT_SYMBOL_GPL(rt2800_config);
5210
5211 /*
5212 * Link tuning
5213 */
5214 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5215 {
5216 u32 reg;
5217
5218 /*
5219 * Update FCS error count from register.
5220 */
5221 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5222 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5223 }
5224 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5225
5226 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5227 {
5228 u8 vgc;
5229
5230 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5231 if (rt2x00_rt(rt2x00dev, RT3070) ||
5232 rt2x00_rt(rt2x00dev, RT3071) ||
5233 rt2x00_rt(rt2x00dev, RT3090) ||
5234 rt2x00_rt(rt2x00dev, RT3290) ||
5235 rt2x00_rt(rt2x00dev, RT3390) ||
5236 rt2x00_rt(rt2x00dev, RT3572) ||
5237 rt2x00_rt(rt2x00dev, RT3593) ||
5238 rt2x00_rt(rt2x00dev, RT5390) ||
5239 rt2x00_rt(rt2x00dev, RT5392) ||
5240 rt2x00_rt(rt2x00dev, RT5592) ||
5241 rt2x00_rt(rt2x00dev, RT6352))
5242 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5243 else
5244 vgc = 0x2e + rt2x00dev->lna_gain;
5245 } else { /* 5GHZ band */
5246 if (rt2x00_rt(rt2x00dev, RT3593))
5247 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5248 else if (rt2x00_rt(rt2x00dev, RT5592))
5249 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5250 else {
5251 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5252 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5253 else
5254 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5255 }
5256 }
5257
5258 return vgc;
5259 }
5260
5261 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5262 struct link_qual *qual, u8 vgc_level)
5263 {
5264 if (qual->vgc_level != vgc_level) {
5265 if (rt2x00_rt(rt2x00dev, RT3572) ||
5266 rt2x00_rt(rt2x00dev, RT3593)) {
5267 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5268 vgc_level);
5269 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5270 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5271 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5272 } else {
5273 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5274 }
5275
5276 qual->vgc_level = vgc_level;
5277 qual->vgc_level_reg = vgc_level;
5278 }
5279 }
5280
5281 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5282 {
5283 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5284 }
5285 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5286
5287 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5288 const u32 count)
5289 {
5290 u8 vgc;
5291
5292 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5293 return;
5294
5295 /* When RSSI is better than a certain threshold, increase VGC
5296 * with a chip specific value in order to improve the balance
5297 * between sensibility and noise isolation.
5298 */
5299
5300 vgc = rt2800_get_default_vgc(rt2x00dev);
5301
5302 switch (rt2x00dev->chip.rt) {
5303 case RT3572:
5304 case RT3593:
5305 if (qual->rssi > -65) {
5306 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5307 vgc += 0x20;
5308 else
5309 vgc += 0x10;
5310 }
5311 break;
5312
5313 case RT5592:
5314 if (qual->rssi > -65)
5315 vgc += 0x20;
5316 break;
5317
5318 default:
5319 if (qual->rssi > -80)
5320 vgc += 0x10;
5321 break;
5322 }
5323
5324 rt2800_set_vgc(rt2x00dev, qual, vgc);
5325 }
5326 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5327
5328 /*
5329 * Initialization functions.
5330 */
5331 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5332 {
5333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5334 u32 reg;
5335 u16 eeprom;
5336 unsigned int i;
5337 int ret;
5338
5339 rt2800_disable_wpdma(rt2x00dev);
5340
5341 ret = rt2800_drv_init_registers(rt2x00dev);
5342 if (ret)
5343 return ret;
5344
5345 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5346 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5347
5348 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5349
5350 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5351 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5352 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5353 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5354 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5355 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5356 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5357 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5358
5359 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5360
5361 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5362 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5363 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5364 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5365
5366 if (rt2x00_rt(rt2x00dev, RT3290)) {
5367 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5368 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5369 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5370 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5371 }
5372
5373 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5374 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5375 rt2x00_set_field32(&reg, LDO0_EN, 1);
5376 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5377 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5378 }
5379
5380 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5381 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5382 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5383 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5384 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5385
5386 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5387 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5388 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5389
5390 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5391 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5392 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5393 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5394 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5395 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5396
5397 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5398 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5399 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5400 }
5401
5402 if (rt2x00_rt(rt2x00dev, RT3071) ||
5403 rt2x00_rt(rt2x00dev, RT3090) ||
5404 rt2x00_rt(rt2x00dev, RT3290) ||
5405 rt2x00_rt(rt2x00dev, RT3390)) {
5406
5407 if (rt2x00_rt(rt2x00dev, RT3290))
5408 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5409 0x00000404);
5410 else
5411 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5412 0x00000400);
5413
5414 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5415 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5416 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5417 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5418 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5419 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5420 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5421 0x0000002c);
5422 else
5423 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5424 0x0000000f);
5425 } else {
5426 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5427 }
5428 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5429 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5430
5431 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5432 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5433 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5434 } else {
5435 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5436 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5437 }
5438 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5439 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5440 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5441 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5442 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5443 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5444 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5445 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5446 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5447 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5448 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5449 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5450 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5451 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5452 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5453 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5454 if (rt2x00_get_field16(eeprom,
5455 EEPROM_NIC_CONF1_DAC_TEST))
5456 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5457 0x0000001f);
5458 else
5459 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5460 0x0000000f);
5461 } else {
5462 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5463 0x00000000);
5464 }
5465 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5466 rt2x00_rt(rt2x00dev, RT5392) ||
5467 rt2x00_rt(rt2x00dev, RT6352)) {
5468 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5469 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5470 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5471 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5472 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5473 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5474 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5475 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5476 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5477 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5478 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5479 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5480 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5481 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5482 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5483 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5484 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5485 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5486 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5487 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5488 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5489 0x3630363A);
5490 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5491 0x3630363A);
5492 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5493 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5494 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5495 } else {
5496 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5497 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5498 }
5499
5500 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5501 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5502 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5503 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5504 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5505 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5506 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5507 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5508 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5509 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5510
5511 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5512 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5513 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5514 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5515 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5516
5517 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5518 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5519 if (rt2x00_is_usb(rt2x00dev)) {
5520 drv_data->max_psdu = 3;
5521 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5522 rt2x00_rt(rt2x00dev, RT2883) ||
5523 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5524 drv_data->max_psdu = 2;
5525 } else {
5526 drv_data->max_psdu = 1;
5527 }
5528 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5529 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5530 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5531 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5532
5533 reg = rt2800_register_read(rt2x00dev, LED_CFG);
5534 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5535 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5536 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5537 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5538 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5539 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5540 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5541 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5542
5543 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5544
5545 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5546 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5547 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5548 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5549 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5550 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5551 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5552 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5553
5554 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5555 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5556 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5557 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5558 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5559 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5560 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5561 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5562 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5563
5564 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5565 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5566 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5567 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5568 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5569 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5570 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5571 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5572 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5573 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5574 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5575 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5576
5577 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5578 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5579 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5580 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5581 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5582 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5583 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5584 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5585 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5586 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5587 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5588 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5589
5590 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5591 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5592 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5593 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5594 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5595 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5596 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5597 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5598 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5599 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5600 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5601 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5602
5603 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5604 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5605 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5606 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5607 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5608 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5609 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5610 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5611 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5612 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5613 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5614 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5615
5616 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5617 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5618 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5619 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5620 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5621 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5622 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5623 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5624 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5625 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5626 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
5627 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5628
5629 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
5630 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5631 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
5632 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5633 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5634 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5635 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5636 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5637 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5638 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5639 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
5640 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5641
5642 if (rt2x00_is_usb(rt2x00dev)) {
5643 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5644
5645 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
5646 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5647 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5648 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5649 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5650 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5651 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5652 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5653 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5654 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5655 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5656 }
5657
5658 /*
5659 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5660 * although it is reserved.
5661 */
5662 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
5663 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5664 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5665 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5666 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5667 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5668 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5669 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5670 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5671 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5672 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5673 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5674
5675 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5676 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
5677
5678 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
5679 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
5680 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5681 IEEE80211_MAX_RTS_THRESHOLD);
5682 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
5683 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5684
5685 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5686
5687 /*
5688 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5689 * time should be set to 16. However, the original Ralink driver uses
5690 * 16 for both and indeed using a value of 10 for CCK SIFS results in
5691 * connection problems with 11g + CTS protection. Hence, use the same
5692 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5693 */
5694 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
5695 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5696 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
5697 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5698 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
5699 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5700 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5701
5702 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5703
5704 /*
5705 * ASIC will keep garbage value after boot, clear encryption keys.
5706 */
5707 for (i = 0; i < 4; i++)
5708 rt2800_register_write(rt2x00dev,
5709 SHARED_KEY_MODE_ENTRY(i), 0);
5710
5711 for (i = 0; i < 256; i++) {
5712 rt2800_config_wcid(rt2x00dev, NULL, i);
5713 rt2800_delete_wcid_attr(rt2x00dev, i);
5714 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5715 }
5716
5717 /*
5718 * Clear all beacons
5719 */
5720 for (i = 0; i < 8; i++)
5721 rt2800_clear_beacon_register(rt2x00dev, i);
5722
5723 if (rt2x00_is_usb(rt2x00dev)) {
5724 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5725 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
5726 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5727 } else if (rt2x00_is_pcie(rt2x00dev)) {
5728 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5729 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
5730 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5731 }
5732
5733 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
5734 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5735 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5736 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5737 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5738 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5739 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5740 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5741 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5742 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5743
5744 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
5745 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5746 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5747 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5748 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5749 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5750 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5751 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5752 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5753 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5754
5755 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
5756 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5757 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5758 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5759 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5760 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5761 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5762 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5763 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5764 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5765
5766 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
5767 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5768 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5769 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5770 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5771 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5772
5773 /*
5774 * Do not force the BA window size, we use the TXWI to set it
5775 */
5776 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
5777 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5778 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5779 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5780
5781 /*
5782 * We must clear the error counters.
5783 * These registers are cleared on read,
5784 * so we may pass a useless variable to store the value.
5785 */
5786 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5787 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
5788 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
5789 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
5790 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
5791 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
5792
5793 /*
5794 * Setup leadtime for pre tbtt interrupt to 6ms
5795 */
5796 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
5797 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5798 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5799
5800 /*
5801 * Set up channel statistics timer
5802 */
5803 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
5804 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5805 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5806 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5807 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5808 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5809 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5810
5811 return 0;
5812 }
5813
5814 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5815 {
5816 unsigned int i;
5817 u32 reg;
5818
5819 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5820 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
5821 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5822 return 0;
5823
5824 udelay(REGISTER_BUSY_DELAY);
5825 }
5826
5827 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5828 return -EACCES;
5829 }
5830
5831 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5832 {
5833 unsigned int i;
5834 u8 value;
5835
5836 /*
5837 * BBP was enabled after firmware was loaded,
5838 * but we need to reactivate it now.
5839 */
5840 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5841 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5842 msleep(1);
5843
5844 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5845 value = rt2800_bbp_read(rt2x00dev, 0);
5846 if ((value != 0xff) && (value != 0x00))
5847 return 0;
5848 udelay(REGISTER_BUSY_DELAY);
5849 }
5850
5851 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5852 return -EACCES;
5853 }
5854
5855 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5856 {
5857 u8 value;
5858
5859 value = rt2800_bbp_read(rt2x00dev, 4);
5860 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5861 rt2800_bbp_write(rt2x00dev, 4, value);
5862 }
5863
5864 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5865 {
5866 rt2800_bbp_write(rt2x00dev, 142, 1);
5867 rt2800_bbp_write(rt2x00dev, 143, 57);
5868 }
5869
5870 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5871 {
5872 static const u8 glrt_table[] = {
5873 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5874 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5875 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5876 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5877 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5878 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5879 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5880 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5881 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5882 };
5883 int i;
5884
5885 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5886 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5887 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5888 }
5889 };
5890
5891 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5892 {
5893 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5894 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5895 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5896 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5897 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5898 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5899 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5900 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5901 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5902 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5903 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5904 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5905 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5906 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5907 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5908 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5909 }
5910
5911 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5912 {
5913 u16 eeprom;
5914 u8 value;
5915
5916 value = rt2800_bbp_read(rt2x00dev, 138);
5917 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
5918 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5919 value |= 0x20;
5920 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5921 value &= ~0x02;
5922 rt2800_bbp_write(rt2x00dev, 138, value);
5923 }
5924
5925 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5926 {
5927 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5928
5929 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5930 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5931
5932 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5933 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5934
5935 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5936
5937 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5938 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5939
5940 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5941
5942 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5943
5944 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5945
5946 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5947
5948 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5949
5950 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5951
5952 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5953
5954 rt2800_bbp_write(rt2x00dev, 105, 0x01);
5955
5956 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5957 }
5958
5959 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5960 {
5961 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5962 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5963
5964 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5965 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5966 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5967 } else {
5968 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5969 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5970 }
5971
5972 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5973
5974 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5975
5976 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5977
5978 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5979
5980 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5981 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5982 else
5983 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5984
5985 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5986
5987 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5988
5989 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5990
5991 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5992
5993 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5994
5995 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5996 }
5997
5998 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5999 {
6000 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6001 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6002
6003 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6004 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6005
6006 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6007
6008 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6009 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6010 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6011
6012 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6013
6014 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6015
6016 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6017
6018 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6019
6020 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6021
6022 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6023
6024 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6025 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6026 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6027 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6028 else
6029 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6030
6031 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6032
6033 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6034
6035 if (rt2x00_rt(rt2x00dev, RT3071) ||
6036 rt2x00_rt(rt2x00dev, RT3090))
6037 rt2800_disable_unused_dac_adc(rt2x00dev);
6038 }
6039
6040 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6041 {
6042 u8 value;
6043
6044 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6045
6046 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6047
6048 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6049 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6050
6051 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6052
6053 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6054 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6055 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6056 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6057
6058 rt2800_bbp_write(rt2x00dev, 77, 0x58);
6059
6060 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6061
6062 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6063 rt2800_bbp_write(rt2x00dev, 79, 0x18);
6064 rt2800_bbp_write(rt2x00dev, 80, 0x09);
6065 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6066
6067 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6068
6069 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6070
6071 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6072
6073 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6074
6075 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6076
6077 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6078
6079 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6080
6081 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6082
6083 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6084
6085 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6086
6087 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6088
6089 rt2800_bbp_write(rt2x00dev, 67, 0x24);
6090 rt2800_bbp_write(rt2x00dev, 143, 0x04);
6091 rt2800_bbp_write(rt2x00dev, 142, 0x99);
6092 rt2800_bbp_write(rt2x00dev, 150, 0x30);
6093 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6094 rt2800_bbp_write(rt2x00dev, 152, 0x20);
6095 rt2800_bbp_write(rt2x00dev, 153, 0x34);
6096 rt2800_bbp_write(rt2x00dev, 154, 0x40);
6097 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6098 rt2800_bbp_write(rt2x00dev, 253, 0x04);
6099
6100 value = rt2800_bbp_read(rt2x00dev, 47);
6101 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6102 rt2800_bbp_write(rt2x00dev, 47, value);
6103
6104 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6105 value = rt2800_bbp_read(rt2x00dev, 3);
6106 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6107 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6108 rt2800_bbp_write(rt2x00dev, 3, value);
6109 }
6110
6111 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6112 {
6113 rt2800_bbp_write(rt2x00dev, 3, 0x00);
6114 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6115
6116 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6117
6118 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6119
6120 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6121 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6122
6123 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6124
6125 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6126 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6127 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6128 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6129
6130 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6131
6132 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6133
6134 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6135 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6136 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6137
6138 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6139
6140 if (rt2x00_rt(rt2x00dev, RT5350)) {
6141 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6142 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6143 } else {
6144 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6145 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6146 }
6147
6148 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6149
6150 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6151
6152 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6153
6154 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6155
6156 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6157
6158 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6159
6160 if (rt2x00_rt(rt2x00dev, RT5350)) {
6161 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6162 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6163 } else {
6164 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6165 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6166 }
6167
6168 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6169
6170 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6171
6172 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6173 /* Set ITxBF timeout to 0x9c40=1000msec */
6174 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6175 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6176 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6177 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6178 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6179 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6180 /* Reprogram the inband interface to put right values in RXWI */
6181 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6182 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6183 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6184 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6185 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6186 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6187 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6188 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6189
6190 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6191
6192 if (rt2x00_rt(rt2x00dev, RT5350)) {
6193 /* Antenna Software OFDM */
6194 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6195 /* Antenna Software CCK */
6196 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6197 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6198 /* Clear previously selected antenna */
6199 rt2800_bbp_write(rt2x00dev, 154, 0);
6200 }
6201 }
6202
6203 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6204 {
6205 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6206 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6207
6208 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6209 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6210
6211 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6212
6213 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6214 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6215 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6216
6217 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6218
6219 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6220
6221 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6222
6223 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6224
6225 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6226
6227 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6228
6229 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6230 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6231 else
6232 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6233
6234 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6235
6236 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6237
6238 rt2800_disable_unused_dac_adc(rt2x00dev);
6239 }
6240
6241 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6242 {
6243 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6244
6245 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6246 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6247
6248 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6249 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6250
6251 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6252
6253 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6254 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6255 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6256
6257 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6258
6259 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6260
6261 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6262
6263 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6264
6265 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6266
6267 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6268
6269 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6270
6271 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6272
6273 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6274
6275 rt2800_disable_unused_dac_adc(rt2x00dev);
6276 }
6277
6278 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6279 {
6280 rt2800_init_bbp_early(rt2x00dev);
6281
6282 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6283 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6284 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6285 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6286
6287 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6288
6289 /* Enable DC filter */
6290 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6291 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6292 }
6293
6294 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6295 {
6296 int ant, div_mode;
6297 u16 eeprom;
6298 u8 value;
6299
6300 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6301
6302 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6303
6304 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6305 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6306
6307 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6308
6309 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6310 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6311 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6312 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6313
6314 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6315
6316 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6317
6318 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6319 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6320 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6321
6322 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6323
6324 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6325
6326 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6327
6328 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6329
6330 if (rt2x00_rt(rt2x00dev, RT5392))
6331 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6332
6333 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6334
6335 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6336
6337 if (rt2x00_rt(rt2x00dev, RT5392)) {
6338 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6339 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6340 }
6341
6342 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6343
6344 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6345
6346 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6347
6348 if (rt2x00_rt(rt2x00dev, RT5390))
6349 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6350 else if (rt2x00_rt(rt2x00dev, RT5392))
6351 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6352 else
6353 WARN_ON(1);
6354
6355 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6356
6357 if (rt2x00_rt(rt2x00dev, RT5392)) {
6358 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6359 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6360 }
6361
6362 rt2800_disable_unused_dac_adc(rt2x00dev);
6363
6364 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6365 div_mode = rt2x00_get_field16(eeprom,
6366 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6367 ant = (div_mode == 3) ? 1 : 0;
6368
6369 /* check if this is a Bluetooth combo card */
6370 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6371 u32 reg;
6372
6373 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6374 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6375 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6376 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6377 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6378 if (ant == 0)
6379 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6380 else if (ant == 1)
6381 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6382 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6383 }
6384
6385 /* These chips have hardware RX antenna diversity */
6386 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6387 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6388 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6389 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6390 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6391 }
6392
6393 value = rt2800_bbp_read(rt2x00dev, 152);
6394 if (ant == 0)
6395 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6396 else
6397 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6398 rt2800_bbp_write(rt2x00dev, 152, value);
6399
6400 rt2800_init_freq_calibration(rt2x00dev);
6401 }
6402
6403 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6404 {
6405 int ant, div_mode;
6406 u16 eeprom;
6407 u8 value;
6408
6409 rt2800_init_bbp_early(rt2x00dev);
6410
6411 value = rt2800_bbp_read(rt2x00dev, 105);
6412 rt2x00_set_field8(&value, BBP105_MLD,
6413 rt2x00dev->default_ant.rx_chain_num == 2);
6414 rt2800_bbp_write(rt2x00dev, 105, value);
6415
6416 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6417
6418 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6419 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6420 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6421 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6422 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6423 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6424 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6425 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6426 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6427 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6428 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6429 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6430 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6431 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6432 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6433 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6434 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6435 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6436 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6437 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6438 /* FIXME BBP105 owerwrite */
6439 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6440 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6441 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6442 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6443 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6444 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6445
6446 /* Initialize GLRT (Generalized Likehood Radio Test) */
6447 rt2800_init_bbp_5592_glrt(rt2x00dev);
6448
6449 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6450
6451 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6452 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6453 ant = (div_mode == 3) ? 1 : 0;
6454 value = rt2800_bbp_read(rt2x00dev, 152);
6455 if (ant == 0) {
6456 /* Main antenna */
6457 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6458 } else {
6459 /* Auxiliary antenna */
6460 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6461 }
6462 rt2800_bbp_write(rt2x00dev, 152, value);
6463
6464 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6465 value = rt2800_bbp_read(rt2x00dev, 254);
6466 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6467 rt2800_bbp_write(rt2x00dev, 254, value);
6468 }
6469
6470 rt2800_init_freq_calibration(rt2x00dev);
6471
6472 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6473 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6474 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6475 }
6476
6477 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6478 const u8 reg, const u8 value)
6479 {
6480 rt2800_bbp_write(rt2x00dev, 195, reg);
6481 rt2800_bbp_write(rt2x00dev, 196, value);
6482 }
6483
6484 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6485 const u8 reg, const u8 value)
6486 {
6487 rt2800_bbp_write(rt2x00dev, 158, reg);
6488 rt2800_bbp_write(rt2x00dev, 159, value);
6489 }
6490
6491 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6492 {
6493 rt2800_bbp_write(rt2x00dev, 158, reg);
6494 return rt2800_bbp_read(rt2x00dev, 159);
6495 }
6496
6497 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6498 {
6499 u8 bbp;
6500
6501 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6502 bbp = rt2800_bbp_read(rt2x00dev, 105);
6503 rt2x00_set_field8(&bbp, BBP105_MLD,
6504 rt2x00dev->default_ant.rx_chain_num == 2);
6505 rt2800_bbp_write(rt2x00dev, 105, bbp);
6506
6507 /* Avoid data loss and CRC errors */
6508 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6509
6510 /* Fix I/Q swap issue */
6511 bbp = rt2800_bbp_read(rt2x00dev, 1);
6512 bbp |= 0x04;
6513 rt2800_bbp_write(rt2x00dev, 1, bbp);
6514
6515 /* BBP for G band */
6516 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6517 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6518 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6519 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6520 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6521 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6522 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6523 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6524 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6525 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6526 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6527 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6528 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6529 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6530 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6531 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6532 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6533 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6534 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6535 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6536 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6537 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6538 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6539 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6540 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6541 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6542 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6543 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6544 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6545 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6546 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6547 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6548 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6549 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6550 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6551 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6552 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6553 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6554 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6555 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6556 rt2800_bbp_write(rt2x00dev, 96, 0x00);
6557 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6558 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6559 /* FIXME BBP105 owerwrite */
6560 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6561 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6562 rt2800_bbp_write(rt2x00dev, 109, 0x00);
6563 rt2800_bbp_write(rt2x00dev, 134, 0x10);
6564 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6565 rt2800_bbp_write(rt2x00dev, 137, 0x04);
6566 rt2800_bbp_write(rt2x00dev, 142, 0x30);
6567 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6568 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6569 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6570 rt2800_bbp_write(rt2x00dev, 162, 0x77);
6571 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6572 rt2800_bbp_write(rt2x00dev, 164, 0x00);
6573 rt2800_bbp_write(rt2x00dev, 165, 0x00);
6574 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6575 rt2800_bbp_write(rt2x00dev, 187, 0x00);
6576 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6577 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6578 rt2800_bbp_write(rt2x00dev, 187, 0x01);
6579 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6580 rt2800_bbp_write(rt2x00dev, 189, 0x00);
6581
6582 rt2800_bbp_write(rt2x00dev, 91, 0x06);
6583 rt2800_bbp_write(rt2x00dev, 92, 0x04);
6584 rt2800_bbp_write(rt2x00dev, 93, 0x54);
6585 rt2800_bbp_write(rt2x00dev, 99, 0x50);
6586 rt2800_bbp_write(rt2x00dev, 148, 0x84);
6587 rt2800_bbp_write(rt2x00dev, 167, 0x80);
6588 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6589 rt2800_bbp_write(rt2x00dev, 106, 0x13);
6590
6591 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6592 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6593 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6594 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6595 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6596 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6597 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6598 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6599 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6600 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6601 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6602 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6603 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6604 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6605 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6606 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6607 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6608 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6609 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6610 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6611 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6612 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6613 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6614 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6615 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6616 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6617 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6618 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6619 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6620 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6621 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6622 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6623 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6624 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6625 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6626 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6627 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6628 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6629 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6630 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6631 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6632 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6633 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6634 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6635 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6636 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6637 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6638 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6639 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6640 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6641 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6642 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6643 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6644 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6645 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6646 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6647 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6648 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6649 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6650 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6651 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6652 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6653 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6654 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6655 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6656 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6657 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6658 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6659 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6660 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6661 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6662 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6663 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6664 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6665 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6666 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6667 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6668 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6669 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6670 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6671 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6672 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6673 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6674 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6675
6676 /* BBP for G band DCOC function */
6677 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6678 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6679 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6680 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6681 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6682 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6683 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6684 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6685 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6686 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6687 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6688 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6689 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6690 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6691 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6692 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6693 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6694 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6695 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6696 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6697
6698 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6699 }
6700
6701 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
6702 {
6703 unsigned int i;
6704 u16 eeprom;
6705 u8 reg_id;
6706 u8 value;
6707
6708 if (rt2800_is_305x_soc(rt2x00dev))
6709 rt2800_init_bbp_305x_soc(rt2x00dev);
6710
6711 switch (rt2x00dev->chip.rt) {
6712 case RT2860:
6713 case RT2872:
6714 case RT2883:
6715 rt2800_init_bbp_28xx(rt2x00dev);
6716 break;
6717 case RT3070:
6718 case RT3071:
6719 case RT3090:
6720 rt2800_init_bbp_30xx(rt2x00dev);
6721 break;
6722 case RT3290:
6723 rt2800_init_bbp_3290(rt2x00dev);
6724 break;
6725 case RT3352:
6726 case RT5350:
6727 rt2800_init_bbp_3352(rt2x00dev);
6728 break;
6729 case RT3390:
6730 rt2800_init_bbp_3390(rt2x00dev);
6731 break;
6732 case RT3572:
6733 rt2800_init_bbp_3572(rt2x00dev);
6734 break;
6735 case RT3593:
6736 rt2800_init_bbp_3593(rt2x00dev);
6737 return;
6738 case RT5390:
6739 case RT5392:
6740 rt2800_init_bbp_53xx(rt2x00dev);
6741 break;
6742 case RT5592:
6743 rt2800_init_bbp_5592(rt2x00dev);
6744 return;
6745 case RT6352:
6746 rt2800_init_bbp_6352(rt2x00dev);
6747 break;
6748 }
6749
6750 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
6751 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
6752 EEPROM_BBP_START, i);
6753
6754 if (eeprom != 0xffff && eeprom != 0x0000) {
6755 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6756 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6757 rt2800_bbp_write(rt2x00dev, reg_id, value);
6758 }
6759 }
6760 }
6761
6762 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6763 {
6764 u32 reg;
6765
6766 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
6767 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
6768 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6769 }
6770
6771 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6772 u8 filter_target)
6773 {
6774 unsigned int i;
6775 u8 bbp;
6776 u8 rfcsr;
6777 u8 passband;
6778 u8 stopband;
6779 u8 overtuned = 0;
6780 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
6781
6782 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6783
6784 bbp = rt2800_bbp_read(rt2x00dev, 4);
6785 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6786 rt2800_bbp_write(rt2x00dev, 4, bbp);
6787
6788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
6789 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6790 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6791
6792 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6793 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6794 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6795
6796 /*
6797 * Set power & frequency of passband test tone
6798 */
6799 rt2800_bbp_write(rt2x00dev, 24, 0);
6800
6801 for (i = 0; i < 100; i++) {
6802 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6803 msleep(1);
6804
6805 passband = rt2800_bbp_read(rt2x00dev, 55);
6806 if (passband)
6807 break;
6808 }
6809
6810 /*
6811 * Set power & frequency of stopband test tone
6812 */
6813 rt2800_bbp_write(rt2x00dev, 24, 0x06);
6814
6815 for (i = 0; i < 100; i++) {
6816 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6817 msleep(1);
6818
6819 stopband = rt2800_bbp_read(rt2x00dev, 55);
6820
6821 if ((passband - stopband) <= filter_target) {
6822 rfcsr24++;
6823 overtuned += ((passband - stopband) == filter_target);
6824 } else
6825 break;
6826
6827 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6828 }
6829
6830 rfcsr24 -= !!overtuned;
6831
6832 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6833 return rfcsr24;
6834 }
6835
6836 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6837 const unsigned int rf_reg)
6838 {
6839 u8 rfcsr;
6840
6841 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
6842 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6843 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6844 msleep(1);
6845 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6846 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6847 }
6848
6849 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6850 {
6851 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6852 u8 filter_tgt_bw20;
6853 u8 filter_tgt_bw40;
6854 u8 rfcsr, bbp;
6855
6856 /*
6857 * TODO: sync filter_tgt values with vendor driver
6858 */
6859 if (rt2x00_rt(rt2x00dev, RT3070)) {
6860 filter_tgt_bw20 = 0x16;
6861 filter_tgt_bw40 = 0x19;
6862 } else {
6863 filter_tgt_bw20 = 0x13;
6864 filter_tgt_bw40 = 0x15;
6865 }
6866
6867 drv_data->calibration_bw20 =
6868 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6869 drv_data->calibration_bw40 =
6870 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6871
6872 /*
6873 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6874 */
6875 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
6876 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
6877
6878 /*
6879 * Set back to initial state
6880 */
6881 rt2800_bbp_write(rt2x00dev, 24, 0);
6882
6883 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6884 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6885 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6886
6887 /*
6888 * Set BBP back to BW20
6889 */
6890 bbp = rt2800_bbp_read(rt2x00dev, 4);
6891 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6892 rt2800_bbp_write(rt2x00dev, 4, bbp);
6893 }
6894
6895 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6896 {
6897 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6898 u8 min_gain, rfcsr, bbp;
6899 u16 eeprom;
6900
6901 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
6902
6903 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6904 if (rt2x00_rt(rt2x00dev, RT3070) ||
6905 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6906 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6907 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
6908 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
6909 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6910 }
6911
6912 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6913 if (drv_data->txmixer_gain_24g >= min_gain) {
6914 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6915 drv_data->txmixer_gain_24g);
6916 }
6917
6918 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6919
6920 if (rt2x00_rt(rt2x00dev, RT3090)) {
6921 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6922 bbp = rt2800_bbp_read(rt2x00dev, 138);
6923 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6924 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6925 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6926 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6927 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6928 rt2800_bbp_write(rt2x00dev, 138, bbp);
6929 }
6930
6931 if (rt2x00_rt(rt2x00dev, RT3070)) {
6932 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
6933 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6934 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6935 else
6936 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6937 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6938 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6939 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6940 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6941 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6942 rt2x00_rt(rt2x00dev, RT3090) ||
6943 rt2x00_rt(rt2x00dev, RT3390)) {
6944 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6945 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6946 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6947 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6948 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6949 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6950 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6951
6952 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
6953 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6954 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6955
6956 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
6957 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6958 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6959
6960 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
6961 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6962 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6963 }
6964 }
6965
6966 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6967 {
6968 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6969 u8 rfcsr;
6970 u8 tx_gain;
6971
6972 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
6973 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6974 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6975
6976 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
6977 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6978 RFCSR17_TXMIXER_GAIN);
6979 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6980 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6981
6982 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
6983 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6984 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6985
6986 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
6987 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6988 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6989
6990 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6991 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6992 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6993 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6994
6995 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
6996 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6997 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6998
6999 /* TODO: enable stream mode */
7000 }
7001
7002 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7003 {
7004 u8 reg;
7005 u16 eeprom;
7006
7007 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
7008 reg = rt2800_bbp_read(rt2x00dev, 138);
7009 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7010 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7011 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7012 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7013 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7014 rt2800_bbp_write(rt2x00dev, 138, reg);
7015
7016 reg = rt2800_rfcsr_read(rt2x00dev, 38);
7017 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7018 rt2800_rfcsr_write(rt2x00dev, 38, reg);
7019
7020 reg = rt2800_rfcsr_read(rt2x00dev, 39);
7021 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7022 rt2800_rfcsr_write(rt2x00dev, 39, reg);
7023
7024 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7025
7026 reg = rt2800_rfcsr_read(rt2x00dev, 30);
7027 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7028 rt2800_rfcsr_write(rt2x00dev, 30, reg);
7029 }
7030
7031 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7032 {
7033 rt2800_rf_init_calibration(rt2x00dev, 30);
7034
7035 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7036 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7037 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7038 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7039 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7040 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7041 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7042 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7043 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7044 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7045 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7046 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7047 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7048 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7049 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7050 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7051 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7052 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7053 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7054 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7055 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7056 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7057 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7058 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7059 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7060 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7061 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7062 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7063 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7064 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7065 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7066 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7067 }
7068
7069 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7070 {
7071 u8 rfcsr;
7072 u16 eeprom;
7073 u32 reg;
7074
7075 /* XXX vendor driver do this only for 3070 */
7076 rt2800_rf_init_calibration(rt2x00dev, 30);
7077
7078 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7079 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7080 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7081 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7082 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7083 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7084 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7085 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7086 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7087 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7088 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7089 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7090 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7091 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7092 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7093 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7094 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7095 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7096 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7097
7098 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7099 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7100 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7101 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7102 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7103 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7104 rt2x00_rt(rt2x00dev, RT3090)) {
7105 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7106
7107 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7108 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7109 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7110
7111 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7112 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7113 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7114 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7115 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7116 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7117 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7118 else
7119 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7120 }
7121 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7122
7123 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7124 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7125 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7126 }
7127
7128 rt2800_rx_filter_calibration(rt2x00dev);
7129
7130 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7131 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7132 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7133 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7134
7135 rt2800_led_open_drain_enable(rt2x00dev);
7136 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7137 }
7138
7139 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7140 {
7141 u8 rfcsr;
7142
7143 rt2800_rf_init_calibration(rt2x00dev, 2);
7144
7145 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7146 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7147 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7148 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7149 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7150 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7151 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7152 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7153 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7154 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7155 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7156 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7157 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7158 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7159 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7160 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7161 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7162 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7163 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7164 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7165 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7166 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7167 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7168 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7169 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7170 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7171 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7172 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7173 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7174 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7175 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7176 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7177 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7178 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7179 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7180 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7181 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7182 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7183 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7184 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7185 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7186 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7187 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7188 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7189 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7190 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7191
7192 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7193 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7194 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7195
7196 rt2800_led_open_drain_enable(rt2x00dev);
7197 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7198 }
7199
7200 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7201 {
7202 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7203 &rt2x00dev->cap_flags);
7204 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7205 &rt2x00dev->cap_flags);
7206 u8 rfcsr;
7207
7208 rt2800_rf_init_calibration(rt2x00dev, 30);
7209
7210 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7211 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7212 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7213 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7214 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7215 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7216 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7217 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7218 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7219 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7220 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7221 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7222 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7223 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7224 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7225 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7226 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7227 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7228 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7229 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7230 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7231 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7232 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7233 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7234 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7235 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7236 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7237 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7238 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7239 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7240 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7241 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7242 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7243 rfcsr = 0x01;
7244 if (tx0_ext_pa)
7245 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7246 if (tx1_ext_pa)
7247 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7248 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7249 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7250 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7251 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7252 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7253 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7254 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7255 rfcsr = 0x52;
7256 if (!tx0_ext_pa) {
7257 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7258 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7259 }
7260 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7261 rfcsr = 0x52;
7262 if (!tx1_ext_pa) {
7263 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7264 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7265 }
7266 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7267 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7268 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7269 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7270 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7271 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7272 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7273 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7274 rfcsr = 0x2d;
7275 if (tx0_ext_pa)
7276 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7277 if (tx1_ext_pa)
7278 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7279 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7280 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7281 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7282 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7283 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7284 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7285 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7286 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7287 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7288 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7289 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7290 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7291 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7292 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7293
7294 rt2800_rx_filter_calibration(rt2x00dev);
7295 rt2800_led_open_drain_enable(rt2x00dev);
7296 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7297 }
7298
7299 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7300 {
7301 u32 reg;
7302
7303 rt2800_rf_init_calibration(rt2x00dev, 30);
7304
7305 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7306 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7307 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7308 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7309 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7310 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7311 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7312 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7313 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7314 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7315 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7316 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7317 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7318 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7319 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7320 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7321 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7322 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7323 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7324 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7325 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7326 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7327 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7328 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7329 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7330 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7331 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7332 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7333 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7334 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7335 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7336 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7337
7338 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7339 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7340 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7341
7342 rt2800_rx_filter_calibration(rt2x00dev);
7343
7344 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7345 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7346
7347 rt2800_led_open_drain_enable(rt2x00dev);
7348 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7349 }
7350
7351 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7352 {
7353 u8 rfcsr;
7354 u32 reg;
7355
7356 rt2800_rf_init_calibration(rt2x00dev, 30);
7357
7358 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7359 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7360 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7361 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7362 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7363 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7364 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7365 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7366 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7367 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7368 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7369 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7370 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7371 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7372 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7373 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7374 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7375 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7376 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7377 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7378 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7379 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7380 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7381 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7382 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7383 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7384 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7385 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7386 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7387 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7388 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7389
7390 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7391 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7392 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7393
7394 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7395 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7396 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7397 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7398 msleep(1);
7399 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7400 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7401 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7402 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7403
7404 rt2800_rx_filter_calibration(rt2x00dev);
7405 rt2800_led_open_drain_enable(rt2x00dev);
7406 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7407 }
7408
7409 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7410 {
7411 u8 bbp;
7412 bool txbf_enabled = false; /* FIXME */
7413
7414 bbp = rt2800_bbp_read(rt2x00dev, 105);
7415 if (rt2x00dev->default_ant.rx_chain_num == 1)
7416 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7417 else
7418 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7419 rt2800_bbp_write(rt2x00dev, 105, bbp);
7420
7421 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7422
7423 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7424 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7425 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7426 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7427 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7428 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7429 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7430 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7431
7432 if (txbf_enabled)
7433 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7434 else
7435 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7436
7437 /* SNR mapping */
7438 rt2800_bbp_write(rt2x00dev, 142, 6);
7439 rt2800_bbp_write(rt2x00dev, 143, 160);
7440 rt2800_bbp_write(rt2x00dev, 142, 7);
7441 rt2800_bbp_write(rt2x00dev, 143, 161);
7442 rt2800_bbp_write(rt2x00dev, 142, 8);
7443 rt2800_bbp_write(rt2x00dev, 143, 162);
7444
7445 /* ADC/DAC control */
7446 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7447
7448 /* RX AGC energy lower bound in log2 */
7449 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7450
7451 /* FIXME: BBP 105 owerwrite? */
7452 rt2800_bbp_write(rt2x00dev, 105, 0x04);
7453
7454 }
7455
7456 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7457 {
7458 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7459 u32 reg;
7460 u8 rfcsr;
7461
7462 /* Disable GPIO #4 and #7 function for LAN PE control */
7463 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7464 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7465 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7466 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7467
7468 /* Initialize default register values */
7469 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7470 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7471 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7472 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7473 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7474 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7475 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7476 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7477 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7478 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7479 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7480 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7481 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7482 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7483 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7484 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7485 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7486 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7487 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7488 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7489 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7490 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7491 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7492 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7493 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7494 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7495 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7496 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7497 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7498 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7499 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7500 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7501
7502 /* Initiate calibration */
7503 /* TODO: use rt2800_rf_init_calibration ? */
7504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7505 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7506 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7507
7508 rt2800_freq_cal_mode1(rt2x00dev);
7509
7510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7511 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7512 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7513
7514 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7515 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7516 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7517 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7518 usleep_range(1000, 1500);
7519 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7520 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7521 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7522
7523 /* Set initial values for RX filter calibration */
7524 drv_data->calibration_bw20 = 0x1f;
7525 drv_data->calibration_bw40 = 0x2f;
7526
7527 /* Save BBP 25 & 26 values for later use in channel switching */
7528 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7529 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7530
7531 rt2800_led_open_drain_enable(rt2x00dev);
7532 rt2800_normal_mode_setup_3593(rt2x00dev);
7533
7534 rt3593_post_bbp_init(rt2x00dev);
7535
7536 /* TODO: enable stream mode support */
7537 }
7538
7539 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7540 {
7541 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7542 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7543 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7544 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7545 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7546 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7547 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7548 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7549 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7550 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7551 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7552 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7553 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7554 if (rt2800_clk_is_20mhz(rt2x00dev))
7555 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7556 else
7557 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7558 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7559 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7560 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7561 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7562 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7563 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7564 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7565 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7566 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7567 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7568 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7569 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7570 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7571 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7572 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7573 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7574 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7575 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7576 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7577 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7578 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7579 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7580 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7581 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7582 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7583 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7584 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7585 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7586 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7587 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7588 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7589 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7590 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7591 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7592 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7593 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7594 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7595 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7596 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7597 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7598 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7599 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7600 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7601 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7602 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7603 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7604 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7605 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7606 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7607 }
7608
7609 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7610 {
7611 rt2800_rf_init_calibration(rt2x00dev, 2);
7612
7613 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7614 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7615 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7616 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7617 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7618 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7619 else
7620 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7621 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7622 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7623 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7624 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7625 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7626 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7627 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7628 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7629 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7630 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7631
7632 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7633 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7634 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7635 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7636 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7637 if (rt2x00_is_usb(rt2x00dev) &&
7638 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7639 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7640 else
7641 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7642 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7643 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7644 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7645 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7646
7647 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7648 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7649 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7650 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7651 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7652 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7653 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7654 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7655 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7656 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7657
7658 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7659 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7660 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7661 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7662 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7663 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7664 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7665 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7666 else
7667 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7668 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7669 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7670 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7671
7672 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7673 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7674 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7675 else
7676 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7677 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7678 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
7679 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7680 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7681 else
7682 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
7683 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7684 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7685 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
7686
7687 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7688 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7689 if (rt2x00_is_usb(rt2x00dev))
7690 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7691 else
7692 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7693 } else {
7694 if (rt2x00_is_usb(rt2x00dev))
7695 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7696 else
7697 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7698 }
7699 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7700 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7701
7702 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7703
7704 rt2800_led_open_drain_enable(rt2x00dev);
7705 }
7706
7707 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7708 {
7709 rt2800_rf_init_calibration(rt2x00dev, 2);
7710
7711 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
7712 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7713 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7714 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7715 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7716 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7717 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7718 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7719 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7720 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7721 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7722 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7723 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7724 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7725 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7726 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7727 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7728 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7729 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7730 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7731 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7732 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7733 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7734 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7735 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7736 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7737 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7738 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7739 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7740 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7741 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7742 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7743 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7744 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7745 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7746 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7747 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7748 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7749 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7750 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7751 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7752 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7753 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7754 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7755 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7756 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7757 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7758 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7759 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7760 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7761 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7762 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7763 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7764 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7765 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7766 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7767 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7768 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7769
7770 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7771
7772 rt2800_led_open_drain_enable(rt2x00dev);
7773 }
7774
7775 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7776 {
7777 rt2800_rf_init_calibration(rt2x00dev, 30);
7778
7779 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7780 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7781 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7782 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7783 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7784 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7785 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7786 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7787 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7788 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7789 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7790 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7791 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7792 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7793 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7794 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7795 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7796 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7797 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7798 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7799 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7800
7801 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7802 msleep(1);
7803
7804 rt2800_freq_cal_mode1(rt2x00dev);
7805
7806 /* Enable DC filter */
7807 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7808 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7809
7810 rt2800_normal_mode_setup_5xxx(rt2x00dev);
7811
7812 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7813 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7814
7815 rt2800_led_open_drain_enable(rt2x00dev);
7816 }
7817
7818 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7819 bool set_bw, bool is_ht40)
7820 {
7821 u8 bbp_val;
7822
7823 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7824 bbp_val |= 0x1;
7825 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7826 usleep_range(100, 200);
7827
7828 if (set_bw) {
7829 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
7830 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7831 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7832 usleep_range(100, 200);
7833 }
7834
7835 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7836 bbp_val &= (~0x1);
7837 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7838 usleep_range(100, 200);
7839 }
7840
7841 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7842 {
7843 u8 rf_val;
7844
7845 if (btxcal)
7846 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7847 else
7848 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7849
7850 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7851
7852 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7853 rf_val |= 0x80;
7854 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7855
7856 if (btxcal) {
7857 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7858 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7859 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7860 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7861 rf_val &= (~0x3F);
7862 rf_val |= 0x3F;
7863 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7864 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7865 rf_val &= (~0x3F);
7866 rf_val |= 0x3F;
7867 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7868 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7869 } else {
7870 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7871 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7872 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7873 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7874 rf_val &= (~0x3F);
7875 rf_val |= 0x34;
7876 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7877 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7878 rf_val &= (~0x3F);
7879 rf_val |= 0x34;
7880 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7881 }
7882
7883 return 0;
7884 }
7885
7886 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7887 {
7888 unsigned int cnt;
7889 u8 bbp_val;
7890 char cal_val;
7891
7892 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7893
7894 cnt = 0;
7895 do {
7896 usleep_range(500, 2000);
7897 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
7898 if (bbp_val == 0x02 || cnt == 20)
7899 break;
7900
7901 cnt++;
7902 } while (cnt < 20);
7903
7904 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
7905 cal_val = bbp_val & 0x7F;
7906 if (cal_val >= 0x40)
7907 cal_val -= 128;
7908
7909 return cal_val;
7910 }
7911
7912 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7913 bool btxcal)
7914 {
7915 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7916 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7917 u8 filter_target;
7918 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7919 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7920 int loop = 0, is_ht40, cnt;
7921 u8 bbp_val, rf_val;
7922 char cal_r32_init, cal_r32_val, cal_diff;
7923 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7924 u8 saverfb5r06, saverfb5r07;
7925 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7926 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7927 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7928 u8 saverfb5r58, saverfb5r59;
7929 u8 savebbp159r0, savebbp159r2, savebbpr23;
7930 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7931
7932 /* Save MAC registers */
7933 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
7934 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
7935
7936 /* save BBP registers */
7937 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
7938
7939 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
7940 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7941
7942 /* Save RF registers */
7943 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7944 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7945 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7946 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7947 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
7948 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7949 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7950 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7951 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7952 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
7953 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
7954 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
7955
7956 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
7957 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
7958 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
7959 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
7960 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
7961 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
7962 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
7963 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
7964 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
7965 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
7966
7967 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7968 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7969
7970 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7971 rf_val |= 0x3;
7972 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7973
7974 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7975 rf_val |= 0x1;
7976 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7977
7978 cnt = 0;
7979 do {
7980 usleep_range(500, 2000);
7981 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7982 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7983 break;
7984 cnt++;
7985 } while (cnt < 40);
7986
7987 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7988 rf_val &= (~0x3);
7989 rf_val |= 0x1;
7990 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7991
7992 /* I-3 */
7993 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
7994 bbp_val &= (~0x1F);
7995 bbp_val |= 0x10;
7996 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7997
7998 do {
7999 /* I-4,5,6,7,8,9 */
8000 if (loop == 0) {
8001 is_ht40 = false;
8002
8003 if (btxcal)
8004 filter_target = tx_filter_target_20m;
8005 else
8006 filter_target = rx_filter_target_20m;
8007 } else {
8008 is_ht40 = true;
8009
8010 if (btxcal)
8011 filter_target = tx_filter_target_40m;
8012 else
8013 filter_target = rx_filter_target_40m;
8014 }
8015
8016 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8017 rf_val &= (~0x04);
8018 if (loop == 1)
8019 rf_val |= 0x4;
8020
8021 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8022
8023 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8024
8025 rt2800_rf_lp_config(rt2x00dev, btxcal);
8026 if (btxcal) {
8027 tx_agc_fc = 0;
8028 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8029 rf_val &= (~0x7F);
8030 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8031 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8032 rf_val &= (~0x7F);
8033 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8034 } else {
8035 rx_agc_fc = 0;
8036 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8037 rf_val &= (~0x7F);
8038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8039 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8040 rf_val &= (~0x7F);
8041 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8042 }
8043
8044 usleep_range(1000, 2000);
8045
8046 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8047 bbp_val &= (~0x6);
8048 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8049
8050 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8051
8052 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8053
8054 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8055 bbp_val |= 0x6;
8056 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8057 do_cal:
8058 if (btxcal) {
8059 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8060 rf_val &= (~0x7F);
8061 rf_val |= tx_agc_fc;
8062 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8063 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8064 rf_val &= (~0x7F);
8065 rf_val |= tx_agc_fc;
8066 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8067 } else {
8068 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8069 rf_val &= (~0x7F);
8070 rf_val |= rx_agc_fc;
8071 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8072 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8073 rf_val &= (~0x7F);
8074 rf_val |= rx_agc_fc;
8075 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8076 }
8077
8078 usleep_range(500, 1000);
8079
8080 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8081
8082 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8083
8084 cal_diff = cal_r32_init - cal_r32_val;
8085
8086 if (btxcal)
8087 cmm_agc_fc = tx_agc_fc;
8088 else
8089 cmm_agc_fc = rx_agc_fc;
8090
8091 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8092 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8093 if (btxcal)
8094 tx_agc_fc = 0;
8095 else
8096 rx_agc_fc = 0;
8097 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8098 if (btxcal)
8099 tx_agc_fc++;
8100 else
8101 rx_agc_fc++;
8102 goto do_cal;
8103 }
8104
8105 if (btxcal) {
8106 if (loop == 0)
8107 drv_data->tx_calibration_bw20 = tx_agc_fc;
8108 else
8109 drv_data->tx_calibration_bw40 = tx_agc_fc;
8110 } else {
8111 if (loop == 0)
8112 drv_data->rx_calibration_bw20 = rx_agc_fc;
8113 else
8114 drv_data->rx_calibration_bw40 = rx_agc_fc;
8115 }
8116
8117 loop++;
8118 } while (loop <= 1);
8119
8120 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8121 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8122 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8123 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8124 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8125 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8126 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8127 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8128 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8129 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8130 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8131 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8132
8133 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8134 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8135 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8136 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8137 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8138 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8139 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8140 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8141 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8142 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8143
8144 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8145 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8146
8147 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8148
8149 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8150 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8151
8152 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8153 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8154 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8155 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8156
8157 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8158 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8159 }
8160
8161 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8162 {
8163 /* Initialize RF central register to default value */
8164 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8165 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8166 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8167 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8168 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8169 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8170 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8171 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8172 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8173 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8174 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8175 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8176 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8177 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8178 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8179 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8180 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8181 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8182 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8183 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8184 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8185 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8186 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8187 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8188 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8189 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8190 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8191 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8192 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8193 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8194 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8195 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8196 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8197 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8198 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8199 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8200 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8201 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8202 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8203 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8204 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8205 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8206 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8207 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8208
8209 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8210 if (rt2800_clk_is_20mhz(rt2x00dev))
8211 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8212 else
8213 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8214 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8215 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8216 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8217 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8218 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8219 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8220 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8221 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8222 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8223 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8224 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8225 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8226 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8227 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8228 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8229 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8230
8231 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8232 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8233 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8234
8235 /* Initialize RF channel register to default value */
8236 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8237 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8238 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8239 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8240 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8241 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8242 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8243 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8244 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8245 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8246 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8247 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8248 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8249 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8250 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8251 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8252 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8253 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8254 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8255 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8256 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8257 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8258 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8259 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8260 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8261 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8262 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8263 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8264 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8265 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8266 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8267 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8268 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8269 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8270 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8271 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8272 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8273 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8274 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8275 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8276 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8277 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8278 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8279 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8280 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8281 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8282 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8283 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8284 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8285 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8286 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8287 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8288 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8289 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8290 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8291 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8292 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8293 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8294 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8295 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8296
8297 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8298
8299 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8300 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8301 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8302 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8303 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8304 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8305 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8306 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8307 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8308 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8309 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8310 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8311 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8312 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8313 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8314 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8315 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8316 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8317 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8318 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8319 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8320 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8321 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8322 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8323 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8324 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8325 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8326 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8327 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8328 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8329
8330 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8331 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8332 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8333 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8334 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8335 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8336 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8337 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8338 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8339
8340 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8341 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8342 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8343 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8344 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8345 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8346
8347 /* Initialize RF channel register for DRQFN */
8348 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8349 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8350 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8351 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8352 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8353 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8354 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8355 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8356
8357 /* Initialize RF DC calibration register to default value */
8358 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8359 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8360 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8361 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8362 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8363 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8364 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8365 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8366 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8367 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8368 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8369 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8370 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8371 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8372 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8373 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8374 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8375 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8376 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8377 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8378 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8379 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8380 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8381 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8382 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8383 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8384 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8385 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8386 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8387 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8388 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8389 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8390 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8391 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8392 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8393 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8394 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8395 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8396 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8397 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8398 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8399 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8400 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8401 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8402 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8403 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8404 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8405 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8406 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8407 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8408 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8409 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8410 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8411 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8412 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8413 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8414 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8415 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8416 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8417
8418 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8419 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8420 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8421
8422 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8423 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8424
8425 rt2800_bw_filter_calibration(rt2x00dev, true);
8426 rt2800_bw_filter_calibration(rt2x00dev, false);
8427 }
8428
8429 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8430 {
8431 if (rt2800_is_305x_soc(rt2x00dev)) {
8432 rt2800_init_rfcsr_305x_soc(rt2x00dev);
8433 return;
8434 }
8435
8436 switch (rt2x00dev->chip.rt) {
8437 case RT3070:
8438 case RT3071:
8439 case RT3090:
8440 rt2800_init_rfcsr_30xx(rt2x00dev);
8441 break;
8442 case RT3290:
8443 rt2800_init_rfcsr_3290(rt2x00dev);
8444 break;
8445 case RT3352:
8446 rt2800_init_rfcsr_3352(rt2x00dev);
8447 break;
8448 case RT3390:
8449 rt2800_init_rfcsr_3390(rt2x00dev);
8450 break;
8451 case RT3572:
8452 rt2800_init_rfcsr_3572(rt2x00dev);
8453 break;
8454 case RT3593:
8455 rt2800_init_rfcsr_3593(rt2x00dev);
8456 break;
8457 case RT5350:
8458 rt2800_init_rfcsr_5350(rt2x00dev);
8459 break;
8460 case RT5390:
8461 rt2800_init_rfcsr_5390(rt2x00dev);
8462 break;
8463 case RT5392:
8464 rt2800_init_rfcsr_5392(rt2x00dev);
8465 break;
8466 case RT5592:
8467 rt2800_init_rfcsr_5592(rt2x00dev);
8468 break;
8469 case RT6352:
8470 rt2800_init_rfcsr_6352(rt2x00dev);
8471 break;
8472 }
8473 }
8474
8475 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8476 {
8477 u32 reg;
8478 u16 word;
8479
8480 /*
8481 * Initialize MAC registers.
8482 */
8483 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
8484 rt2800_init_registers(rt2x00dev)))
8485 return -EIO;
8486
8487 /*
8488 * Wait BBP/RF to wake up.
8489 */
8490 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8491 return -EIO;
8492
8493 /*
8494 * Send signal during boot time to initialize firmware.
8495 */
8496 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8497 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8498 if (rt2x00_is_usb(rt2x00dev))
8499 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8500 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
8501 msleep(1);
8502
8503 /*
8504 * Make sure BBP is up and running.
8505 */
8506 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
8507 return -EIO;
8508
8509 /*
8510 * Initialize BBP/RF registers.
8511 */
8512 rt2800_init_bbp(rt2x00dev);
8513 rt2800_init_rfcsr(rt2x00dev);
8514
8515 if (rt2x00_is_usb(rt2x00dev) &&
8516 (rt2x00_rt(rt2x00dev, RT3070) ||
8517 rt2x00_rt(rt2x00dev, RT3071) ||
8518 rt2x00_rt(rt2x00dev, RT3572))) {
8519 udelay(200);
8520 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8521 udelay(10);
8522 }
8523
8524 /*
8525 * Enable RX.
8526 */
8527 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8528 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8529 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8530 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8531
8532 udelay(50);
8533
8534 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
8535 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8536 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
8537 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8538 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8539
8540 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8541 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8542 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
8543 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8544
8545 /*
8546 * Initialize LED control
8547 */
8548 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
8549 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
8550 word & 0xff, (word >> 8) & 0xff);
8551
8552 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
8553 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
8554 word & 0xff, (word >> 8) & 0xff);
8555
8556 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
8557 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
8558 word & 0xff, (word >> 8) & 0xff);
8559
8560 return 0;
8561 }
8562 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8563
8564 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8565 {
8566 u32 reg;
8567
8568 rt2800_disable_wpdma(rt2x00dev);
8569
8570 /* Wait for DMA, ignore error */
8571 rt2800_wait_wpdma_ready(rt2x00dev);
8572
8573 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8574 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
8575 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8576 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8577 }
8578 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
8579
8580 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8581 {
8582 u32 reg;
8583 u16 efuse_ctrl_reg;
8584
8585 if (rt2x00_rt(rt2x00dev, RT3290))
8586 efuse_ctrl_reg = EFUSE_CTRL_3290;
8587 else
8588 efuse_ctrl_reg = EFUSE_CTRL;
8589
8590 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
8591 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8592 }
8593 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8594
8595 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8596 {
8597 u32 reg;
8598 u16 efuse_ctrl_reg;
8599 u16 efuse_data0_reg;
8600 u16 efuse_data1_reg;
8601 u16 efuse_data2_reg;
8602 u16 efuse_data3_reg;
8603
8604 if (rt2x00_rt(rt2x00dev, RT3290)) {
8605 efuse_ctrl_reg = EFUSE_CTRL_3290;
8606 efuse_data0_reg = EFUSE_DATA0_3290;
8607 efuse_data1_reg = EFUSE_DATA1_3290;
8608 efuse_data2_reg = EFUSE_DATA2_3290;
8609 efuse_data3_reg = EFUSE_DATA3_3290;
8610 } else {
8611 efuse_ctrl_reg = EFUSE_CTRL;
8612 efuse_data0_reg = EFUSE_DATA0;
8613 efuse_data1_reg = EFUSE_DATA1;
8614 efuse_data2_reg = EFUSE_DATA2;
8615 efuse_data3_reg = EFUSE_DATA3;
8616 }
8617 mutex_lock(&rt2x00dev->csr_mutex);
8618
8619 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
8620 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
8621 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
8622 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
8623 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
8624
8625 /* Wait until the EEPROM has been loaded */
8626 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
8627 /* Apparently the data is read from end to start */
8628 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
8629 /* The returned value is in CPU order, but eeprom is le */
8630 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
8631 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
8632 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
8633 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
8634 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
8635 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
8636 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
8637
8638 mutex_unlock(&rt2x00dev->csr_mutex);
8639 }
8640
8641 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
8642 {
8643 unsigned int i;
8644
8645 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8646 rt2800_efuse_read(rt2x00dev, i);
8647
8648 return 0;
8649 }
8650 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8651
8652 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8653 {
8654 u16 word;
8655
8656 if (rt2x00_rt(rt2x00dev, RT3593))
8657 return 0;
8658
8659 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
8660 if ((word & 0x00ff) != 0x00ff)
8661 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8662
8663 return 0;
8664 }
8665
8666 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8667 {
8668 u16 word;
8669
8670 if (rt2x00_rt(rt2x00dev, RT3593))
8671 return 0;
8672
8673 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
8674 if ((word & 0x00ff) != 0x00ff)
8675 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8676
8677 return 0;
8678 }
8679
8680 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
8681 {
8682 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8683 u16 word;
8684 u8 *mac;
8685 u8 default_lna_gain;
8686 int retval;
8687
8688 /*
8689 * Read the EEPROM.
8690 */
8691 retval = rt2800_read_eeprom(rt2x00dev);
8692 if (retval)
8693 return retval;
8694
8695 /*
8696 * Start validation of the data that has been read.
8697 */
8698 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
8699 rt2x00lib_set_mac_address(rt2x00dev, mac);
8700
8701 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8702 if (word == 0xffff) {
8703 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8704 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8705 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
8706 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8707 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
8708 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
8709 rt2x00_rt(rt2x00dev, RT2872)) {
8710 /*
8711 * There is a max of 2 RX streams for RT28x0 series
8712 */
8713 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8714 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8715 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8716 }
8717
8718 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8719 if (word == 0xffff) {
8720 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8721 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8722 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8723 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8724 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8725 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8726 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8727 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8730 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8731 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8732 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8733 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8734 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
8735 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
8736 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
8737 }
8738
8739 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8740 if ((word & 0x00ff) == 0x00ff) {
8741 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
8742 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8743 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
8744 }
8745 if ((word & 0xff00) == 0xff00) {
8746 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8747 LED_MODE_TXRX_ACTIVITY);
8748 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
8749 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8750 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8751 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8752 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
8753 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
8754 }
8755
8756 /*
8757 * During the LNA validation we are going to use
8758 * lna0 as correct value. Note that EEPROM_LNA
8759 * is never validated.
8760 */
8761 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
8762 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8763
8764 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
8765 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8766 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8767 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8768 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
8769 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
8770
8771 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
8772
8773 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
8774 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8775 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
8776 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8777 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8778 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8779 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8780 default_lna_gain);
8781 }
8782 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
8783
8784 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
8785
8786 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
8787 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8788 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8789 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8790 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
8791 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
8792
8793 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
8794 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8795 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
8796 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8797 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8798 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8799 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8800 default_lna_gain);
8801 }
8802 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
8803
8804 if (rt2x00_rt(rt2x00dev, RT3593)) {
8805 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
8806 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8807 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8808 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8809 default_lna_gain);
8810 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8811 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8812 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8813 default_lna_gain);
8814 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8815 }
8816
8817 return 0;
8818 }
8819
8820 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
8821 {
8822 u16 value;
8823 u16 eeprom;
8824 u16 rf;
8825
8826 /*
8827 * Read EEPROM word for configuration.
8828 */
8829 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8830
8831 /*
8832 * Identify RF chipset by EEPROM value
8833 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8834 * RT53xx: defined in "EEPROM_CHIP_ID" field
8835 */
8836 if (rt2x00_rt(rt2x00dev, RT3290) ||
8837 rt2x00_rt(rt2x00dev, RT5390) ||
8838 rt2x00_rt(rt2x00dev, RT5392) ||
8839 rt2x00_rt(rt2x00dev, RT6352))
8840 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
8841 else if (rt2x00_rt(rt2x00dev, RT3352))
8842 rf = RF3322;
8843 else if (rt2x00_rt(rt2x00dev, RT5350))
8844 rf = RF5350;
8845 else
8846 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8847
8848 switch (rf) {
8849 case RF2820:
8850 case RF2850:
8851 case RF2720:
8852 case RF2750:
8853 case RF3020:
8854 case RF2020:
8855 case RF3021:
8856 case RF3022:
8857 case RF3052:
8858 case RF3053:
8859 case RF3070:
8860 case RF3290:
8861 case RF3320:
8862 case RF3322:
8863 case RF5350:
8864 case RF5360:
8865 case RF5362:
8866 case RF5370:
8867 case RF5372:
8868 case RF5390:
8869 case RF5392:
8870 case RF5592:
8871 case RF7620:
8872 break;
8873 default:
8874 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8875 rf);
8876 return -ENODEV;
8877 }
8878
8879 rt2x00_set_rf(rt2x00dev, rf);
8880
8881 /*
8882 * Identify default antenna configuration.
8883 */
8884 rt2x00dev->default_ant.tx_chain_num =
8885 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
8886 rt2x00dev->default_ant.rx_chain_num =
8887 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
8888
8889 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8890
8891 if (rt2x00_rt(rt2x00dev, RT3070) ||
8892 rt2x00_rt(rt2x00dev, RT3090) ||
8893 rt2x00_rt(rt2x00dev, RT3352) ||
8894 rt2x00_rt(rt2x00dev, RT3390)) {
8895 value = rt2x00_get_field16(eeprom,
8896 EEPROM_NIC_CONF1_ANT_DIVERSITY);
8897 switch (value) {
8898 case 0:
8899 case 1:
8900 case 2:
8901 rt2x00dev->default_ant.tx = ANTENNA_A;
8902 rt2x00dev->default_ant.rx = ANTENNA_A;
8903 break;
8904 case 3:
8905 rt2x00dev->default_ant.tx = ANTENNA_A;
8906 rt2x00dev->default_ant.rx = ANTENNA_B;
8907 break;
8908 }
8909 } else {
8910 rt2x00dev->default_ant.tx = ANTENNA_A;
8911 rt2x00dev->default_ant.rx = ANTENNA_A;
8912 }
8913
8914 /* These chips have hardware RX antenna diversity */
8915 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
8916 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
8917 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8918 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8919 }
8920
8921 /*
8922 * Determine external LNA informations.
8923 */
8924 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
8925 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
8926 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
8927 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
8928
8929 /*
8930 * Detect if this device has an hardware controlled radio.
8931 */
8932 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
8933 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
8934
8935 /*
8936 * Detect if this device has Bluetooth co-existence.
8937 */
8938 if (!rt2x00_rt(rt2x00dev, RT3352) &&
8939 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
8940 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8941
8942 /*
8943 * Read frequency offset and RF programming sequence.
8944 */
8945 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8946 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8947
8948 /*
8949 * Store led settings, for correct led behaviour.
8950 */
8951 #ifdef CONFIG_RT2X00_LIB_LEDS
8952 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8953 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8954 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8955
8956 rt2x00dev->led_mcu_reg = eeprom;
8957 #endif /* CONFIG_RT2X00_LIB_LEDS */
8958
8959 /*
8960 * Check if support EIRP tx power limit feature.
8961 */
8962 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
8963
8964 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8965 EIRP_MAX_TX_POWER_LIMIT)
8966 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
8967
8968 /*
8969 * Detect if device uses internal or external PA
8970 */
8971 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8972
8973 if (rt2x00_rt(rt2x00dev, RT3352)) {
8974 if (rt2x00_get_field16(eeprom,
8975 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
8976 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
8977 &rt2x00dev->cap_flags);
8978 if (rt2x00_get_field16(eeprom,
8979 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
8980 __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
8981 &rt2x00dev->cap_flags);
8982 }
8983
8984 return 0;
8985 }
8986
8987 /*
8988 * RF value list for rt28xx
8989 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8990 */
8991 static const struct rf_channel rf_vals[] = {
8992 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8993 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8994 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8995 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8996 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8997 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8998 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8999 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9000 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9001 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9002 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9003 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9004 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9005 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9006
9007 /* 802.11 UNI / HyperLan 2 */
9008 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9009 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9010 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9011 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9012 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9013 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9014 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9015 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9016 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9017 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9018 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9019 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9020
9021 /* 802.11 HyperLan 2 */
9022 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9023 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9024 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9025 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9026 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9027 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9028 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9029 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9030 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9031 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9032 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9033 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9034 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9035 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9036 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9037 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9038
9039 /* 802.11 UNII */
9040 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9041 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9042 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9043 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9044 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9045 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9046 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9047 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9048 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9049 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9050 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9051
9052 /* 802.11 Japan */
9053 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9054 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9055 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9056 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9057 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9058 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9059 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9060 };
9061
9062 /*
9063 * RF value list for rt3xxx
9064 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9065 */
9066 static const struct rf_channel rf_vals_3x[] = {
9067 {1, 241, 2, 2 },
9068 {2, 241, 2, 7 },
9069 {3, 242, 2, 2 },
9070 {4, 242, 2, 7 },
9071 {5, 243, 2, 2 },
9072 {6, 243, 2, 7 },
9073 {7, 244, 2, 2 },
9074 {8, 244, 2, 7 },
9075 {9, 245, 2, 2 },
9076 {10, 245, 2, 7 },
9077 {11, 246, 2, 2 },
9078 {12, 246, 2, 7 },
9079 {13, 247, 2, 2 },
9080 {14, 248, 2, 4 },
9081
9082 /* 802.11 UNI / HyperLan 2 */
9083 {36, 0x56, 0, 4},
9084 {38, 0x56, 0, 6},
9085 {40, 0x56, 0, 8},
9086 {44, 0x57, 0, 0},
9087 {46, 0x57, 0, 2},
9088 {48, 0x57, 0, 4},
9089 {52, 0x57, 0, 8},
9090 {54, 0x57, 0, 10},
9091 {56, 0x58, 0, 0},
9092 {60, 0x58, 0, 4},
9093 {62, 0x58, 0, 6},
9094 {64, 0x58, 0, 8},
9095
9096 /* 802.11 HyperLan 2 */
9097 {100, 0x5b, 0, 8},
9098 {102, 0x5b, 0, 10},
9099 {104, 0x5c, 0, 0},
9100 {108, 0x5c, 0, 4},
9101 {110, 0x5c, 0, 6},
9102 {112, 0x5c, 0, 8},
9103 {116, 0x5d, 0, 0},
9104 {118, 0x5d, 0, 2},
9105 {120, 0x5d, 0, 4},
9106 {124, 0x5d, 0, 8},
9107 {126, 0x5d, 0, 10},
9108 {128, 0x5e, 0, 0},
9109 {132, 0x5e, 0, 4},
9110 {134, 0x5e, 0, 6},
9111 {136, 0x5e, 0, 8},
9112 {140, 0x5f, 0, 0},
9113
9114 /* 802.11 UNII */
9115 {149, 0x5f, 0, 9},
9116 {151, 0x5f, 0, 11},
9117 {153, 0x60, 0, 1},
9118 {157, 0x60, 0, 5},
9119 {159, 0x60, 0, 7},
9120 {161, 0x60, 0, 9},
9121 {165, 0x61, 0, 1},
9122 {167, 0x61, 0, 3},
9123 {169, 0x61, 0, 5},
9124 {171, 0x61, 0, 7},
9125 {173, 0x61, 0, 9},
9126 };
9127
9128 /*
9129 * RF value list for rt3xxx with Xtal20MHz
9130 * Supports: 2.4 GHz (all) (RF3322)
9131 */
9132 static const struct rf_channel rf_vals_3x_xtal20[] = {
9133 {1, 0xE2, 2, 0x14},
9134 {2, 0xE3, 2, 0x14},
9135 {3, 0xE4, 2, 0x14},
9136 {4, 0xE5, 2, 0x14},
9137 {5, 0xE6, 2, 0x14},
9138 {6, 0xE7, 2, 0x14},
9139 {7, 0xE8, 2, 0x14},
9140 {8, 0xE9, 2, 0x14},
9141 {9, 0xEA, 2, 0x14},
9142 {10, 0xEB, 2, 0x14},
9143 {11, 0xEC, 2, 0x14},
9144 {12, 0xED, 2, 0x14},
9145 {13, 0xEE, 2, 0x14},
9146 {14, 0xF0, 2, 0x18},
9147 };
9148
9149 static const struct rf_channel rf_vals_5592_xtal20[] = {
9150 /* Channel, N, K, mod, R */
9151 {1, 482, 4, 10, 3},
9152 {2, 483, 4, 10, 3},
9153 {3, 484, 4, 10, 3},
9154 {4, 485, 4, 10, 3},
9155 {5, 486, 4, 10, 3},
9156 {6, 487, 4, 10, 3},
9157 {7, 488, 4, 10, 3},
9158 {8, 489, 4, 10, 3},
9159 {9, 490, 4, 10, 3},
9160 {10, 491, 4, 10, 3},
9161 {11, 492, 4, 10, 3},
9162 {12, 493, 4, 10, 3},
9163 {13, 494, 4, 10, 3},
9164 {14, 496, 8, 10, 3},
9165 {36, 172, 8, 12, 1},
9166 {38, 173, 0, 12, 1},
9167 {40, 173, 4, 12, 1},
9168 {42, 173, 8, 12, 1},
9169 {44, 174, 0, 12, 1},
9170 {46, 174, 4, 12, 1},
9171 {48, 174, 8, 12, 1},
9172 {50, 175, 0, 12, 1},
9173 {52, 175, 4, 12, 1},
9174 {54, 175, 8, 12, 1},
9175 {56, 176, 0, 12, 1},
9176 {58, 176, 4, 12, 1},
9177 {60, 176, 8, 12, 1},
9178 {62, 177, 0, 12, 1},
9179 {64, 177, 4, 12, 1},
9180 {100, 183, 4, 12, 1},
9181 {102, 183, 8, 12, 1},
9182 {104, 184, 0, 12, 1},
9183 {106, 184, 4, 12, 1},
9184 {108, 184, 8, 12, 1},
9185 {110, 185, 0, 12, 1},
9186 {112, 185, 4, 12, 1},
9187 {114, 185, 8, 12, 1},
9188 {116, 186, 0, 12, 1},
9189 {118, 186, 4, 12, 1},
9190 {120, 186, 8, 12, 1},
9191 {122, 187, 0, 12, 1},
9192 {124, 187, 4, 12, 1},
9193 {126, 187, 8, 12, 1},
9194 {128, 188, 0, 12, 1},
9195 {130, 188, 4, 12, 1},
9196 {132, 188, 8, 12, 1},
9197 {134, 189, 0, 12, 1},
9198 {136, 189, 4, 12, 1},
9199 {138, 189, 8, 12, 1},
9200 {140, 190, 0, 12, 1},
9201 {149, 191, 6, 12, 1},
9202 {151, 191, 10, 12, 1},
9203 {153, 192, 2, 12, 1},
9204 {155, 192, 6, 12, 1},
9205 {157, 192, 10, 12, 1},
9206 {159, 193, 2, 12, 1},
9207 {161, 193, 6, 12, 1},
9208 {165, 194, 2, 12, 1},
9209 {184, 164, 0, 12, 1},
9210 {188, 164, 4, 12, 1},
9211 {192, 165, 8, 12, 1},
9212 {196, 166, 0, 12, 1},
9213 };
9214
9215 static const struct rf_channel rf_vals_5592_xtal40[] = {
9216 /* Channel, N, K, mod, R */
9217 {1, 241, 2, 10, 3},
9218 {2, 241, 7, 10, 3},
9219 {3, 242, 2, 10, 3},
9220 {4, 242, 7, 10, 3},
9221 {5, 243, 2, 10, 3},
9222 {6, 243, 7, 10, 3},
9223 {7, 244, 2, 10, 3},
9224 {8, 244, 7, 10, 3},
9225 {9, 245, 2, 10, 3},
9226 {10, 245, 7, 10, 3},
9227 {11, 246, 2, 10, 3},
9228 {12, 246, 7, 10, 3},
9229 {13, 247, 2, 10, 3},
9230 {14, 248, 4, 10, 3},
9231 {36, 86, 4, 12, 1},
9232 {38, 86, 6, 12, 1},
9233 {40, 86, 8, 12, 1},
9234 {42, 86, 10, 12, 1},
9235 {44, 87, 0, 12, 1},
9236 {46, 87, 2, 12, 1},
9237 {48, 87, 4, 12, 1},
9238 {50, 87, 6, 12, 1},
9239 {52, 87, 8, 12, 1},
9240 {54, 87, 10, 12, 1},
9241 {56, 88, 0, 12, 1},
9242 {58, 88, 2, 12, 1},
9243 {60, 88, 4, 12, 1},
9244 {62, 88, 6, 12, 1},
9245 {64, 88, 8, 12, 1},
9246 {100, 91, 8, 12, 1},
9247 {102, 91, 10, 12, 1},
9248 {104, 92, 0, 12, 1},
9249 {106, 92, 2, 12, 1},
9250 {108, 92, 4, 12, 1},
9251 {110, 92, 6, 12, 1},
9252 {112, 92, 8, 12, 1},
9253 {114, 92, 10, 12, 1},
9254 {116, 93, 0, 12, 1},
9255 {118, 93, 2, 12, 1},
9256 {120, 93, 4, 12, 1},
9257 {122, 93, 6, 12, 1},
9258 {124, 93, 8, 12, 1},
9259 {126, 93, 10, 12, 1},
9260 {128, 94, 0, 12, 1},
9261 {130, 94, 2, 12, 1},
9262 {132, 94, 4, 12, 1},
9263 {134, 94, 6, 12, 1},
9264 {136, 94, 8, 12, 1},
9265 {138, 94, 10, 12, 1},
9266 {140, 95, 0, 12, 1},
9267 {149, 95, 9, 12, 1},
9268 {151, 95, 11, 12, 1},
9269 {153, 96, 1, 12, 1},
9270 {155, 96, 3, 12, 1},
9271 {157, 96, 5, 12, 1},
9272 {159, 96, 7, 12, 1},
9273 {161, 96, 9, 12, 1},
9274 {165, 97, 1, 12, 1},
9275 {184, 82, 0, 12, 1},
9276 {188, 82, 4, 12, 1},
9277 {192, 82, 8, 12, 1},
9278 {196, 83, 0, 12, 1},
9279 };
9280
9281 static const struct rf_channel rf_vals_7620[] = {
9282 {1, 0x50, 0x99, 0x99, 1},
9283 {2, 0x50, 0x44, 0x44, 2},
9284 {3, 0x50, 0xEE, 0xEE, 2},
9285 {4, 0x50, 0x99, 0x99, 3},
9286 {5, 0x51, 0x44, 0x44, 0},
9287 {6, 0x51, 0xEE, 0xEE, 0},
9288 {7, 0x51, 0x99, 0x99, 1},
9289 {8, 0x51, 0x44, 0x44, 2},
9290 {9, 0x51, 0xEE, 0xEE, 2},
9291 {10, 0x51, 0x99, 0x99, 3},
9292 {11, 0x52, 0x44, 0x44, 0},
9293 {12, 0x52, 0xEE, 0xEE, 0},
9294 {13, 0x52, 0x99, 0x99, 1},
9295 {14, 0x52, 0x33, 0x33, 3},
9296 };
9297
9298 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9299 {
9300 struct hw_mode_spec *spec = &rt2x00dev->spec;
9301 struct channel_info *info;
9302 char *default_power1;
9303 char *default_power2;
9304 char *default_power3;
9305 unsigned int i, tx_chains, rx_chains;
9306 u32 reg;
9307
9308 /*
9309 * Disable powersaving as default.
9310 */
9311 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9312
9313 /*
9314 * Change default retry settings to values corresponding more closely
9315 * to rate[0].count setting of minstrel rate control algorithm.
9316 */
9317 rt2x00dev->hw->wiphy->retry_short = 2;
9318 rt2x00dev->hw->wiphy->retry_long = 2;
9319
9320 /*
9321 * Initialize all hw fields.
9322 */
9323 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9324 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9325 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9326 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9327 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9328
9329 /*
9330 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9331 * unless we are capable of sending the buffered frames out after the
9332 * DTIM transmission using rt2x00lib_beacondone. This will send out
9333 * multicast and broadcast traffic immediately instead of buffering it
9334 * infinitly and thus dropping it after some time.
9335 */
9336 if (!rt2x00_is_usb(rt2x00dev))
9337 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9338
9339 /* Set MFP if HW crypto is disabled. */
9340 if (rt2800_hwcrypt_disabled(rt2x00dev))
9341 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9342
9343 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9344 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9345 rt2800_eeprom_addr(rt2x00dev,
9346 EEPROM_MAC_ADDR_0));
9347
9348 /*
9349 * As rt2800 has a global fallback table we cannot specify
9350 * more then one tx rate per frame but since the hw will
9351 * try several rates (based on the fallback table) we should
9352 * initialize max_report_rates to the maximum number of rates
9353 * we are going to try. Otherwise mac80211 will truncate our
9354 * reported tx rates and the rc algortihm will end up with
9355 * incorrect data.
9356 */
9357 rt2x00dev->hw->max_rates = 1;
9358 rt2x00dev->hw->max_report_rates = 7;
9359 rt2x00dev->hw->max_rate_tries = 1;
9360
9361 /*
9362 * Initialize hw_mode information.
9363 */
9364 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9365
9366 switch (rt2x00dev->chip.rf) {
9367 case RF2720:
9368 case RF2820:
9369 spec->num_channels = 14;
9370 spec->channels = rf_vals;
9371 break;
9372
9373 case RF2750:
9374 case RF2850:
9375 spec->num_channels = ARRAY_SIZE(rf_vals);
9376 spec->channels = rf_vals;
9377 break;
9378
9379 case RF2020:
9380 case RF3020:
9381 case RF3021:
9382 case RF3022:
9383 case RF3070:
9384 case RF3290:
9385 case RF3320:
9386 case RF3322:
9387 case RF5350:
9388 case RF5360:
9389 case RF5362:
9390 case RF5370:
9391 case RF5372:
9392 case RF5390:
9393 case RF5392:
9394 spec->num_channels = 14;
9395 if (rt2800_clk_is_20mhz(rt2x00dev))
9396 spec->channels = rf_vals_3x_xtal20;
9397 else
9398 spec->channels = rf_vals_3x;
9399 break;
9400
9401 case RF7620:
9402 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9403 spec->channels = rf_vals_7620;
9404 break;
9405
9406 case RF3052:
9407 case RF3053:
9408 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9409 spec->channels = rf_vals_3x;
9410 break;
9411
9412 case RF5592:
9413 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
9414 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9415 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9416 spec->channels = rf_vals_5592_xtal40;
9417 } else {
9418 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9419 spec->channels = rf_vals_5592_xtal20;
9420 }
9421 break;
9422 }
9423
9424 if (WARN_ON_ONCE(!spec->channels))
9425 return -ENODEV;
9426
9427 spec->supported_bands = SUPPORT_BAND_2GHZ;
9428 if (spec->num_channels > 14)
9429 spec->supported_bands |= SUPPORT_BAND_5GHZ;
9430
9431 /*
9432 * Initialize HT information.
9433 */
9434 if (!rt2x00_rf(rt2x00dev, RF2020))
9435 spec->ht.ht_supported = true;
9436 else
9437 spec->ht.ht_supported = false;
9438
9439 spec->ht.cap =
9440 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
9441 IEEE80211_HT_CAP_GRN_FLD |
9442 IEEE80211_HT_CAP_SGI_20 |
9443 IEEE80211_HT_CAP_SGI_40;
9444
9445 tx_chains = rt2x00dev->default_ant.tx_chain_num;
9446 rx_chains = rt2x00dev->default_ant.rx_chain_num;
9447
9448 if (tx_chains >= 2)
9449 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9450
9451 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
9452
9453 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
9454 spec->ht.ampdu_density = 4;
9455 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9456 if (tx_chains != rx_chains) {
9457 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9458 spec->ht.mcs.tx_params |=
9459 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9460 }
9461
9462 switch (rx_chains) {
9463 case 3:
9464 spec->ht.mcs.rx_mask[2] = 0xff;
9465 /* fall through */
9466 case 2:
9467 spec->ht.mcs.rx_mask[1] = 0xff;
9468 /* fall through */
9469 case 1:
9470 spec->ht.mcs.rx_mask[0] = 0xff;
9471 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9472 break;
9473 }
9474
9475 /*
9476 * Create channel information array
9477 */
9478 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
9479 if (!info)
9480 return -ENOMEM;
9481
9482 spec->channels_info = info;
9483
9484 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9485 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
9486
9487 if (rt2x00dev->default_ant.tx_chain_num > 2)
9488 default_power3 = rt2800_eeprom_addr(rt2x00dev,
9489 EEPROM_EXT_TXPOWER_BG3);
9490 else
9491 default_power3 = NULL;
9492
9493 for (i = 0; i < 14; i++) {
9494 info[i].default_power1 = default_power1[i];
9495 info[i].default_power2 = default_power2[i];
9496 if (default_power3)
9497 info[i].default_power3 = default_power3[i];
9498 }
9499
9500 if (spec->num_channels > 14) {
9501 default_power1 = rt2800_eeprom_addr(rt2x00dev,
9502 EEPROM_TXPOWER_A1);
9503 default_power2 = rt2800_eeprom_addr(rt2x00dev,
9504 EEPROM_TXPOWER_A2);
9505
9506 if (rt2x00dev->default_ant.tx_chain_num > 2)
9507 default_power3 =
9508 rt2800_eeprom_addr(rt2x00dev,
9509 EEPROM_EXT_TXPOWER_A3);
9510 else
9511 default_power3 = NULL;
9512
9513 for (i = 14; i < spec->num_channels; i++) {
9514 info[i].default_power1 = default_power1[i - 14];
9515 info[i].default_power2 = default_power2[i - 14];
9516 if (default_power3)
9517 info[i].default_power3 = default_power3[i - 14];
9518 }
9519 }
9520
9521 switch (rt2x00dev->chip.rf) {
9522 case RF2020:
9523 case RF3020:
9524 case RF3021:
9525 case RF3022:
9526 case RF3320:
9527 case RF3052:
9528 case RF3053:
9529 case RF3070:
9530 case RF3290:
9531 case RF5350:
9532 case RF5360:
9533 case RF5362:
9534 case RF5370:
9535 case RF5372:
9536 case RF5390:
9537 case RF5392:
9538 case RF5592:
9539 case RF7620:
9540 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9541 break;
9542 }
9543
9544 return 0;
9545 }
9546
9547 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9548 {
9549 u32 reg;
9550 u32 rt;
9551 u32 rev;
9552
9553 if (rt2x00_rt(rt2x00dev, RT3290))
9554 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
9555 else
9556 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
9557
9558 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9559 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9560
9561 switch (rt) {
9562 case RT2860:
9563 case RT2872:
9564 case RT2883:
9565 case RT3070:
9566 case RT3071:
9567 case RT3090:
9568 case RT3290:
9569 case RT3352:
9570 case RT3390:
9571 case RT3572:
9572 case RT3593:
9573 case RT5350:
9574 case RT5390:
9575 case RT5392:
9576 case RT5592:
9577 break;
9578 default:
9579 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9580 rt, rev);
9581 return -ENODEV;
9582 }
9583
9584 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9585 rt = RT6352;
9586
9587 rt2x00_set_rt(rt2x00dev, rt, rev);
9588
9589 return 0;
9590 }
9591
9592 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9593 {
9594 int retval;
9595 u32 reg;
9596
9597 retval = rt2800_probe_rt(rt2x00dev);
9598 if (retval)
9599 return retval;
9600
9601 /*
9602 * Allocate eeprom data.
9603 */
9604 retval = rt2800_validate_eeprom(rt2x00dev);
9605 if (retval)
9606 return retval;
9607
9608 retval = rt2800_init_eeprom(rt2x00dev);
9609 if (retval)
9610 return retval;
9611
9612 /*
9613 * Enable rfkill polling by setting GPIO direction of the
9614 * rfkill switch GPIO pin correctly.
9615 */
9616 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
9617 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
9618 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9619
9620 /*
9621 * Initialize hw specifications.
9622 */
9623 retval = rt2800_probe_hw_mode(rt2x00dev);
9624 if (retval)
9625 return retval;
9626
9627 /*
9628 * Set device capabilities.
9629 */
9630 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9631 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9632 if (!rt2x00_is_usb(rt2x00dev))
9633 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9634
9635 /*
9636 * Set device requirements.
9637 */
9638 if (!rt2x00_is_soc(rt2x00dev))
9639 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9640 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9641 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9642 if (!rt2800_hwcrypt_disabled(rt2x00dev))
9643 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9644 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9645 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9646 if (rt2x00_is_usb(rt2x00dev))
9647 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9648 else {
9649 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9650 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9651 }
9652
9653 /*
9654 * Set the rssi offset.
9655 */
9656 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9657
9658 return 0;
9659 }
9660 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
9661
9662 /*
9663 * IEEE80211 stack callback functions.
9664 */
9665 void rt2800_get_key_seq(struct ieee80211_hw *hw,
9666 struct ieee80211_key_conf *key,
9667 struct ieee80211_key_seq *seq)
9668 {
9669 struct rt2x00_dev *rt2x00dev = hw->priv;
9670 struct mac_iveiv_entry iveiv_entry;
9671 u32 offset;
9672
9673 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9674 return;
9675
9676 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
9677 rt2800_register_multiread(rt2x00dev, offset,
9678 &iveiv_entry, sizeof(iveiv_entry));
9679
9680 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9681 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
9682 }
9683 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
9684
9685 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
9686 {
9687 struct rt2x00_dev *rt2x00dev = hw->priv;
9688 u32 reg;
9689 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9690
9691 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
9692 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9693 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9694
9695 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
9696 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9697 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9698
9699 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
9700 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9701 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9702
9703 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
9704 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9705 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9706
9707 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
9708 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9709 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9710
9711 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
9712 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9713 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9714
9715 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
9716 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9717 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9718
9719 return 0;
9720 }
9721 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
9722
9723 int rt2800_conf_tx(struct ieee80211_hw *hw,
9724 struct ieee80211_vif *vif, u16 queue_idx,
9725 const struct ieee80211_tx_queue_params *params)
9726 {
9727 struct rt2x00_dev *rt2x00dev = hw->priv;
9728 struct data_queue *queue;
9729 struct rt2x00_field32 field;
9730 int retval;
9731 u32 reg;
9732 u32 offset;
9733
9734 /*
9735 * First pass the configuration through rt2x00lib, that will
9736 * update the queue settings and validate the input. After that
9737 * we are free to update the registers based on the value
9738 * in the queue parameter.
9739 */
9740 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
9741 if (retval)
9742 return retval;
9743
9744 /*
9745 * We only need to perform additional register initialization
9746 * for WMM queues/
9747 */
9748 if (queue_idx >= 4)
9749 return 0;
9750
9751 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
9752
9753 /* Update WMM TXOP register */
9754 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9755 field.bit_offset = (queue_idx & 1) * 16;
9756 field.bit_mask = 0xffff << field.bit_offset;
9757
9758 reg = rt2800_register_read(rt2x00dev, offset);
9759 rt2x00_set_field32(&reg, field, queue->txop);
9760 rt2800_register_write(rt2x00dev, offset, reg);
9761
9762 /* Update WMM registers */
9763 field.bit_offset = queue_idx * 4;
9764 field.bit_mask = 0xf << field.bit_offset;
9765
9766 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
9767 rt2x00_set_field32(&reg, field, queue->aifs);
9768 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9769
9770 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
9771 rt2x00_set_field32(&reg, field, queue->cw_min);
9772 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9773
9774 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
9775 rt2x00_set_field32(&reg, field, queue->cw_max);
9776 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9777
9778 /* Update EDCA registers */
9779 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9780
9781 reg = rt2800_register_read(rt2x00dev, offset);
9782 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
9783 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
9784 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9785 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9786 rt2800_register_write(rt2x00dev, offset, reg);
9787
9788 return 0;
9789 }
9790 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
9791
9792 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
9793 {
9794 struct rt2x00_dev *rt2x00dev = hw->priv;
9795 u64 tsf;
9796 u32 reg;
9797
9798 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
9799 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9800 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
9801 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9802
9803 return tsf;
9804 }
9805 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
9806
9807 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
9808 struct ieee80211_ampdu_params *params)
9809 {
9810 struct ieee80211_sta *sta = params->sta;
9811 enum ieee80211_ampdu_mlme_action action = params->action;
9812 u16 tid = params->tid;
9813 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
9814 int ret = 0;
9815
9816 /*
9817 * Don't allow aggregation for stations the hardware isn't aware
9818 * of because tx status reports for frames to an unknown station
9819 * always contain wcid=WCID_END+1 and thus we can't distinguish
9820 * between multiple stations which leads to unwanted situations
9821 * when the hw reorders frames due to aggregation.
9822 */
9823 if (sta_priv->wcid > WCID_END)
9824 return 1;
9825
9826 switch (action) {
9827 case IEEE80211_AMPDU_RX_START:
9828 case IEEE80211_AMPDU_RX_STOP:
9829 /*
9830 * The hw itself takes care of setting up BlockAck mechanisms.
9831 * So, we only have to allow mac80211 to nagotiate a BlockAck
9832 * agreement. Once that is done, the hw will BlockAck incoming
9833 * AMPDUs without further setup.
9834 */
9835 break;
9836 case IEEE80211_AMPDU_TX_START:
9837 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9838 break;
9839 case IEEE80211_AMPDU_TX_STOP_CONT:
9840 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9841 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9842 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9843 break;
9844 case IEEE80211_AMPDU_TX_OPERATIONAL:
9845 break;
9846 default:
9847 rt2x00_warn((struct rt2x00_dev *)hw->priv,
9848 "Unknown AMPDU action\n");
9849 }
9850
9851 return ret;
9852 }
9853 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
9854
9855 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9856 struct survey_info *survey)
9857 {
9858 struct rt2x00_dev *rt2x00dev = hw->priv;
9859 struct ieee80211_conf *conf = &hw->conf;
9860 u32 idle, busy, busy_ext;
9861
9862 if (idx != 0)
9863 return -ENOENT;
9864
9865 survey->channel = conf->chandef.chan;
9866
9867 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
9868 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
9869 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
9870
9871 if (idle || busy) {
9872 survey->filled = SURVEY_INFO_TIME |
9873 SURVEY_INFO_TIME_BUSY |
9874 SURVEY_INFO_TIME_EXT_BUSY;
9875
9876 survey->time = (idle + busy) / 1000;
9877 survey->time_busy = busy / 1000;
9878 survey->time_ext_busy = busy_ext / 1000;
9879 }
9880
9881 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9882 survey->filled |= SURVEY_INFO_IN_USE;
9883
9884 return 0;
9885
9886 }
9887 EXPORT_SYMBOL_GPL(rt2800_get_survey);
9888
9889 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9890 MODULE_VERSION(DRV_VERSION);
9891 MODULE_DESCRIPTION("Ralink RT2800 library");
9892 MODULE_LICENSE("GPL");
Linux with added FPC-III support