drivers/pci/controller/dwc/pci-meson.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCIe host controller driver for Amlogic MESON SoCs
   4  *
   5  * Copyright (c) 2018 Amlogic, inc.
   6  * Author: Yue Wang <yue.wang@amlogic.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/pci.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/reset.h>
  17 #include <linux/resource.h>
  18 #include <linux/types.h>
  19
  20 #include "pcie-designware.h"
  21
  22 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
  23
  24 /* External local bus interface registers */
  25 #define PLR_OFFSET                      0x700
  26 #define PCIE_PORT_LINK_CTRL_OFF         (PLR_OFFSET + 0x10)
  27 #define FAST_LINK_MODE                  BIT(7)
  28 #define LINK_CAPABLE_MASK               GENMASK(21, 16)
  29 #define LINK_CAPABLE_X1                 BIT(16)
  30
  31 #define PCIE_GEN2_CTRL_OFF              (PLR_OFFSET + 0x10c)
  32 #define NUM_OF_LANES_MASK               GENMASK(12, 8)
  33 #define NUM_OF_LANES_X1                 BIT(8)
  34 #define DIRECT_SPEED_CHANGE             BIT(17)
  35
  36 #define TYPE1_HDR_OFFSET                0x0
  37 #define PCIE_STATUS_COMMAND             (TYPE1_HDR_OFFSET + 0x04)
  38 #define PCI_IO_EN                       BIT(0)
  39 #define PCI_MEM_SPACE_EN                BIT(1)
  40 #define PCI_BUS_MASTER_EN               BIT(2)
  41
  42 #define PCIE_BASE_ADDR0                 (TYPE1_HDR_OFFSET + 0x10)
  43 #define PCIE_BASE_ADDR1                 (TYPE1_HDR_OFFSET + 0x14)
  44
  45 #define PCIE_CAP_OFFSET                 0x70
  46 #define PCIE_DEV_CTRL_DEV_STUS          (PCIE_CAP_OFFSET + 0x08)
  47 #define PCIE_CAP_MAX_PAYLOAD_MASK       GENMASK(7, 5)
  48 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x)    ((x) << 5)
  49 #define PCIE_CAP_MAX_READ_REQ_MASK      GENMASK(14, 12)
  50 #define PCIE_CAP_MAX_READ_REQ_SIZE(x)   ((x) << 12)
  51
  52 /* PCIe specific config registers */
  53 #define PCIE_CFG0                       0x0
  54 #define APP_LTSSM_ENABLE                BIT(7)
  55
  56 #define PCIE_CFG_STATUS12               0x30
  57 #define IS_SMLH_LINK_UP(x)              ((x) & (1 << 6))
  58 #define IS_RDLH_LINK_UP(x)              ((x) & (1 << 16))
  59 #define IS_LTSSM_UP(x)                  ((((x) >> 10) & 0x1f) == 0x11)
  60
  61 #define PCIE_CFG_STATUS17               0x44
  62 #define PM_CURRENT_STATE(x)             (((x) >> 7) & 0x1)
  63
  64 #define WAIT_LINKUP_TIMEOUT             4000
  65 #define PORT_CLK_RATE                   100000000UL
  66 #define MAX_PAYLOAD_SIZE                256
  67 #define MAX_READ_REQ_SIZE               256
  68 #define MESON_PCIE_PHY_POWERUP          0x1c
  69 #define PCIE_RESET_DELAY                500
  70 #define PCIE_SHARED_RESET               1
  71 #define PCIE_NORMAL_RESET               0
  72
  73 enum pcie_data_rate {
  74         PCIE_GEN1,
  75         PCIE_GEN2,
  76         PCIE_GEN3,
  77         PCIE_GEN4
  78 };
  79
  80 struct meson_pcie_mem_res {
  81         void __iomem *elbi_base;
  82         void __iomem *cfg_base;
  83         void __iomem *phy_base;
  84 };
  85
  86 struct meson_pcie_clk_res {
  87         struct clk *clk;
  88         struct clk *mipi_gate;
  89         struct clk *port_clk;
  90         struct clk *general_clk;
  91 };
  92
  93 struct meson_pcie_rc_reset {
  94         struct reset_control *phy;
  95         struct reset_control *port;
  96         struct reset_control *apb;
  97 };
  98
  99 struct meson_pcie {
 100         struct dw_pcie pci;
 101         struct meson_pcie_mem_res mem_res;
 102         struct meson_pcie_clk_res clk_res;
 103         struct meson_pcie_rc_reset mrst;
 104         struct gpio_desc *reset_gpio;
 105 };
 106
 107 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
 108                                                   const char *id,
 109                                                   u32 reset_type)
 110 {
 111         struct device *dev = mp->pci.dev;
 112         struct reset_control *reset;
 113
 114         if (reset_type == PCIE_SHARED_RESET)
 115                 reset = devm_reset_control_get_shared(dev, id);
 116         else
 117                 reset = devm_reset_control_get(dev, id);
 118
 119         return reset;
 120 }
 121
 122 static int meson_pcie_get_resets(struct meson_pcie *mp)
 123 {
 124         struct meson_pcie_rc_reset *mrst = &mp->mrst;
 125
 126         mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
 127         if (IS_ERR(mrst->phy))
 128                 return PTR_ERR(mrst->phy);
 129         reset_control_deassert(mrst->phy);
 130
 131         mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
 132         if (IS_ERR(mrst->port))
 133                 return PTR_ERR(mrst->port);
 134         reset_control_deassert(mrst->port);
 135
 136         mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
 137         if (IS_ERR(mrst->apb))
 138                 return PTR_ERR(mrst->apb);
 139         reset_control_deassert(mrst->apb);
 140
 141         return 0;
 142 }
 143
 144 static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
 145                                         struct meson_pcie *mp,
 146                                         const char *id)
 147 {
 148         struct device *dev = mp->pci.dev;
 149         struct resource *res;
 150
 151         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
 152
 153         return devm_ioremap_resource(dev, res);
 154 }
 155
 156 static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
 157                                                struct meson_pcie *mp,
 158                                                const char *id)
 159 {
 160         struct device *dev = mp->pci.dev;
 161         struct resource *res;
 162
 163         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
 164         if (!res) {
 165                 dev_err(dev, "No REG resource %s\n", id);
 166                 return ERR_PTR(-ENXIO);
 167         }
 168
 169         return devm_ioremap(dev, res->start, resource_size(res));
 170 }
 171
 172 static int meson_pcie_get_mems(struct platform_device *pdev,
 173                                struct meson_pcie *mp)
 174 {
 175         mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
 176         if (IS_ERR(mp->mem_res.elbi_base))
 177                 return PTR_ERR(mp->mem_res.elbi_base);
 178
 179         mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
 180         if (IS_ERR(mp->mem_res.cfg_base))
 181                 return PTR_ERR(mp->mem_res.cfg_base);
 182
 183         /* Meson SoC has two PCI controllers use same phy register*/
 184         mp->mem_res.phy_base = meson_pcie_get_mem_shared(pdev, mp, "phy");
 185         if (IS_ERR(mp->mem_res.phy_base))
 186                 return PTR_ERR(mp->mem_res.phy_base);
 187
 188         return 0;
 189 }
 190
 191 static void meson_pcie_power_on(struct meson_pcie *mp)
 192 {
 193         writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
 194 }
 195
 196 static void meson_pcie_reset(struct meson_pcie *mp)
 197 {
 198         struct meson_pcie_rc_reset *mrst = &mp->mrst;
 199
 200         reset_control_assert(mrst->phy);
 201         udelay(PCIE_RESET_DELAY);
 202         reset_control_deassert(mrst->phy);
 203         udelay(PCIE_RESET_DELAY);
 204
 205         reset_control_assert(mrst->port);
 206         reset_control_assert(mrst->apb);
 207         udelay(PCIE_RESET_DELAY);
 208         reset_control_deassert(mrst->port);
 209         reset_control_deassert(mrst->apb);
 210         udelay(PCIE_RESET_DELAY);
 211 }
 212
 213 static inline struct clk *meson_pcie_probe_clock(struct device *dev,
 214                                                  const char *id, u64 rate)
 215 {
 216         struct clk *clk;
 217         int ret;
 218
 219         clk = devm_clk_get(dev, id);
 220         if (IS_ERR(clk))
 221                 return clk;
 222
 223         if (rate) {
 224                 ret = clk_set_rate(clk, rate);
 225                 if (ret) {
 226                         dev_err(dev, "set clk rate failed, ret = %d\n", ret);
 227                         return ERR_PTR(ret);
 228                 }
 229         }
 230
 231         ret = clk_prepare_enable(clk);
 232         if (ret) {
 233                 dev_err(dev, "couldn't enable clk\n");
 234                 return ERR_PTR(ret);
 235         }
 236
 237         devm_add_action_or_reset(dev,
 238                                  (void (*) (void *))clk_disable_unprepare,
 239                                  clk);
 240
 241         return clk;
 242 }
 243
 244 static int meson_pcie_probe_clocks(struct meson_pcie *mp)
 245 {
 246         struct device *dev = mp->pci.dev;
 247         struct meson_pcie_clk_res *res = &mp->clk_res;
 248
 249         res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
 250         if (IS_ERR(res->port_clk))
 251                 return PTR_ERR(res->port_clk);
 252
 253         res->mipi_gate = meson_pcie_probe_clock(dev, "pcie_mipi_en", 0);
 254         if (IS_ERR(res->mipi_gate))
 255                 return PTR_ERR(res->mipi_gate);
 256
 257         res->general_clk = meson_pcie_probe_clock(dev, "pcie_general", 0);
 258         if (IS_ERR(res->general_clk))
 259                 return PTR_ERR(res->general_clk);
 260
 261         res->clk = meson_pcie_probe_clock(dev, "pcie", 0);
 262         if (IS_ERR(res->clk))
 263                 return PTR_ERR(res->clk);
 264
 265         return 0;
 266 }
 267
 268 static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
 269 {
 270         writel(val, mp->mem_res.elbi_base + reg);
 271 }
 272
 273 static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
 274 {
 275         return readl(mp->mem_res.elbi_base + reg);
 276 }
 277
 278 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
 279 {
 280         return readl(mp->mem_res.cfg_base + reg);
 281 }
 282
 283 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
 284 {
 285         writel(val, mp->mem_res.cfg_base + reg);
 286 }
 287
 288 static void meson_pcie_assert_reset(struct meson_pcie *mp)
 289 {
 290         gpiod_set_value_cansleep(mp->reset_gpio, 0);
 291         udelay(500);
 292         gpiod_set_value_cansleep(mp->reset_gpio, 1);
 293 }
 294
 295 static void meson_pcie_init_dw(struct meson_pcie *mp)
 296 {
 297         u32 val;
 298
 299         val = meson_cfg_readl(mp, PCIE_CFG0);
 300         val |= APP_LTSSM_ENABLE;
 301         meson_cfg_writel(mp, val, PCIE_CFG0);
 302
 303         val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
 304         val &= ~LINK_CAPABLE_MASK;
 305         meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
 306
 307         val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
 308         val |= LINK_CAPABLE_X1 | FAST_LINK_MODE;
 309         meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
 310
 311         val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
 312         val &= ~NUM_OF_LANES_MASK;
 313         meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
 314
 315         val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
 316         val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
 317         meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
 318
 319         meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
 320         meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
 321 }
 322
 323 static int meson_size_to_payload(struct meson_pcie *mp, int size)
 324 {
 325         struct device *dev = mp->pci.dev;
 326
 327         /*
 328          * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
 329          * So if input size is not 2^order alignment or less than 2^7 or bigger
 330          * than 2^12, just set to default size 2^(1+7).
 331          */
 332         if (!is_power_of_2(size) || size < 128 || size > 4096) {
 333                 dev_warn(dev, "payload size %d, set to default 256\n", size);
 334                 return 1;
 335         }
 336
 337         return fls(size) - 8;
 338 }
 339
 340 static void meson_set_max_payload(struct meson_pcie *mp, int size)
 341 {
 342         u32 val;
 343         int max_payload_size = meson_size_to_payload(mp, size);
 344
 345         val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
 346         val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
 347         meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
 348
 349         val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
 350         val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
 351         meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
 352 }
 353
 354 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
 355 {
 356         u32 val;
 357         int max_rd_req_size = meson_size_to_payload(mp, size);
 358
 359         val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
 360         val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
 361         meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
 362
 363         val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
 364         val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
 365         meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
 366 }
 367
 368 static inline void meson_enable_memory_space(struct meson_pcie *mp)
 369 {
 370         /* Set the RC Bus Master, Memory Space and I/O Space enables */
 371         meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
 372                          PCIE_STATUS_COMMAND);
 373 }
 374
 375 static int meson_pcie_establish_link(struct meson_pcie *mp)
 376 {
 377         struct dw_pcie *pci = &mp->pci;
 378         struct pcie_port *pp = &pci->pp;
 379
 380         meson_pcie_init_dw(mp);
 381         meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
 382         meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
 383
 384         dw_pcie_setup_rc(pp);
 385         meson_enable_memory_space(mp);
 386
 387         meson_pcie_assert_reset(mp);
 388
 389         return dw_pcie_wait_for_link(pci);
 390 }
 391
 392 static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
 393 {
 394         if (IS_ENABLED(CONFIG_PCI_MSI))
 395                 dw_pcie_msi_init(&mp->pci.pp);
 396 }
 397
 398 static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 399                                   u32 *val)
 400 {
 401         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 402         int ret;
 403
 404         ret = dw_pcie_read(pci->dbi_base + where, size, val);
 405         if (ret != PCIBIOS_SUCCESSFUL)
 406                 return ret;
 407
 408         /*
 409          * There is a bug in the MESON AXG PCIe controller whereby software
 410          * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
 411          * the return value in the config accessors.
 412          */
 413         if (where == PCI_CLASS_REVISION && size == 4)
 414                 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
 415         else if (where == PCI_CLASS_DEVICE && size == 2)
 416                 *val = PCI_CLASS_BRIDGE_PCI;
 417         else if (where == PCI_CLASS_DEVICE && size == 1)
 418                 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
 419         else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
 420                 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
 421
 422         return PCIBIOS_SUCCESSFUL;
 423 }
 424
 425 static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
 426                                   int size, u32 val)
 427 {
 428         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 429
 430         return dw_pcie_write(pci->dbi_base + where, size, val);
 431 }
 432
 433 static int meson_pcie_link_up(struct dw_pcie *pci)
 434 {
 435         struct meson_pcie *mp = to_meson_pcie(pci);
 436         struct device *dev = pci->dev;
 437         u32 speed_okay = 0;
 438         u32 cnt = 0;
 439         u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
 440
 441         do {
 442                 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
 443                 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
 444                 smlh_up = IS_SMLH_LINK_UP(state12);
 445                 rdlh_up = IS_RDLH_LINK_UP(state12);
 446                 ltssm_up = IS_LTSSM_UP(state12);
 447
 448                 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
 449                         speed_okay = 1;
 450
 451                 if (smlh_up)
 452                         dev_dbg(dev, "smlh_link_up is on\n");
 453                 if (rdlh_up)
 454                         dev_dbg(dev, "rdlh_link_up is on\n");
 455                 if (ltssm_up)
 456                         dev_dbg(dev, "ltssm_up is on\n");
 457                 if (speed_okay)
 458                         dev_dbg(dev, "speed_okay\n");
 459
 460                 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
 461                         return 1;
 462
 463                 cnt++;
 464
 465                 udelay(10);
 466         } while (cnt < WAIT_LINKUP_TIMEOUT);
 467
 468         dev_err(dev, "error: wait linkup timeout\n");
 469         return 0;
 470 }
 471
 472 static int meson_pcie_host_init(struct pcie_port *pp)
 473 {
 474         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 475         struct meson_pcie *mp = to_meson_pcie(pci);
 476         int ret;
 477
 478         ret = meson_pcie_establish_link(mp);
 479         if (ret)
 480                 return ret;
 481
 482         meson_pcie_enable_interrupts(mp);
 483
 484         return 0;
 485 }
 486
 487 static const struct dw_pcie_host_ops meson_pcie_host_ops = {
 488         .rd_own_conf = meson_pcie_rd_own_conf,
 489         .wr_own_conf = meson_pcie_wr_own_conf,
 490         .host_init = meson_pcie_host_init,
 491 };
 492
 493 static int meson_add_pcie_port(struct meson_pcie *mp,
 494                                struct platform_device *pdev)
 495 {
 496         struct dw_pcie *pci = &mp->pci;
 497         struct pcie_port *pp = &pci->pp;
 498         struct device *dev = &pdev->dev;
 499         int ret;
 500
 501         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 502                 pp->msi_irq = platform_get_irq(pdev, 0);
 503                 if (pp->msi_irq < 0) {
 504                         dev_err(dev, "failed to get MSI IRQ\n");
 505                         return pp->msi_irq;
 506                 }
 507         }
 508
 509         pp->ops = &meson_pcie_host_ops;
 510         pci->dbi_base = mp->mem_res.elbi_base;
 511
 512         ret = dw_pcie_host_init(pp);
 513         if (ret) {
 514                 dev_err(dev, "failed to initialize host\n");
 515                 return ret;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static const struct dw_pcie_ops dw_pcie_ops = {
 522         .link_up = meson_pcie_link_up,
 523 };
 524
 525 static int meson_pcie_probe(struct platform_device *pdev)
 526 {
 527         struct device *dev = &pdev->dev;
 528         struct dw_pcie *pci;
 529         struct meson_pcie *mp;
 530         int ret;
 531
 532         mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
 533         if (!mp)
 534                 return -ENOMEM;
 535
 536         pci = &mp->pci;
 537         pci->dev = dev;
 538         pci->ops = &dw_pcie_ops;
 539
 540         mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
 541         if (IS_ERR(mp->reset_gpio)) {
 542                 dev_err(dev, "get reset gpio failed\n");
 543                 return PTR_ERR(mp->reset_gpio);
 544         }
 545
 546         ret = meson_pcie_get_resets(mp);
 547         if (ret) {
 548                 dev_err(dev, "get reset resource failed, %d\n", ret);
 549                 return ret;
 550         }
 551
 552         ret = meson_pcie_get_mems(pdev, mp);
 553         if (ret) {
 554                 dev_err(dev, "get memory resource failed, %d\n", ret);
 555                 return ret;
 556         }
 557
 558         meson_pcie_power_on(mp);
 559         meson_pcie_reset(mp);
 560
 561         ret = meson_pcie_probe_clocks(mp);
 562         if (ret) {
 563                 dev_err(dev, "init clock resources failed, %d\n", ret);
 564                 return ret;
 565         }
 566
 567         platform_set_drvdata(pdev, mp);
 568
 569         ret = meson_add_pcie_port(mp, pdev);
 570         if (ret < 0) {
 571                 dev_err(dev, "Add PCIe port failed, %d\n", ret);
 572                 return ret;
 573         }
 574
 575         return 0;
 576 }
 577
 578 static const struct of_device_id meson_pcie_of_match[] = {
 579         {
 580                 .compatible = "amlogic,axg-pcie",
 581         },
 582         {},
 583 };
 584
 585 static struct platform_driver meson_pcie_driver = {
 586         .probe = meson_pcie_probe,
 587         .driver = {
 588                 .name = "meson-pcie",
 589                 .of_match_table = meson_pcie_of_match,
 590         },
 591 };
 592
 593 builtin_platform_driver(meson_pcie_driver);