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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / soc / mediatek / mtk-pmic-wrap.c
blob8236a6c87e19f0bcd3f066b409307a844c2f1e61
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #include <linux/clk.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
25 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
27 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
29 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
30 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
33
34 /* macro for wrapper status */
35 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
36 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
37 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
38 #define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
39 #define PWRAP_STATE_INIT_DONE0 (1 << 21)
40
41 /* macro for WACS FSM */
42 #define PWRAP_WACS_FSM_IDLE 0x00
43 #define PWRAP_WACS_FSM_REQ 0x02
44 #define PWRAP_WACS_FSM_WFDLE 0x04
45 #define PWRAP_WACS_FSM_WFVLDCLR 0x06
46 #define PWRAP_WACS_INIT_DONE 0x01
47 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
48 #define PWRAP_WACS_SYNC_BUSY 0x00
49
50 /* macro for device wrapper default value */
51 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
52 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
53
54 /* macro for manual command */
55 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
56 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
57 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
58 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
59 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
60 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
61 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
62 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
63
64 /* macro for Watch Dog Timer Source */
65 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
67 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
68 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
69 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
70 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
71 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
72
73 /* Group of bits used for shown slave capability */
74 #define PWRAP_SLV_CAP_SPI BIT(0)
75 #define PWRAP_SLV_CAP_DUALIO BIT(1)
76 #define PWRAP_SLV_CAP_SECURITY BIT(2)
77 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
78
79 /* Group of bits used for shown pwrap capability */
80 #define PWRAP_CAP_BRIDGE BIT(0)
81 #define PWRAP_CAP_RESET BIT(1)
82 #define PWRAP_CAP_DCM BIT(2)
83 #define PWRAP_CAP_INT1_EN BIT(3)
84 #define PWRAP_CAP_WDT_SRC1 BIT(4)
85
86 /* defines for slave device wrapper registers */
87 enum dew_regs {
88 PWRAP_DEW_BASE,
89 PWRAP_DEW_DIO_EN,
90 PWRAP_DEW_READ_TEST,
91 PWRAP_DEW_WRITE_TEST,
92 PWRAP_DEW_CRC_EN,
93 PWRAP_DEW_CRC_VAL,
94 PWRAP_DEW_MON_GRP_SEL,
95 PWRAP_DEW_CIPHER_KEY_SEL,
96 PWRAP_DEW_CIPHER_IV_SEL,
97 PWRAP_DEW_CIPHER_RDY,
98 PWRAP_DEW_CIPHER_MODE,
99 PWRAP_DEW_CIPHER_SWRST,
100
101 /* MT6323 only regs */
102 PWRAP_DEW_CIPHER_EN,
103 PWRAP_DEW_RDDMY_NO,
104
105 /* MT6358 only regs */
106 PWRAP_SMT_CON1,
107 PWRAP_DRV_CON1,
108 PWRAP_FILTER_CON0,
109 PWRAP_GPIO_PULLEN0_CLR,
110 PWRAP_RG_SPI_CON0,
111 PWRAP_RG_SPI_RECORD0,
112 PWRAP_RG_SPI_CON2,
113 PWRAP_RG_SPI_CON3,
114 PWRAP_RG_SPI_CON4,
115 PWRAP_RG_SPI_CON5,
116 PWRAP_RG_SPI_CON6,
117 PWRAP_RG_SPI_CON7,
118 PWRAP_RG_SPI_CON8,
119 PWRAP_RG_SPI_CON13,
120 PWRAP_SPISLV_KEY,
121
122 /* MT6397 only regs */
123 PWRAP_DEW_EVENT_OUT_EN,
124 PWRAP_DEW_EVENT_SRC_EN,
125 PWRAP_DEW_EVENT_SRC,
126 PWRAP_DEW_EVENT_FLAG,
127 PWRAP_DEW_MON_FLAG_SEL,
128 PWRAP_DEW_EVENT_TEST,
129 PWRAP_DEW_CIPHER_LOAD,
130 PWRAP_DEW_CIPHER_START,
131 };
132
133 static const u32 mt6323_regs[] = {
134 [PWRAP_DEW_BASE] = 0x0000,
135 [PWRAP_DEW_DIO_EN] = 0x018a,
136 [PWRAP_DEW_READ_TEST] = 0x018c,
137 [PWRAP_DEW_WRITE_TEST] = 0x018e,
138 [PWRAP_DEW_CRC_EN] = 0x0192,
139 [PWRAP_DEW_CRC_VAL] = 0x0194,
140 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
141 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
142 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
143 [PWRAP_DEW_CIPHER_EN] = 0x019c,
144 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
145 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
146 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
147 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
148 };
149
150 static const u32 mt6351_regs[] = {
151 [PWRAP_DEW_DIO_EN] = 0x02F2,
152 [PWRAP_DEW_READ_TEST] = 0x02F4,
153 [PWRAP_DEW_WRITE_TEST] = 0x02F6,
154 [PWRAP_DEW_CRC_EN] = 0x02FA,
155 [PWRAP_DEW_CRC_VAL] = 0x02FC,
156 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
157 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
158 [PWRAP_DEW_CIPHER_EN] = 0x0304,
159 [PWRAP_DEW_CIPHER_RDY] = 0x0306,
160 [PWRAP_DEW_CIPHER_MODE] = 0x0308,
161 [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
162 [PWRAP_DEW_RDDMY_NO] = 0x030C,
163 };
164
165 static const u32 mt6357_regs[] = {
166 [PWRAP_DEW_DIO_EN] = 0x040A,
167 [PWRAP_DEW_READ_TEST] = 0x040C,
168 [PWRAP_DEW_WRITE_TEST] = 0x040E,
169 [PWRAP_DEW_CRC_EN] = 0x0412,
170 [PWRAP_DEW_CRC_VAL] = 0x0414,
171 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
172 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
173 [PWRAP_DEW_CIPHER_EN] = 0x041C,
174 [PWRAP_DEW_CIPHER_RDY] = 0x041E,
175 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
176 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
177 [PWRAP_DEW_RDDMY_NO] = 0x0424,
178 };
179
180 static const u32 mt6358_regs[] = {
181 [PWRAP_SMT_CON1] = 0x0030,
182 [PWRAP_DRV_CON1] = 0x0038,
183 [PWRAP_FILTER_CON0] = 0x0040,
184 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
185 [PWRAP_RG_SPI_CON0] = 0x0408,
186 [PWRAP_RG_SPI_RECORD0] = 0x040a,
187 [PWRAP_DEW_DIO_EN] = 0x040c,
188 [PWRAP_DEW_READ_TEST] = 0x040e,
189 [PWRAP_DEW_WRITE_TEST] = 0x0410,
190 [PWRAP_DEW_CRC_EN] = 0x0414,
191 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
192 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
193 [PWRAP_DEW_CIPHER_EN] = 0x041e,
194 [PWRAP_DEW_CIPHER_RDY] = 0x0420,
195 [PWRAP_DEW_CIPHER_MODE] = 0x0422,
196 [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
197 [PWRAP_RG_SPI_CON2] = 0x0432,
198 [PWRAP_RG_SPI_CON3] = 0x0434,
199 [PWRAP_RG_SPI_CON4] = 0x0436,
200 [PWRAP_RG_SPI_CON5] = 0x0438,
201 [PWRAP_RG_SPI_CON6] = 0x043a,
202 [PWRAP_RG_SPI_CON7] = 0x043c,
203 [PWRAP_RG_SPI_CON8] = 0x043e,
204 [PWRAP_RG_SPI_CON13] = 0x0448,
205 [PWRAP_SPISLV_KEY] = 0x044a,
206 };
207
208 static const u32 mt6397_regs[] = {
209 [PWRAP_DEW_BASE] = 0xbc00,
210 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
211 [PWRAP_DEW_DIO_EN] = 0xbc02,
212 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
213 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
214 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
215 [PWRAP_DEW_READ_TEST] = 0xbc0a,
216 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
217 [PWRAP_DEW_CRC_EN] = 0xbc0e,
218 [PWRAP_DEW_CRC_VAL] = 0xbc10,
219 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
220 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
221 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
222 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
223 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
224 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
225 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
226 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
227 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
228 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
229 };
230
231 enum pwrap_regs {
232 PWRAP_MUX_SEL,
233 PWRAP_WRAP_EN,
234 PWRAP_DIO_EN,
235 PWRAP_SIDLY,
236 PWRAP_CSHEXT_WRITE,
237 PWRAP_CSHEXT_READ,
238 PWRAP_CSLEXT_START,
239 PWRAP_CSLEXT_END,
240 PWRAP_STAUPD_PRD,
241 PWRAP_STAUPD_GRPEN,
242 PWRAP_STAUPD_MAN_TRIG,
243 PWRAP_STAUPD_STA,
244 PWRAP_WRAP_STA,
245 PWRAP_HARB_INIT,
246 PWRAP_HARB_HPRIO,
247 PWRAP_HIPRIO_ARB_EN,
248 PWRAP_HARB_STA0,
249 PWRAP_HARB_STA1,
250 PWRAP_MAN_EN,
251 PWRAP_MAN_CMD,
252 PWRAP_MAN_RDATA,
253 PWRAP_MAN_VLDCLR,
254 PWRAP_WACS0_EN,
255 PWRAP_INIT_DONE0,
256 PWRAP_WACS0_CMD,
257 PWRAP_WACS0_RDATA,
258 PWRAP_WACS0_VLDCLR,
259 PWRAP_WACS1_EN,
260 PWRAP_INIT_DONE1,
261 PWRAP_WACS1_CMD,
262 PWRAP_WACS1_RDATA,
263 PWRAP_WACS1_VLDCLR,
264 PWRAP_WACS2_EN,
265 PWRAP_INIT_DONE2,
266 PWRAP_WACS2_CMD,
267 PWRAP_WACS2_RDATA,
268 PWRAP_WACS2_VLDCLR,
269 PWRAP_INT_EN,
270 PWRAP_INT_FLG_RAW,
271 PWRAP_INT_FLG,
272 PWRAP_INT_CLR,
273 PWRAP_SIG_ADR,
274 PWRAP_SIG_MODE,
275 PWRAP_SIG_VALUE,
276 PWRAP_SIG_ERRVAL,
277 PWRAP_CRC_EN,
278 PWRAP_TIMER_EN,
279 PWRAP_TIMER_STA,
280 PWRAP_WDT_UNIT,
281 PWRAP_WDT_SRC_EN,
282 PWRAP_WDT_FLG,
283 PWRAP_DEBUG_INT_SEL,
284 PWRAP_CIPHER_KEY_SEL,
285 PWRAP_CIPHER_IV_SEL,
286 PWRAP_CIPHER_RDY,
287 PWRAP_CIPHER_MODE,
288 PWRAP_CIPHER_SWRST,
289 PWRAP_DCM_EN,
290 PWRAP_DCM_DBC_PRD,
291 PWRAP_EINT_STA0_ADR,
292 PWRAP_EINT_STA1_ADR,
293
294 /* MT2701 only regs */
295 PWRAP_ADC_CMD_ADDR,
296 PWRAP_PWRAP_ADC_CMD,
297 PWRAP_ADC_RDY_ADDR,
298 PWRAP_ADC_RDATA_ADDR1,
299 PWRAP_ADC_RDATA_ADDR2,
300
301 /* MT7622 only regs */
302 PWRAP_STA,
303 PWRAP_CLR,
304 PWRAP_DVFS_ADR8,
305 PWRAP_DVFS_WDATA8,
306 PWRAP_DVFS_ADR9,
307 PWRAP_DVFS_WDATA9,
308 PWRAP_DVFS_ADR10,
309 PWRAP_DVFS_WDATA10,
310 PWRAP_DVFS_ADR11,
311 PWRAP_DVFS_WDATA11,
312 PWRAP_DVFS_ADR12,
313 PWRAP_DVFS_WDATA12,
314 PWRAP_DVFS_ADR13,
315 PWRAP_DVFS_WDATA13,
316 PWRAP_DVFS_ADR14,
317 PWRAP_DVFS_WDATA14,
318 PWRAP_DVFS_ADR15,
319 PWRAP_DVFS_WDATA15,
320 PWRAP_EXT_CK,
321 PWRAP_ADC_RDATA_ADDR,
322 PWRAP_GPS_STA,
323 PWRAP_SW_RST,
324 PWRAP_DVFS_STEP_CTRL0,
325 PWRAP_DVFS_STEP_CTRL1,
326 PWRAP_DVFS_STEP_CTRL2,
327 PWRAP_SPI2_CTRL,
328
329 /* MT8135 only regs */
330 PWRAP_CSHEXT,
331 PWRAP_EVENT_IN_EN,
332 PWRAP_EVENT_DST_EN,
333 PWRAP_RRARB_INIT,
334 PWRAP_RRARB_EN,
335 PWRAP_RRARB_STA0,
336 PWRAP_RRARB_STA1,
337 PWRAP_EVENT_STA,
338 PWRAP_EVENT_STACLR,
339 PWRAP_CIPHER_LOAD,
340 PWRAP_CIPHER_START,
341
342 /* MT8173 only regs */
343 PWRAP_RDDMY,
344 PWRAP_SI_CK_CON,
345 PWRAP_DVFS_ADR0,
346 PWRAP_DVFS_WDATA0,
347 PWRAP_DVFS_ADR1,
348 PWRAP_DVFS_WDATA1,
349 PWRAP_DVFS_ADR2,
350 PWRAP_DVFS_WDATA2,
351 PWRAP_DVFS_ADR3,
352 PWRAP_DVFS_WDATA3,
353 PWRAP_DVFS_ADR4,
354 PWRAP_DVFS_WDATA4,
355 PWRAP_DVFS_ADR5,
356 PWRAP_DVFS_WDATA5,
357 PWRAP_DVFS_ADR6,
358 PWRAP_DVFS_WDATA6,
359 PWRAP_DVFS_ADR7,
360 PWRAP_DVFS_WDATA7,
361 PWRAP_SPMINF_STA,
362 PWRAP_CIPHER_EN,
363
364 /* MT8183 only regs */
365 PWRAP_SI_SAMPLE_CTRL,
366 PWRAP_CSLEXT_WRITE,
367 PWRAP_CSLEXT_READ,
368 PWRAP_EXT_CK_WRITE,
369 PWRAP_STAUPD_CTRL,
370 PWRAP_WACS_P2P_EN,
371 PWRAP_INIT_DONE_P2P,
372 PWRAP_WACS_MD32_EN,
373 PWRAP_INIT_DONE_MD32,
374 PWRAP_INT1_EN,
375 PWRAP_INT1_FLG,
376 PWRAP_INT1_CLR,
377 PWRAP_WDT_SRC_EN_1,
378 PWRAP_INT_GPS_AUXADC_CMD_ADDR,
379 PWRAP_INT_GPS_AUXADC_CMD,
380 PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
381 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
382 PWRAP_GPSINF_0_STA,
383 PWRAP_GPSINF_1_STA,
384 };
385
386 static int mt2701_regs[] = {
387 [PWRAP_MUX_SEL] = 0x0,
388 [PWRAP_WRAP_EN] = 0x4,
389 [PWRAP_DIO_EN] = 0x8,
390 [PWRAP_SIDLY] = 0xc,
391 [PWRAP_RDDMY] = 0x18,
392 [PWRAP_SI_CK_CON] = 0x1c,
393 [PWRAP_CSHEXT_WRITE] = 0x20,
394 [PWRAP_CSHEXT_READ] = 0x24,
395 [PWRAP_CSLEXT_START] = 0x28,
396 [PWRAP_CSLEXT_END] = 0x2c,
397 [PWRAP_STAUPD_PRD] = 0x30,
398 [PWRAP_STAUPD_GRPEN] = 0x34,
399 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
400 [PWRAP_STAUPD_STA] = 0x3c,
401 [PWRAP_WRAP_STA] = 0x44,
402 [PWRAP_HARB_INIT] = 0x48,
403 [PWRAP_HARB_HPRIO] = 0x4c,
404 [PWRAP_HIPRIO_ARB_EN] = 0x50,
405 [PWRAP_HARB_STA0] = 0x54,
406 [PWRAP_HARB_STA1] = 0x58,
407 [PWRAP_MAN_EN] = 0x5c,
408 [PWRAP_MAN_CMD] = 0x60,
409 [PWRAP_MAN_RDATA] = 0x64,
410 [PWRAP_MAN_VLDCLR] = 0x68,
411 [PWRAP_WACS0_EN] = 0x6c,
412 [PWRAP_INIT_DONE0] = 0x70,
413 [PWRAP_WACS0_CMD] = 0x74,
414 [PWRAP_WACS0_RDATA] = 0x78,
415 [PWRAP_WACS0_VLDCLR] = 0x7c,
416 [PWRAP_WACS1_EN] = 0x80,
417 [PWRAP_INIT_DONE1] = 0x84,
418 [PWRAP_WACS1_CMD] = 0x88,
419 [PWRAP_WACS1_RDATA] = 0x8c,
420 [PWRAP_WACS1_VLDCLR] = 0x90,
421 [PWRAP_WACS2_EN] = 0x94,
422 [PWRAP_INIT_DONE2] = 0x98,
423 [PWRAP_WACS2_CMD] = 0x9c,
424 [PWRAP_WACS2_RDATA] = 0xa0,
425 [PWRAP_WACS2_VLDCLR] = 0xa4,
426 [PWRAP_INT_EN] = 0xa8,
427 [PWRAP_INT_FLG_RAW] = 0xac,
428 [PWRAP_INT_FLG] = 0xb0,
429 [PWRAP_INT_CLR] = 0xb4,
430 [PWRAP_SIG_ADR] = 0xb8,
431 [PWRAP_SIG_MODE] = 0xbc,
432 [PWRAP_SIG_VALUE] = 0xc0,
433 [PWRAP_SIG_ERRVAL] = 0xc4,
434 [PWRAP_CRC_EN] = 0xc8,
435 [PWRAP_TIMER_EN] = 0xcc,
436 [PWRAP_TIMER_STA] = 0xd0,
437 [PWRAP_WDT_UNIT] = 0xd4,
438 [PWRAP_WDT_SRC_EN] = 0xd8,
439 [PWRAP_WDT_FLG] = 0xdc,
440 [PWRAP_DEBUG_INT_SEL] = 0xe0,
441 [PWRAP_DVFS_ADR0] = 0xe4,
442 [PWRAP_DVFS_WDATA0] = 0xe8,
443 [PWRAP_DVFS_ADR1] = 0xec,
444 [PWRAP_DVFS_WDATA1] = 0xf0,
445 [PWRAP_DVFS_ADR2] = 0xf4,
446 [PWRAP_DVFS_WDATA2] = 0xf8,
447 [PWRAP_DVFS_ADR3] = 0xfc,
448 [PWRAP_DVFS_WDATA3] = 0x100,
449 [PWRAP_DVFS_ADR4] = 0x104,
450 [PWRAP_DVFS_WDATA4] = 0x108,
451 [PWRAP_DVFS_ADR5] = 0x10c,
452 [PWRAP_DVFS_WDATA5] = 0x110,
453 [PWRAP_DVFS_ADR6] = 0x114,
454 [PWRAP_DVFS_WDATA6] = 0x118,
455 [PWRAP_DVFS_ADR7] = 0x11c,
456 [PWRAP_DVFS_WDATA7] = 0x120,
457 [PWRAP_CIPHER_KEY_SEL] = 0x124,
458 [PWRAP_CIPHER_IV_SEL] = 0x128,
459 [PWRAP_CIPHER_EN] = 0x12c,
460 [PWRAP_CIPHER_RDY] = 0x130,
461 [PWRAP_CIPHER_MODE] = 0x134,
462 [PWRAP_CIPHER_SWRST] = 0x138,
463 [PWRAP_DCM_EN] = 0x13c,
464 [PWRAP_DCM_DBC_PRD] = 0x140,
465 [PWRAP_ADC_CMD_ADDR] = 0x144,
466 [PWRAP_PWRAP_ADC_CMD] = 0x148,
467 [PWRAP_ADC_RDY_ADDR] = 0x14c,
468 [PWRAP_ADC_RDATA_ADDR1] = 0x150,
469 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
470 };
471
472 static int mt6765_regs[] = {
473 [PWRAP_MUX_SEL] = 0x0,
474 [PWRAP_WRAP_EN] = 0x4,
475 [PWRAP_DIO_EN] = 0x8,
476 [PWRAP_RDDMY] = 0x20,
477 [PWRAP_CSHEXT_WRITE] = 0x24,
478 [PWRAP_CSHEXT_READ] = 0x28,
479 [PWRAP_CSLEXT_START] = 0x2C,
480 [PWRAP_CSLEXT_END] = 0x30,
481 [PWRAP_STAUPD_PRD] = 0x3C,
482 [PWRAP_HARB_HPRIO] = 0x68,
483 [PWRAP_HIPRIO_ARB_EN] = 0x6C,
484 [PWRAP_MAN_EN] = 0x7C,
485 [PWRAP_MAN_CMD] = 0x80,
486 [PWRAP_WACS0_EN] = 0x8C,
487 [PWRAP_WACS1_EN] = 0x94,
488 [PWRAP_WACS2_EN] = 0x9C,
489 [PWRAP_INIT_DONE2] = 0xA0,
490 [PWRAP_WACS2_CMD] = 0xC20,
491 [PWRAP_WACS2_RDATA] = 0xC24,
492 [PWRAP_WACS2_VLDCLR] = 0xC28,
493 [PWRAP_INT_EN] = 0xB4,
494 [PWRAP_INT_FLG_RAW] = 0xB8,
495 [PWRAP_INT_FLG] = 0xBC,
496 [PWRAP_INT_CLR] = 0xC0,
497 [PWRAP_TIMER_EN] = 0xE8,
498 [PWRAP_WDT_UNIT] = 0xF0,
499 [PWRAP_WDT_SRC_EN] = 0xF4,
500 [PWRAP_DCM_EN] = 0x1DC,
501 [PWRAP_DCM_DBC_PRD] = 0x1E0,
502 };
503
504 static int mt6797_regs[] = {
505 [PWRAP_MUX_SEL] = 0x0,
506 [PWRAP_WRAP_EN] = 0x4,
507 [PWRAP_DIO_EN] = 0x8,
508 [PWRAP_SIDLY] = 0xC,
509 [PWRAP_RDDMY] = 0x10,
510 [PWRAP_CSHEXT_WRITE] = 0x18,
511 [PWRAP_CSHEXT_READ] = 0x1C,
512 [PWRAP_CSLEXT_START] = 0x20,
513 [PWRAP_CSLEXT_END] = 0x24,
514 [PWRAP_STAUPD_PRD] = 0x28,
515 [PWRAP_HARB_HPRIO] = 0x50,
516 [PWRAP_HIPRIO_ARB_EN] = 0x54,
517 [PWRAP_MAN_EN] = 0x60,
518 [PWRAP_MAN_CMD] = 0x64,
519 [PWRAP_WACS0_EN] = 0x70,
520 [PWRAP_WACS1_EN] = 0x84,
521 [PWRAP_WACS2_EN] = 0x98,
522 [PWRAP_INIT_DONE2] = 0x9C,
523 [PWRAP_WACS2_CMD] = 0xA0,
524 [PWRAP_WACS2_RDATA] = 0xA4,
525 [PWRAP_WACS2_VLDCLR] = 0xA8,
526 [PWRAP_INT_EN] = 0xC0,
527 [PWRAP_INT_FLG_RAW] = 0xC4,
528 [PWRAP_INT_FLG] = 0xC8,
529 [PWRAP_INT_CLR] = 0xCC,
530 [PWRAP_TIMER_EN] = 0xF4,
531 [PWRAP_WDT_UNIT] = 0xFC,
532 [PWRAP_WDT_SRC_EN] = 0x100,
533 [PWRAP_DCM_EN] = 0x1CC,
534 [PWRAP_DCM_DBC_PRD] = 0x1D4,
535 };
536
537 static int mt7622_regs[] = {
538 [PWRAP_MUX_SEL] = 0x0,
539 [PWRAP_WRAP_EN] = 0x4,
540 [PWRAP_DIO_EN] = 0x8,
541 [PWRAP_SIDLY] = 0xC,
542 [PWRAP_RDDMY] = 0x10,
543 [PWRAP_SI_CK_CON] = 0x14,
544 [PWRAP_CSHEXT_WRITE] = 0x18,
545 [PWRAP_CSHEXT_READ] = 0x1C,
546 [PWRAP_CSLEXT_START] = 0x20,
547 [PWRAP_CSLEXT_END] = 0x24,
548 [PWRAP_STAUPD_PRD] = 0x28,
549 [PWRAP_STAUPD_GRPEN] = 0x2C,
550 [PWRAP_EINT_STA0_ADR] = 0x30,
551 [PWRAP_EINT_STA1_ADR] = 0x34,
552 [PWRAP_STA] = 0x38,
553 [PWRAP_CLR] = 0x3C,
554 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
555 [PWRAP_STAUPD_STA] = 0x44,
556 [PWRAP_WRAP_STA] = 0x48,
557 [PWRAP_HARB_INIT] = 0x4C,
558 [PWRAP_HARB_HPRIO] = 0x50,
559 [PWRAP_HIPRIO_ARB_EN] = 0x54,
560 [PWRAP_HARB_STA0] = 0x58,
561 [PWRAP_HARB_STA1] = 0x5C,
562 [PWRAP_MAN_EN] = 0x60,
563 [PWRAP_MAN_CMD] = 0x64,
564 [PWRAP_MAN_RDATA] = 0x68,
565 [PWRAP_MAN_VLDCLR] = 0x6C,
566 [PWRAP_WACS0_EN] = 0x70,
567 [PWRAP_INIT_DONE0] = 0x74,
568 [PWRAP_WACS0_CMD] = 0x78,
569 [PWRAP_WACS0_RDATA] = 0x7C,
570 [PWRAP_WACS0_VLDCLR] = 0x80,
571 [PWRAP_WACS1_EN] = 0x84,
572 [PWRAP_INIT_DONE1] = 0x88,
573 [PWRAP_WACS1_CMD] = 0x8C,
574 [PWRAP_WACS1_RDATA] = 0x90,
575 [PWRAP_WACS1_VLDCLR] = 0x94,
576 [PWRAP_WACS2_EN] = 0x98,
577 [PWRAP_INIT_DONE2] = 0x9C,
578 [PWRAP_WACS2_CMD] = 0xA0,
579 [PWRAP_WACS2_RDATA] = 0xA4,
580 [PWRAP_WACS2_VLDCLR] = 0xA8,
581 [PWRAP_INT_EN] = 0xAC,
582 [PWRAP_INT_FLG_RAW] = 0xB0,
583 [PWRAP_INT_FLG] = 0xB4,
584 [PWRAP_INT_CLR] = 0xB8,
585 [PWRAP_SIG_ADR] = 0xBC,
586 [PWRAP_SIG_MODE] = 0xC0,
587 [PWRAP_SIG_VALUE] = 0xC4,
588 [PWRAP_SIG_ERRVAL] = 0xC8,
589 [PWRAP_CRC_EN] = 0xCC,
590 [PWRAP_TIMER_EN] = 0xD0,
591 [PWRAP_TIMER_STA] = 0xD4,
592 [PWRAP_WDT_UNIT] = 0xD8,
593 [PWRAP_WDT_SRC_EN] = 0xDC,
594 [PWRAP_WDT_FLG] = 0xE0,
595 [PWRAP_DEBUG_INT_SEL] = 0xE4,
596 [PWRAP_DVFS_ADR0] = 0xE8,
597 [PWRAP_DVFS_WDATA0] = 0xEC,
598 [PWRAP_DVFS_ADR1] = 0xF0,
599 [PWRAP_DVFS_WDATA1] = 0xF4,
600 [PWRAP_DVFS_ADR2] = 0xF8,
601 [PWRAP_DVFS_WDATA2] = 0xFC,
602 [PWRAP_DVFS_ADR3] = 0x100,
603 [PWRAP_DVFS_WDATA3] = 0x104,
604 [PWRAP_DVFS_ADR4] = 0x108,
605 [PWRAP_DVFS_WDATA4] = 0x10C,
606 [PWRAP_DVFS_ADR5] = 0x110,
607 [PWRAP_DVFS_WDATA5] = 0x114,
608 [PWRAP_DVFS_ADR6] = 0x118,
609 [PWRAP_DVFS_WDATA6] = 0x11C,
610 [PWRAP_DVFS_ADR7] = 0x120,
611 [PWRAP_DVFS_WDATA7] = 0x124,
612 [PWRAP_DVFS_ADR8] = 0x128,
613 [PWRAP_DVFS_WDATA8] = 0x12C,
614 [PWRAP_DVFS_ADR9] = 0x130,
615 [PWRAP_DVFS_WDATA9] = 0x134,
616 [PWRAP_DVFS_ADR10] = 0x138,
617 [PWRAP_DVFS_WDATA10] = 0x13C,
618 [PWRAP_DVFS_ADR11] = 0x140,
619 [PWRAP_DVFS_WDATA11] = 0x144,
620 [PWRAP_DVFS_ADR12] = 0x148,
621 [PWRAP_DVFS_WDATA12] = 0x14C,
622 [PWRAP_DVFS_ADR13] = 0x150,
623 [PWRAP_DVFS_WDATA13] = 0x154,
624 [PWRAP_DVFS_ADR14] = 0x158,
625 [PWRAP_DVFS_WDATA14] = 0x15C,
626 [PWRAP_DVFS_ADR15] = 0x160,
627 [PWRAP_DVFS_WDATA15] = 0x164,
628 [PWRAP_SPMINF_STA] = 0x168,
629 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
630 [PWRAP_CIPHER_IV_SEL] = 0x170,
631 [PWRAP_CIPHER_EN] = 0x174,
632 [PWRAP_CIPHER_RDY] = 0x178,
633 [PWRAP_CIPHER_MODE] = 0x17C,
634 [PWRAP_CIPHER_SWRST] = 0x180,
635 [PWRAP_DCM_EN] = 0x184,
636 [PWRAP_DCM_DBC_PRD] = 0x188,
637 [PWRAP_EXT_CK] = 0x18C,
638 [PWRAP_ADC_CMD_ADDR] = 0x190,
639 [PWRAP_PWRAP_ADC_CMD] = 0x194,
640 [PWRAP_ADC_RDATA_ADDR] = 0x198,
641 [PWRAP_GPS_STA] = 0x19C,
642 [PWRAP_SW_RST] = 0x1A0,
643 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
644 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
645 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
646 [PWRAP_SPI2_CTRL] = 0x244,
647 };
648
649 static int mt8135_regs[] = {
650 [PWRAP_MUX_SEL] = 0x0,
651 [PWRAP_WRAP_EN] = 0x4,
652 [PWRAP_DIO_EN] = 0x8,
653 [PWRAP_SIDLY] = 0xc,
654 [PWRAP_CSHEXT] = 0x10,
655 [PWRAP_CSHEXT_WRITE] = 0x14,
656 [PWRAP_CSHEXT_READ] = 0x18,
657 [PWRAP_CSLEXT_START] = 0x1c,
658 [PWRAP_CSLEXT_END] = 0x20,
659 [PWRAP_STAUPD_PRD] = 0x24,
660 [PWRAP_STAUPD_GRPEN] = 0x28,
661 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
662 [PWRAP_STAUPD_STA] = 0x30,
663 [PWRAP_EVENT_IN_EN] = 0x34,
664 [PWRAP_EVENT_DST_EN] = 0x38,
665 [PWRAP_WRAP_STA] = 0x3c,
666 [PWRAP_RRARB_INIT] = 0x40,
667 [PWRAP_RRARB_EN] = 0x44,
668 [PWRAP_RRARB_STA0] = 0x48,
669 [PWRAP_RRARB_STA1] = 0x4c,
670 [PWRAP_HARB_INIT] = 0x50,
671 [PWRAP_HARB_HPRIO] = 0x54,
672 [PWRAP_HIPRIO_ARB_EN] = 0x58,
673 [PWRAP_HARB_STA0] = 0x5c,
674 [PWRAP_HARB_STA1] = 0x60,
675 [PWRAP_MAN_EN] = 0x64,
676 [PWRAP_MAN_CMD] = 0x68,
677 [PWRAP_MAN_RDATA] = 0x6c,
678 [PWRAP_MAN_VLDCLR] = 0x70,
679 [PWRAP_WACS0_EN] = 0x74,
680 [PWRAP_INIT_DONE0] = 0x78,
681 [PWRAP_WACS0_CMD] = 0x7c,
682 [PWRAP_WACS0_RDATA] = 0x80,
683 [PWRAP_WACS0_VLDCLR] = 0x84,
684 [PWRAP_WACS1_EN] = 0x88,
685 [PWRAP_INIT_DONE1] = 0x8c,
686 [PWRAP_WACS1_CMD] = 0x90,
687 [PWRAP_WACS1_RDATA] = 0x94,
688 [PWRAP_WACS1_VLDCLR] = 0x98,
689 [PWRAP_WACS2_EN] = 0x9c,
690 [PWRAP_INIT_DONE2] = 0xa0,
691 [PWRAP_WACS2_CMD] = 0xa4,
692 [PWRAP_WACS2_RDATA] = 0xa8,
693 [PWRAP_WACS2_VLDCLR] = 0xac,
694 [PWRAP_INT_EN] = 0xb0,
695 [PWRAP_INT_FLG_RAW] = 0xb4,
696 [PWRAP_INT_FLG] = 0xb8,
697 [PWRAP_INT_CLR] = 0xbc,
698 [PWRAP_SIG_ADR] = 0xc0,
699 [PWRAP_SIG_MODE] = 0xc4,
700 [PWRAP_SIG_VALUE] = 0xc8,
701 [PWRAP_SIG_ERRVAL] = 0xcc,
702 [PWRAP_CRC_EN] = 0xd0,
703 [PWRAP_EVENT_STA] = 0xd4,
704 [PWRAP_EVENT_STACLR] = 0xd8,
705 [PWRAP_TIMER_EN] = 0xdc,
706 [PWRAP_TIMER_STA] = 0xe0,
707 [PWRAP_WDT_UNIT] = 0xe4,
708 [PWRAP_WDT_SRC_EN] = 0xe8,
709 [PWRAP_WDT_FLG] = 0xec,
710 [PWRAP_DEBUG_INT_SEL] = 0xf0,
711 [PWRAP_CIPHER_KEY_SEL] = 0x134,
712 [PWRAP_CIPHER_IV_SEL] = 0x138,
713 [PWRAP_CIPHER_LOAD] = 0x13c,
714 [PWRAP_CIPHER_START] = 0x140,
715 [PWRAP_CIPHER_RDY] = 0x144,
716 [PWRAP_CIPHER_MODE] = 0x148,
717 [PWRAP_CIPHER_SWRST] = 0x14c,
718 [PWRAP_DCM_EN] = 0x15c,
719 [PWRAP_DCM_DBC_PRD] = 0x160,
720 };
721
722 static int mt8173_regs[] = {
723 [PWRAP_MUX_SEL] = 0x0,
724 [PWRAP_WRAP_EN] = 0x4,
725 [PWRAP_DIO_EN] = 0x8,
726 [PWRAP_SIDLY] = 0xc,
727 [PWRAP_RDDMY] = 0x10,
728 [PWRAP_SI_CK_CON] = 0x14,
729 [PWRAP_CSHEXT_WRITE] = 0x18,
730 [PWRAP_CSHEXT_READ] = 0x1c,
731 [PWRAP_CSLEXT_START] = 0x20,
732 [PWRAP_CSLEXT_END] = 0x24,
733 [PWRAP_STAUPD_PRD] = 0x28,
734 [PWRAP_STAUPD_GRPEN] = 0x2c,
735 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
736 [PWRAP_STAUPD_STA] = 0x44,
737 [PWRAP_WRAP_STA] = 0x48,
738 [PWRAP_HARB_INIT] = 0x4c,
739 [PWRAP_HARB_HPRIO] = 0x50,
740 [PWRAP_HIPRIO_ARB_EN] = 0x54,
741 [PWRAP_HARB_STA0] = 0x58,
742 [PWRAP_HARB_STA1] = 0x5c,
743 [PWRAP_MAN_EN] = 0x60,
744 [PWRAP_MAN_CMD] = 0x64,
745 [PWRAP_MAN_RDATA] = 0x68,
746 [PWRAP_MAN_VLDCLR] = 0x6c,
747 [PWRAP_WACS0_EN] = 0x70,
748 [PWRAP_INIT_DONE0] = 0x74,
749 [PWRAP_WACS0_CMD] = 0x78,
750 [PWRAP_WACS0_RDATA] = 0x7c,
751 [PWRAP_WACS0_VLDCLR] = 0x80,
752 [PWRAP_WACS1_EN] = 0x84,
753 [PWRAP_INIT_DONE1] = 0x88,
754 [PWRAP_WACS1_CMD] = 0x8c,
755 [PWRAP_WACS1_RDATA] = 0x90,
756 [PWRAP_WACS1_VLDCLR] = 0x94,
757 [PWRAP_WACS2_EN] = 0x98,
758 [PWRAP_INIT_DONE2] = 0x9c,
759 [PWRAP_WACS2_CMD] = 0xa0,
760 [PWRAP_WACS2_RDATA] = 0xa4,
761 [PWRAP_WACS2_VLDCLR] = 0xa8,
762 [PWRAP_INT_EN] = 0xac,
763 [PWRAP_INT_FLG_RAW] = 0xb0,
764 [PWRAP_INT_FLG] = 0xb4,
765 [PWRAP_INT_CLR] = 0xb8,
766 [PWRAP_SIG_ADR] = 0xbc,
767 [PWRAP_SIG_MODE] = 0xc0,
768 [PWRAP_SIG_VALUE] = 0xc4,
769 [PWRAP_SIG_ERRVAL] = 0xc8,
770 [PWRAP_CRC_EN] = 0xcc,
771 [PWRAP_TIMER_EN] = 0xd0,
772 [PWRAP_TIMER_STA] = 0xd4,
773 [PWRAP_WDT_UNIT] = 0xd8,
774 [PWRAP_WDT_SRC_EN] = 0xdc,
775 [PWRAP_WDT_FLG] = 0xe0,
776 [PWRAP_DEBUG_INT_SEL] = 0xe4,
777 [PWRAP_DVFS_ADR0] = 0xe8,
778 [PWRAP_DVFS_WDATA0] = 0xec,
779 [PWRAP_DVFS_ADR1] = 0xf0,
780 [PWRAP_DVFS_WDATA1] = 0xf4,
781 [PWRAP_DVFS_ADR2] = 0xf8,
782 [PWRAP_DVFS_WDATA2] = 0xfc,
783 [PWRAP_DVFS_ADR3] = 0x100,
784 [PWRAP_DVFS_WDATA3] = 0x104,
785 [PWRAP_DVFS_ADR4] = 0x108,
786 [PWRAP_DVFS_WDATA4] = 0x10c,
787 [PWRAP_DVFS_ADR5] = 0x110,
788 [PWRAP_DVFS_WDATA5] = 0x114,
789 [PWRAP_DVFS_ADR6] = 0x118,
790 [PWRAP_DVFS_WDATA6] = 0x11c,
791 [PWRAP_DVFS_ADR7] = 0x120,
792 [PWRAP_DVFS_WDATA7] = 0x124,
793 [PWRAP_SPMINF_STA] = 0x128,
794 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
795 [PWRAP_CIPHER_IV_SEL] = 0x130,
796 [PWRAP_CIPHER_EN] = 0x134,
797 [PWRAP_CIPHER_RDY] = 0x138,
798 [PWRAP_CIPHER_MODE] = 0x13c,
799 [PWRAP_CIPHER_SWRST] = 0x140,
800 [PWRAP_DCM_EN] = 0x144,
801 [PWRAP_DCM_DBC_PRD] = 0x148,
802 };
803
804 static int mt8183_regs[] = {
805 [PWRAP_MUX_SEL] = 0x0,
806 [PWRAP_WRAP_EN] = 0x4,
807 [PWRAP_DIO_EN] = 0x8,
808 [PWRAP_SI_SAMPLE_CTRL] = 0xC,
809 [PWRAP_RDDMY] = 0x14,
810 [PWRAP_CSHEXT_WRITE] = 0x18,
811 [PWRAP_CSHEXT_READ] = 0x1C,
812 [PWRAP_CSLEXT_WRITE] = 0x20,
813 [PWRAP_CSLEXT_READ] = 0x24,
814 [PWRAP_EXT_CK_WRITE] = 0x28,
815 [PWRAP_STAUPD_CTRL] = 0x30,
816 [PWRAP_STAUPD_GRPEN] = 0x34,
817 [PWRAP_EINT_STA0_ADR] = 0x38,
818 [PWRAP_HARB_HPRIO] = 0x5C,
819 [PWRAP_HIPRIO_ARB_EN] = 0x60,
820 [PWRAP_MAN_EN] = 0x70,
821 [PWRAP_MAN_CMD] = 0x74,
822 [PWRAP_WACS0_EN] = 0x80,
823 [PWRAP_INIT_DONE0] = 0x84,
824 [PWRAP_WACS1_EN] = 0x88,
825 [PWRAP_INIT_DONE1] = 0x8C,
826 [PWRAP_WACS2_EN] = 0x90,
827 [PWRAP_INIT_DONE2] = 0x94,
828 [PWRAP_WACS_P2P_EN] = 0xA0,
829 [PWRAP_INIT_DONE_P2P] = 0xA4,
830 [PWRAP_WACS_MD32_EN] = 0xA8,
831 [PWRAP_INIT_DONE_MD32] = 0xAC,
832 [PWRAP_INT_EN] = 0xB0,
833 [PWRAP_INT_FLG] = 0xB8,
834 [PWRAP_INT_CLR] = 0xBC,
835 [PWRAP_INT1_EN] = 0xC0,
836 [PWRAP_INT1_FLG] = 0xC8,
837 [PWRAP_INT1_CLR] = 0xCC,
838 [PWRAP_SIG_ADR] = 0xD0,
839 [PWRAP_CRC_EN] = 0xE0,
840 [PWRAP_TIMER_EN] = 0xE4,
841 [PWRAP_WDT_UNIT] = 0xEC,
842 [PWRAP_WDT_SRC_EN] = 0xF0,
843 [PWRAP_WDT_SRC_EN_1] = 0xF4,
844 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
845 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
846 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
847 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
848 [PWRAP_GPSINF_0_STA] = 0x1EC,
849 [PWRAP_GPSINF_1_STA] = 0x1F0,
850 [PWRAP_WACS2_CMD] = 0xC20,
851 [PWRAP_WACS2_RDATA] = 0xC24,
852 [PWRAP_WACS2_VLDCLR] = 0xC28,
853 };
854
855 enum pmic_type {
856 PMIC_MT6323,
857 PMIC_MT6351,
858 PMIC_MT6357,
859 PMIC_MT6358,
860 PMIC_MT6380,
861 PMIC_MT6397,
862 };
863
864 enum pwrap_type {
865 PWRAP_MT2701,
866 PWRAP_MT6765,
867 PWRAP_MT6797,
868 PWRAP_MT7622,
869 PWRAP_MT8135,
870 PWRAP_MT8173,
871 PWRAP_MT8183,
872 };
873
874 struct pmic_wrapper;
875 struct pwrap_slv_type {
876 const u32 *dew_regs;
877 enum pmic_type type;
878 const struct regmap_config *regmap;
879 /* Flags indicating the capability for the target slave */
880 u32 caps;
881 /*
882 * pwrap operations are highly associated with the PMIC types,
883 * so the pointers added increases flexibility allowing determination
884 * which type is used by the detection through device tree.
885 */
886 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
887 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
888 };
889
890 struct pmic_wrapper {
891 struct device *dev;
892 void __iomem *base;
893 struct regmap *regmap;
894 const struct pmic_wrapper_type *master;
895 const struct pwrap_slv_type *slave;
896 struct clk *clk_spi;
897 struct clk *clk_wrap;
898 struct reset_control *rstc;
899
900 struct reset_control *rstc_bridge;
901 void __iomem *bridge_base;
902 };
903
904 struct pmic_wrapper_type {
905 int *regs;
906 enum pwrap_type type;
907 u32 arb_en_all;
908 u32 int_en_all;
909 u32 int1_en_all;
910 u32 spi_w;
911 u32 wdt_src;
912 /* Flags indicating the capability for the target pwrap */
913 u32 caps;
914 int (*init_reg_clock)(struct pmic_wrapper *wrp);
915 int (*init_soc_specific)(struct pmic_wrapper *wrp);
916 };
917
918 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
919 {
920 return readl(wrp->base + wrp->master->regs[reg]);
921 }
922
923 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
924 {
925 writel(val, wrp->base + wrp->master->regs[reg]);
926 }
927
928 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
929 {
930 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
931
932 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
933 }
934
935 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
936 {
937 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
938
939 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
940 }
941
942 /*
943 * Timeout issue sometimes caused by the last read command
944 * failed because pmic wrap could not got the FSM_VLDCLR
945 * in time after finishing WACS2_CMD. It made state machine
946 * still on FSM_VLDCLR and timeout next time.
947 * Check the status of FSM and clear the vldclr to recovery the
948 * error.
949 */
950 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
951 {
952 if (pwrap_is_fsm_vldclr(wrp))
953 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
954 }
955
956 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
957 {
958 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
959 }
960
961 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
962 {
963 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
964
965 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
966 (val & PWRAP_STATE_SYNC_IDLE0);
967 }
968
969 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
970 bool (*fp)(struct pmic_wrapper *))
971 {
972 unsigned long timeout;
973
974 timeout = jiffies + usecs_to_jiffies(10000);
975
976 do {
977 if (time_after(jiffies, timeout))
978 return fp(wrp) ? 0 : -ETIMEDOUT;
979 if (fp(wrp))
980 return 0;
981 } while (1);
982 }
983
984 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
985 {
986 int ret;
987
988 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
989 if (ret) {
990 pwrap_leave_fsm_vldclr(wrp);
991 return ret;
992 }
993
994 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
995
996 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
997 if (ret)
998 return ret;
999
1000 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
1001
1002 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1003
1004 return 0;
1005 }
1006
1007 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1008 {
1009 int ret, msb;
1010
1011 *rdata = 0;
1012 for (msb = 0; msb < 2; msb++) {
1013 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1014 if (ret) {
1015 pwrap_leave_fsm_vldclr(wrp);
1016 return ret;
1017 }
1018
1019 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1020 PWRAP_WACS2_CMD);
1021
1022 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1023 if (ret)
1024 return ret;
1025
1026 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1027 PWRAP_WACS2_RDATA)) << (16 * msb));
1028
1029 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1030 }
1031
1032 return 0;
1033 }
1034
1035 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1036 {
1037 return wrp->slave->pwrap_read(wrp, adr, rdata);
1038 }
1039
1040 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1041 {
1042 int ret;
1043
1044 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1045 if (ret) {
1046 pwrap_leave_fsm_vldclr(wrp);
1047 return ret;
1048 }
1049
1050 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1051 PWRAP_WACS2_CMD);
1052
1053 return 0;
1054 }
1055
1056 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1057 {
1058 int ret, msb, rdata;
1059
1060 for (msb = 0; msb < 2; msb++) {
1061 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1062 if (ret) {
1063 pwrap_leave_fsm_vldclr(wrp);
1064 return ret;
1065 }
1066
1067 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1068 ((wdata >> (msb * 16)) & 0xffff),
1069 PWRAP_WACS2_CMD);
1070
1071 /*
1072 * The pwrap_read operation is the requirement of hardware used
1073 * for the synchronization between two successive 16-bit
1074 * pwrap_writel operations composing one 32-bit bus writing.
1075 * Otherwise, we'll find the result fails on the lower 16-bit
1076 * pwrap writing.
1077 */
1078 if (!msb)
1079 pwrap_read(wrp, adr, &rdata);
1080 }
1081
1082 return 0;
1083 }
1084
1085 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1086 {
1087 return wrp->slave->pwrap_write(wrp, adr, wdata);
1088 }
1089
1090 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1091 {
1092 return pwrap_read(context, adr, rdata);
1093 }
1094
1095 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1096 {
1097 return pwrap_write(context, adr, wdata);
1098 }
1099
1100 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1101 {
1102 int ret, i;
1103
1104 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1105 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1106 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1107 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1108 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1109
1110 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1111 PWRAP_MAN_CMD);
1112 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1113 PWRAP_MAN_CMD);
1114 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1115 PWRAP_MAN_CMD);
1116
1117 for (i = 0; i < 4; i++)
1118 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1119 PWRAP_MAN_CMD);
1120
1121 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1122 if (ret) {
1123 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1124 return ret;
1125 }
1126
1127 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1128 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1129
1130 return 0;
1131 }
1132
1133 /*
1134 * pwrap_init_sidly - configure serial input delay
1135 *
1136 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1137 * delay. Do a read test with all possible values and chose the best delay.
1138 */
1139 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1140 {
1141 u32 rdata;
1142 u32 i;
1143 u32 pass = 0;
1144 signed char dly[16] = {
1145 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1146 };
1147
1148 for (i = 0; i < 4; i++) {
1149 pwrap_writel(wrp, i, PWRAP_SIDLY);
1150 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1151 &rdata);
1152 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1153 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1154 pass |= 1 << i;
1155 }
1156 }
1157
1158 if (dly[pass] < 0) {
1159 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1160 pass);
1161 return -EIO;
1162 }
1163
1164 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1165
1166 return 0;
1167 }
1168
1169 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1170 {
1171 int ret;
1172 u32 rdata;
1173
1174 /* Enable dual IO mode */
1175 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1176
1177 /* Check IDLE & INIT_DONE in advance */
1178 ret = pwrap_wait_for_state(wrp,
1179 pwrap_is_fsm_idle_and_sync_idle);
1180 if (ret) {
1181 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1182 return ret;
1183 }
1184
1185 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1186
1187 /* Read Test */
1188 pwrap_read(wrp,
1189 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1190 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1191 dev_err(wrp->dev,
1192 "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1193 PWRAP_DEW_READ_TEST_VAL, rdata);
1194 return -EFAULT;
1195 }
1196
1197 return 0;
1198 }
1199
1200 /*
1201 * pwrap_init_chip_select_ext is used to configure CS extension time for each
1202 * phase during data transactions on the pwrap bus.
1203 */
1204 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1205 u8 hext_read, u8 lext_start,
1206 u8 lext_end)
1207 {
1208 /*
1209 * After finishing a write and read transaction, extends CS high time
1210 * to be at least xT of BUS CLK as hext_write and hext_read specifies
1211 * respectively.
1212 */
1213 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1214 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1215
1216 /*
1217 * Extends CS low time after CSL and before CSH command to be at
1218 * least xT of BUS CLK as lext_start and lext_end specifies
1219 * respectively.
1220 */
1221 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1222 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1223 }
1224
1225 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1226 {
1227 switch (wrp->master->type) {
1228 case PWRAP_MT8173:
1229 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1230 break;
1231 case PWRAP_MT8135:
1232 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1233 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1234 break;
1235 default:
1236 break;
1237 }
1238
1239 return 0;
1240 }
1241
1242 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1243 {
1244 switch (wrp->slave->type) {
1245 case PMIC_MT6397:
1246 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1247 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1248 break;
1249
1250 case PMIC_MT6323:
1251 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1252 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1253 0x8);
1254 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1255 break;
1256 default:
1257 break;
1258 }
1259
1260 return 0;
1261 }
1262
1263 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1264 {
1265 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1266 }
1267
1268 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1269 {
1270 u32 rdata;
1271 int ret;
1272
1273 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1274 &rdata);
1275 if (ret)
1276 return false;
1277
1278 return rdata == 1;
1279 }
1280
1281 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1282 {
1283 int ret;
1284 u32 rdata;
1285
1286 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1287 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1288 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1289 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1290
1291 switch (wrp->master->type) {
1292 case PWRAP_MT8135:
1293 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1294 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1295 break;
1296 case PWRAP_MT2701:
1297 case PWRAP_MT6765:
1298 case PWRAP_MT6797:
1299 case PWRAP_MT8173:
1300 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1301 break;
1302 case PWRAP_MT7622:
1303 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1304 break;
1305 case PWRAP_MT8183:
1306 break;
1307 }
1308
1309 /* Config cipher mode @PMIC */
1310 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1311 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1312 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1313 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1314
1315 switch (wrp->slave->type) {
1316 case PMIC_MT6397:
1317 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1318 0x1);
1319 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1320 0x1);
1321 break;
1322 case PMIC_MT6323:
1323 case PMIC_MT6351:
1324 case PMIC_MT6357:
1325 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1326 0x1);
1327 break;
1328 default:
1329 break;
1330 }
1331
1332 /* wait for cipher data ready@AP */
1333 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1334 if (ret) {
1335 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1336 return ret;
1337 }
1338
1339 /* wait for cipher data ready@PMIC */
1340 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1341 if (ret) {
1342 dev_err(wrp->dev,
1343 "timeout waiting for cipher data ready@PMIC\n");
1344 return ret;
1345 }
1346
1347 /* wait for cipher mode idle */
1348 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1349 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1350 if (ret) {
1351 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1352 return ret;
1353 }
1354
1355 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1356
1357 /* Write Test */
1358 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1359 PWRAP_DEW_WRITE_TEST_VAL) ||
1360 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1361 &rdata) ||
1362 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1363 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1364 return -EFAULT;
1365 }
1366
1367 return 0;
1368 }
1369
1370 static int pwrap_init_security(struct pmic_wrapper *wrp)
1371 {
1372 int ret;
1373
1374 /* Enable encryption */
1375 ret = pwrap_init_cipher(wrp);
1376 if (ret)
1377 return ret;
1378
1379 /* Signature checking - using CRC */
1380 if (pwrap_write(wrp,
1381 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1382 return -EFAULT;
1383
1384 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1385 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1386 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1387 PWRAP_SIG_ADR);
1388 pwrap_writel(wrp,
1389 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1390
1391 return 0;
1392 }
1393
1394 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1395 {
1396 /* enable pwrap events and pwrap bridge in AP side */
1397 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1398 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1399 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1400 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1401 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1402 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1403 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1404 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1405 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1406
1407 /* enable PMIC event out and sources */
1408 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1409 0x1) ||
1410 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1411 0xffff)) {
1412 dev_err(wrp->dev, "enable dewrap fail\n");
1413 return -EFAULT;
1414 }
1415
1416 return 0;
1417 }
1418
1419 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1420 {
1421 /* PMIC_DEWRAP enables */
1422 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1423 0x1) ||
1424 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1425 0xffff)) {
1426 dev_err(wrp->dev, "enable dewrap fail\n");
1427 return -EFAULT;
1428 }
1429
1430 return 0;
1431 }
1432
1433 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1434 {
1435 /* GPS_INTF initialization */
1436 switch (wrp->slave->type) {
1437 case PMIC_MT6323:
1438 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1439 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1440 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1441 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1442 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1443 break;
1444 default:
1445 break;
1446 }
1447
1448 return 0;
1449 }
1450
1451 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1452 {
1453 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1454 /* enable 2wire SPI master */
1455 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1456
1457 return 0;
1458 }
1459
1460 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1461 {
1462 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1463
1464 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1465 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1466 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1467 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1468
1469 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1470 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1471 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1472 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1473
1474 return 0;
1475 }
1476
1477 static int pwrap_init(struct pmic_wrapper *wrp)
1478 {
1479 int ret;
1480
1481 reset_control_reset(wrp->rstc);
1482 if (wrp->rstc_bridge)
1483 reset_control_reset(wrp->rstc_bridge);
1484
1485 if (wrp->master->type == PWRAP_MT8173) {
1486 /* Enable DCM */
1487 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1488 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1489 }
1490
1491 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1492 /* Reset SPI slave */
1493 ret = pwrap_reset_spislave(wrp);
1494 if (ret)
1495 return ret;
1496 }
1497
1498 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1499
1500 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1501
1502 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1503
1504 ret = wrp->master->init_reg_clock(wrp);
1505 if (ret)
1506 return ret;
1507
1508 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1509 /* Setup serial input delay */
1510 ret = pwrap_init_sidly(wrp);
1511 if (ret)
1512 return ret;
1513 }
1514
1515 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1516 /* Enable dual I/O mode */
1517 ret = pwrap_init_dual_io(wrp);
1518 if (ret)
1519 return ret;
1520 }
1521
1522 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1523 /* Enable security on bus */
1524 ret = pwrap_init_security(wrp);
1525 if (ret)
1526 return ret;
1527 }
1528
1529 if (wrp->master->type == PWRAP_MT8135)
1530 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1531
1532 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1533 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1534 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1535 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1536 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1537
1538 if (wrp->master->init_soc_specific) {
1539 ret = wrp->master->init_soc_specific(wrp);
1540 if (ret)
1541 return ret;
1542 }
1543
1544 /* Setup the init done registers */
1545 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1546 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1547 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1548
1549 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1550 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1551 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1552 }
1553
1554 return 0;
1555 }
1556
1557 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1558 {
1559 u32 rdata;
1560 struct pmic_wrapper *wrp = dev_id;
1561
1562 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1563 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1564 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1565
1566 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1567 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1568 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1569 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1570 }
1571
1572 return IRQ_HANDLED;
1573 }
1574
1575 static const struct regmap_config pwrap_regmap_config16 = {
1576 .reg_bits = 16,
1577 .val_bits = 16,
1578 .reg_stride = 2,
1579 .reg_read = pwrap_regmap_read,
1580 .reg_write = pwrap_regmap_write,
1581 .max_register = 0xffff,
1582 };
1583
1584 static const struct regmap_config pwrap_regmap_config32 = {
1585 .reg_bits = 32,
1586 .val_bits = 32,
1587 .reg_stride = 4,
1588 .reg_read = pwrap_regmap_read,
1589 .reg_write = pwrap_regmap_write,
1590 .max_register = 0xffff,
1591 };
1592
1593 static const struct pwrap_slv_type pmic_mt6323 = {
1594 .dew_regs = mt6323_regs,
1595 .type = PMIC_MT6323,
1596 .regmap = &pwrap_regmap_config16,
1597 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1598 PWRAP_SLV_CAP_SECURITY,
1599 .pwrap_read = pwrap_read16,
1600 .pwrap_write = pwrap_write16,
1601 };
1602
1603 static const struct pwrap_slv_type pmic_mt6351 = {
1604 .dew_regs = mt6351_regs,
1605 .type = PMIC_MT6351,
1606 .regmap = &pwrap_regmap_config16,
1607 .caps = 0,
1608 .pwrap_read = pwrap_read16,
1609 .pwrap_write = pwrap_write16,
1610 };
1611
1612 static const struct pwrap_slv_type pmic_mt6357 = {
1613 .dew_regs = mt6357_regs,
1614 .type = PMIC_MT6357,
1615 .regmap = &pwrap_regmap_config16,
1616 .caps = 0,
1617 .pwrap_read = pwrap_read16,
1618 .pwrap_write = pwrap_write16,
1619 };
1620
1621 static const struct pwrap_slv_type pmic_mt6358 = {
1622 .dew_regs = mt6358_regs,
1623 .type = PMIC_MT6358,
1624 .regmap = &pwrap_regmap_config16,
1625 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1626 .pwrap_read = pwrap_read16,
1627 .pwrap_write = pwrap_write16,
1628 };
1629
1630 static const struct pwrap_slv_type pmic_mt6380 = {
1631 .dew_regs = NULL,
1632 .type = PMIC_MT6380,
1633 .regmap = &pwrap_regmap_config32,
1634 .caps = 0,
1635 .pwrap_read = pwrap_read32,
1636 .pwrap_write = pwrap_write32,
1637 };
1638
1639 static const struct pwrap_slv_type pmic_mt6397 = {
1640 .dew_regs = mt6397_regs,
1641 .type = PMIC_MT6397,
1642 .regmap = &pwrap_regmap_config16,
1643 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1644 PWRAP_SLV_CAP_SECURITY,
1645 .pwrap_read = pwrap_read16,
1646 .pwrap_write = pwrap_write16,
1647 };
1648
1649 static const struct of_device_id of_slave_match_tbl[] = {
1650 {
1651 .compatible = "mediatek,mt6323",
1652 .data = &pmic_mt6323,
1653 }, {
1654 .compatible = "mediatek,mt6351",
1655 .data = &pmic_mt6351,
1656 }, {
1657 .compatible = "mediatek,mt6357",
1658 .data = &pmic_mt6357,
1659 }, {
1660 .compatible = "mediatek,mt6358",
1661 .data = &pmic_mt6358,
1662 }, {
1663 /* The MT6380 PMIC only implements a regulator, so we bind it
1664 * directly instead of using a MFD.
1665 */
1666 .compatible = "mediatek,mt6380-regulator",
1667 .data = &pmic_mt6380,
1668 }, {
1669 .compatible = "mediatek,mt6397",
1670 .data = &pmic_mt6397,
1671 }, {
1672 /* sentinel */
1673 }
1674 };
1675 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1676
1677 static const struct pmic_wrapper_type pwrap_mt2701 = {
1678 .regs = mt2701_regs,
1679 .type = PWRAP_MT2701,
1680 .arb_en_all = 0x3f,
1681 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1682 .int1_en_all = 0,
1683 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1684 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1685 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1686 .init_reg_clock = pwrap_mt2701_init_reg_clock,
1687 .init_soc_specific = pwrap_mt2701_init_soc_specific,
1688 };
1689
1690 static const struct pmic_wrapper_type pwrap_mt6765 = {
1691 .regs = mt6765_regs,
1692 .type = PWRAP_MT6765,
1693 .arb_en_all = 0x3fd35,
1694 .int_en_all = 0xffffffff,
1695 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1696 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1697 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1698 .init_reg_clock = pwrap_common_init_reg_clock,
1699 .init_soc_specific = NULL,
1700 };
1701
1702 static const struct pmic_wrapper_type pwrap_mt6797 = {
1703 .regs = mt6797_regs,
1704 .type = PWRAP_MT6797,
1705 .arb_en_all = 0x01fff,
1706 .int_en_all = 0xffffffc6,
1707 .int1_en_all = 0,
1708 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1709 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1710 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1711 .init_reg_clock = pwrap_common_init_reg_clock,
1712 .init_soc_specific = NULL,
1713 };
1714
1715 static const struct pmic_wrapper_type pwrap_mt7622 = {
1716 .regs = mt7622_regs,
1717 .type = PWRAP_MT7622,
1718 .arb_en_all = 0xff,
1719 .int_en_all = ~(u32)BIT(31),
1720 .int1_en_all = 0,
1721 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1722 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1723 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1724 .init_reg_clock = pwrap_common_init_reg_clock,
1725 .init_soc_specific = pwrap_mt7622_init_soc_specific,
1726 };
1727
1728 static const struct pmic_wrapper_type pwrap_mt8135 = {
1729 .regs = mt8135_regs,
1730 .type = PWRAP_MT8135,
1731 .arb_en_all = 0x1ff,
1732 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1733 .int1_en_all = 0,
1734 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1735 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1736 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1737 .init_reg_clock = pwrap_common_init_reg_clock,
1738 .init_soc_specific = pwrap_mt8135_init_soc_specific,
1739 };
1740
1741 static const struct pmic_wrapper_type pwrap_mt8173 = {
1742 .regs = mt8173_regs,
1743 .type = PWRAP_MT8173,
1744 .arb_en_all = 0x3f,
1745 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1746 .int1_en_all = 0,
1747 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1748 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1749 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1750 .init_reg_clock = pwrap_common_init_reg_clock,
1751 .init_soc_specific = pwrap_mt8173_init_soc_specific,
1752 };
1753
1754 static const struct pmic_wrapper_type pwrap_mt8183 = {
1755 .regs = mt8183_regs,
1756 .type = PWRAP_MT8183,
1757 .arb_en_all = 0x3fa75,
1758 .int_en_all = 0xffffffff,
1759 .int1_en_all = 0xeef7ffff,
1760 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1761 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1762 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
1763 .init_reg_clock = pwrap_common_init_reg_clock,
1764 .init_soc_specific = pwrap_mt8183_init_soc_specific,
1765 };
1766
1767 static const struct of_device_id of_pwrap_match_tbl[] = {
1768 {
1769 .compatible = "mediatek,mt2701-pwrap",
1770 .data = &pwrap_mt2701,
1771 }, {
1772 .compatible = "mediatek,mt6765-pwrap",
1773 .data = &pwrap_mt6765,
1774 }, {
1775 .compatible = "mediatek,mt6797-pwrap",
1776 .data = &pwrap_mt6797,
1777 }, {
1778 .compatible = "mediatek,mt7622-pwrap",
1779 .data = &pwrap_mt7622,
1780 }, {
1781 .compatible = "mediatek,mt8135-pwrap",
1782 .data = &pwrap_mt8135,
1783 }, {
1784 .compatible = "mediatek,mt8173-pwrap",
1785 .data = &pwrap_mt8173,
1786 }, {
1787 .compatible = "mediatek,mt8183-pwrap",
1788 .data = &pwrap_mt8183,
1789 }, {
1790 /* sentinel */
1791 }
1792 };
1793 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
1794
1795 static int pwrap_probe(struct platform_device *pdev)
1796 {
1797 int ret, irq;
1798 struct pmic_wrapper *wrp;
1799 struct device_node *np = pdev->dev.of_node;
1800 const struct of_device_id *of_slave_id = NULL;
1801 struct resource *res;
1802
1803 if (np->child)
1804 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
1805
1806 if (!of_slave_id) {
1807 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
1808 return -EINVAL;
1809 }
1810
1811 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
1812 if (!wrp)
1813 return -ENOMEM;
1814
1815 platform_set_drvdata(pdev, wrp);
1816
1817 wrp->master = of_device_get_match_data(&pdev->dev);
1818 wrp->slave = of_slave_id->data;
1819 wrp->dev = &pdev->dev;
1820
1821 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
1822 wrp->base = devm_ioremap_resource(wrp->dev, res);
1823 if (IS_ERR(wrp->base))
1824 return PTR_ERR(wrp->base);
1825
1826 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
1827 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
1828 if (IS_ERR(wrp->rstc)) {
1829 ret = PTR_ERR(wrp->rstc);
1830 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
1831 return ret;
1832 }
1833 }
1834
1835 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1836 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1837 "pwrap-bridge");
1838 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
1839 if (IS_ERR(wrp->bridge_base))
1840 return PTR_ERR(wrp->bridge_base);
1841
1842 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
1843 "pwrap-bridge");
1844 if (IS_ERR(wrp->rstc_bridge)) {
1845 ret = PTR_ERR(wrp->rstc_bridge);
1846 dev_dbg(wrp->dev,
1847 "cannot get pwrap-bridge reset: %d\n", ret);
1848 return ret;
1849 }
1850 }
1851
1852 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
1853 if (IS_ERR(wrp->clk_spi)) {
1854 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1855 PTR_ERR(wrp->clk_spi));
1856 return PTR_ERR(wrp->clk_spi);
1857 }
1858
1859 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
1860 if (IS_ERR(wrp->clk_wrap)) {
1861 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1862 PTR_ERR(wrp->clk_wrap));
1863 return PTR_ERR(wrp->clk_wrap);
1864 }
1865
1866 ret = clk_prepare_enable(wrp->clk_spi);
1867 if (ret)
1868 return ret;
1869
1870 ret = clk_prepare_enable(wrp->clk_wrap);
1871 if (ret)
1872 goto err_out1;
1873
1874 /* Enable internal dynamic clock */
1875 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
1876 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1877 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1878 }
1879
1880 /*
1881 * The PMIC could already be initialized by the bootloader.
1882 * Skip initialization here in this case.
1883 */
1884 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
1885 ret = pwrap_init(wrp);
1886 if (ret) {
1887 dev_dbg(wrp->dev, "init failed with %d\n", ret);
1888 goto err_out2;
1889 }
1890 }
1891
1892 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
1893 dev_dbg(wrp->dev, "initialization isn't finished\n");
1894 ret = -ENODEV;
1895 goto err_out2;
1896 }
1897
1898 /* Initialize watchdog, may not be done by the bootloader */
1899 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
1900 /*
1901 * Since STAUPD was not used on mt8173 platform,
1902 * so STAUPD of WDT_SRC which should be turned off
1903 */
1904 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
1905 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
1906 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
1907
1908 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
1909 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
1910 /*
1911 * We add INT1 interrupt to handle starvation and request exception
1912 * If we support it, we should enable it here.
1913 */
1914 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
1915 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
1916
1917 irq = platform_get_irq(pdev, 0);
1918 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
1919 IRQF_TRIGGER_HIGH,
1920 "mt-pmic-pwrap", wrp);
1921 if (ret)
1922 goto err_out2;
1923
1924 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
1925 if (IS_ERR(wrp->regmap)) {
1926 ret = PTR_ERR(wrp->regmap);
1927 goto err_out2;
1928 }
1929
1930 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
1931 if (ret) {
1932 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
1933 np);
1934 goto err_out2;
1935 }
1936
1937 return 0;
1938
1939 err_out2:
1940 clk_disable_unprepare(wrp->clk_wrap);
1941 err_out1:
1942 clk_disable_unprepare(wrp->clk_spi);
1943
1944 return ret;
1945 }
1946
1947 static struct platform_driver pwrap_drv = {
1948 .driver = {
1949 .name = "mt-pmic-pwrap",
1950 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
1951 },
1952 .probe = pwrap_probe,
1953 };
1954
1955 module_platform_driver(pwrap_drv);
1956
1957 MODULE_AUTHOR("Flora Fu, MediaTek");
1958 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
1959 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support