drivers/soc/qcom/qcom-geni-se.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/slab.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/io.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_platform.h>
  11 #include <linux/pinctrl/consumer.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/qcom-geni-se.h>
  14
  15 /**
  16  * DOC: Overview
  17  *
  18  * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
  19  * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
  20  * controller. QUP Wrapper is designed to support various serial bus protocols
  21  * like UART, SPI, I2C, I3C, etc.
  22  */
  23
  24 /**
  25  * DOC: Hardware description
  26  *
  27  * GENI based QUP is a highly-flexible and programmable module for supporting
  28  * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
  29  * QUP module can provide upto 8 serial interfaces, using its internal
  30  * serial engines. The actual configuration is determined by the target
  31  * platform configuration. The protocol supported by each interface is
  32  * determined by the firmware loaded to the serial engine. Each SE consists
  33  * of a DMA Engine and GENI sub modules which enable serial engines to
  34  * support FIFO and DMA modes of operation.
  35  *
  36  *
  37  *                      +-----------------------------------------+
  38  *                      |QUP Wrapper                              |
  39  *                      |         +----------------------------+  |
  40  *   --QUP & SE Clocks-->         | Serial Engine N            |  +-IO------>
  41  *                      |         | ...                        |  | Interface
  42  *   <---Clock Perf.----+    +----+-----------------------+    |  |
  43  *     State Interface  |    | Serial Engine 1            |    |  |
  44  *                      |    |                            |    |  |
  45  *                      |    |                            |    |  |
  46  *   <--------AHB------->    |                            |    |  |
  47  *                      |    |                            +----+  |
  48  *                      |    |                            |       |
  49  *                      |    |                            |       |
  50  *   <------SE IRQ------+    +----------------------------+       |
  51  *                      |                                         |
  52  *                      +-----------------------------------------+
  53  *
  54  *                         Figure 1: GENI based QUP Wrapper
  55  *
  56  * The GENI submodules include primary and secondary sequencers which are
  57  * used to drive TX & RX operations. On serial interfaces that operate using
  58  * master-slave model, primary sequencer drives both TX & RX operations. On
  59  * serial interfaces that operate using peer-to-peer model, primary sequencer
  60  * drives TX operation and secondary sequencer drives RX operation.
  61  */
  62
  63 /**
  64  * DOC: Software description
  65  *
  66  * GENI SE Wrapper driver is structured into 2 parts:
  67  *
  68  * geni_wrapper represents QUP Wrapper controller. This part of the driver
  69  * manages QUP Wrapper information such as hardware version, clock
  70  * performance table that is common to all the internal serial engines.
  71  *
  72  * geni_se represents serial engine. This part of the driver manages serial
  73  * engine information such as clocks, containing QUP Wrapper, etc. This part
  74  * of driver also supports operations (eg. initialize the concerned serial
  75  * engine, select between FIFO and DMA mode of operation etc.) that are
  76  * common to all the serial engines and are independent of serial interfaces.
  77  */
  78
  79 #define MAX_CLK_PERF_LEVEL 32
  80 #define NUM_AHB_CLKS 2
  81
  82 /**
  83  * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
  84  * @dev:                Device pointer of the QUP wrapper core
  85  * @base:               Base address of this instance of QUP wrapper core
  86  * @ahb_clks:           Handle to the primary & secondary AHB clocks
  87  */
  88 struct geni_wrapper {
  89         struct device *dev;
  90         void __iomem *base;
  91         struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
  92 };
  93
  94 #define QUP_HW_VER_REG                  0x4
  95
  96 /* Common SE registers */
  97 #define GENI_INIT_CFG_REVISION          0x0
  98 #define GENI_S_INIT_CFG_REVISION        0x4
  99 #define GENI_OUTPUT_CTRL                0x24
 100 #define GENI_CGC_CTRL                   0x28
 101 #define GENI_CLK_CTRL_RO                0x60
 102 #define GENI_IF_DISABLE_RO              0x64
 103 #define GENI_FW_S_REVISION_RO           0x6c
 104 #define SE_GENI_BYTE_GRAN               0x254
 105 #define SE_GENI_TX_PACKING_CFG0         0x260
 106 #define SE_GENI_TX_PACKING_CFG1         0x264
 107 #define SE_GENI_RX_PACKING_CFG0         0x284
 108 #define SE_GENI_RX_PACKING_CFG1         0x288
 109 #define SE_GENI_M_GP_LENGTH             0x910
 110 #define SE_GENI_S_GP_LENGTH             0x914
 111 #define SE_DMA_TX_PTR_L                 0xc30
 112 #define SE_DMA_TX_PTR_H                 0xc34
 113 #define SE_DMA_TX_ATTR                  0xc38
 114 #define SE_DMA_TX_LEN                   0xc3c
 115 #define SE_DMA_TX_IRQ_EN                0xc48
 116 #define SE_DMA_TX_IRQ_EN_SET            0xc4c
 117 #define SE_DMA_TX_IRQ_EN_CLR            0xc50
 118 #define SE_DMA_TX_LEN_IN                0xc54
 119 #define SE_DMA_TX_MAX_BURST             0xc5c
 120 #define SE_DMA_RX_PTR_L                 0xd30
 121 #define SE_DMA_RX_PTR_H                 0xd34
 122 #define SE_DMA_RX_ATTR                  0xd38
 123 #define SE_DMA_RX_LEN                   0xd3c
 124 #define SE_DMA_RX_IRQ_EN                0xd48
 125 #define SE_DMA_RX_IRQ_EN_SET            0xd4c
 126 #define SE_DMA_RX_IRQ_EN_CLR            0xd50
 127 #define SE_DMA_RX_LEN_IN                0xd54
 128 #define SE_DMA_RX_MAX_BURST             0xd5c
 129 #define SE_DMA_RX_FLUSH                 0xd60
 130 #define SE_GSI_EVENT_EN                 0xe18
 131 #define SE_IRQ_EN                       0xe1c
 132 #define SE_DMA_GENERAL_CFG              0xe30
 133
 134 /* GENI_OUTPUT_CTRL fields */
 135 #define DEFAULT_IO_OUTPUT_CTRL_MSK      GENMASK(6, 0)
 136
 137 /* GENI_CGC_CTRL fields */
 138 #define CFG_AHB_CLK_CGC_ON              BIT(0)
 139 #define CFG_AHB_WR_ACLK_CGC_ON          BIT(1)
 140 #define DATA_AHB_CLK_CGC_ON             BIT(2)
 141 #define SCLK_CGC_ON                     BIT(3)
 142 #define TX_CLK_CGC_ON                   BIT(4)
 143 #define RX_CLK_CGC_ON                   BIT(5)
 144 #define EXT_CLK_CGC_ON                  BIT(6)
 145 #define PROG_RAM_HCLK_OFF               BIT(8)
 146 #define PROG_RAM_SCLK_OFF               BIT(9)
 147 #define DEFAULT_CGC_EN                  GENMASK(6, 0)
 148
 149 /* SE_GSI_EVENT_EN fields */
 150 #define DMA_RX_EVENT_EN                 BIT(0)
 151 #define DMA_TX_EVENT_EN                 BIT(1)
 152 #define GENI_M_EVENT_EN                 BIT(2)
 153 #define GENI_S_EVENT_EN                 BIT(3)
 154
 155 /* SE_IRQ_EN fields */
 156 #define DMA_RX_IRQ_EN                   BIT(0)
 157 #define DMA_TX_IRQ_EN                   BIT(1)
 158 #define GENI_M_IRQ_EN                   BIT(2)
 159 #define GENI_S_IRQ_EN                   BIT(3)
 160
 161 /* SE_DMA_GENERAL_CFG */
 162 #define DMA_RX_CLK_CGC_ON               BIT(0)
 163 #define DMA_TX_CLK_CGC_ON               BIT(1)
 164 #define DMA_AHB_SLV_CFG_ON              BIT(2)
 165 #define AHB_SEC_SLV_CLK_CGC_ON          BIT(3)
 166 #define DUMMY_RX_NON_BUFFERABLE         BIT(4)
 167 #define RX_DMA_ZERO_PADDING_EN          BIT(5)
 168 #define RX_DMA_IRQ_DELAY_MSK            GENMASK(8, 6)
 169 #define RX_DMA_IRQ_DELAY_SHFT           6
 170
 171 /**
 172  * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
 173  * @se: Pointer to the corresponding serial engine.
 174  *
 175  * Return: Hardware Version of the wrapper.
 176  */
 177 u32 geni_se_get_qup_hw_version(struct geni_se *se)
 178 {
 179         struct geni_wrapper *wrapper = se->wrapper;
 180
 181         return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
 182 }
 183 EXPORT_SYMBOL(geni_se_get_qup_hw_version);
 184
 185 static void geni_se_io_set_mode(void __iomem *base)
 186 {
 187         u32 val;
 188
 189         val = readl_relaxed(base + SE_IRQ_EN);
 190         val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
 191         val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
 192         writel_relaxed(val, base + SE_IRQ_EN);
 193
 194         val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
 195         val &= ~GENI_DMA_MODE_EN;
 196         writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
 197
 198         writel_relaxed(0, base + SE_GSI_EVENT_EN);
 199 }
 200
 201 static void geni_se_io_init(void __iomem *base)
 202 {
 203         u32 val;
 204
 205         val = readl_relaxed(base + GENI_CGC_CTRL);
 206         val |= DEFAULT_CGC_EN;
 207         writel_relaxed(val, base + GENI_CGC_CTRL);
 208
 209         val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
 210         val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
 211         val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
 212         writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
 213
 214         writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
 215         writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
 216 }
 217
 218 static void geni_se_irq_clear(struct geni_se *se)
 219 {
 220         writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
 221         writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
 222         writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
 223         writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
 224         writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
 225         writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
 226 }
 227
 228 /**
 229  * geni_se_init() - Initialize the GENI serial engine
 230  * @se:         Pointer to the concerned serial engine.
 231  * @rx_wm:      Receive watermark, in units of FIFO words.
 232  * @rx_rfr_wm:  Ready-for-receive watermark, in units of FIFO words.
 233  *
 234  * This function is used to initialize the GENI serial engine, configure
 235  * receive watermark and ready-for-receive watermarks.
 236  */
 237 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
 238 {
 239         u32 val;
 240
 241         geni_se_irq_clear(se);
 242         geni_se_io_init(se->base);
 243         geni_se_io_set_mode(se->base);
 244
 245         writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
 246         writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
 247
 248         val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
 249         val |= M_COMMON_GENI_M_IRQ_EN;
 250         writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
 251
 252         val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
 253         val |= S_COMMON_GENI_S_IRQ_EN;
 254         writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
 255 }
 256 EXPORT_SYMBOL(geni_se_init);
 257
 258 static void geni_se_select_fifo_mode(struct geni_se *se)
 259 {
 260         u32 proto = geni_se_read_proto(se);
 261         u32 val;
 262
 263         geni_se_irq_clear(se);
 264
 265         val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
 266         if (proto != GENI_SE_UART) {
 267                 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
 268                 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 269         }
 270         writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
 271
 272         val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
 273         if (proto != GENI_SE_UART)
 274                 val |= S_CMD_DONE_EN;
 275         writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
 276
 277         val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
 278         val &= ~GENI_DMA_MODE_EN;
 279         writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
 280 }
 281
 282 static void geni_se_select_dma_mode(struct geni_se *se)
 283 {
 284         u32 val;
 285
 286         geni_se_irq_clear(se);
 287
 288         val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
 289         val |= GENI_DMA_MODE_EN;
 290         writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
 291 }
 292
 293 /**
 294  * geni_se_select_mode() - Select the serial engine transfer mode
 295  * @se:         Pointer to the concerned serial engine.
 296  * @mode:       Transfer mode to be selected.
 297  */
 298 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
 299 {
 300         WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
 301
 302         switch (mode) {
 303         case GENI_SE_FIFO:
 304                 geni_se_select_fifo_mode(se);
 305                 break;
 306         case GENI_SE_DMA:
 307                 geni_se_select_dma_mode(se);
 308                 break;
 309         case GENI_SE_INVALID:
 310         default:
 311                 break;
 312         }
 313 }
 314 EXPORT_SYMBOL(geni_se_select_mode);
 315
 316 /**
 317  * DOC: Overview
 318  *
 319  * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
 320  * of up to 4 operations, each operation represented by 4 configuration vectors
 321  * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
 322  * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
 323  * Refer to below examples for detailed bit-field description.
 324  *
 325  * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
 326  *
 327  *        +-----------+-------+-------+-------+-------+
 328  *        |           | vec_0 | vec_1 | vec_2 | vec_3 |
 329  *        +-----------+-------+-------+-------+-------+
 330  *        | start     | 0x6   | 0xe   | 0x16  | 0x1e  |
 331  *        | direction | 1     | 1     | 1     | 1     |
 332  *        | length    | 6     | 6     | 6     | 6     |
 333  *        | stop      | 0     | 0     | 0     | 1     |
 334  *        +-----------+-------+-------+-------+-------+
 335  *
 336  * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
 337  *
 338  *        +-----------+-------+-------+-------+-------+
 339  *        |           | vec_0 | vec_1 | vec_2 | vec_3 |
 340  *        +-----------+-------+-------+-------+-------+
 341  *        | start     | 0x0   | 0x8   | 0x10  | 0x18  |
 342  *        | direction | 0     | 0     | 0     | 0     |
 343  *        | length    | 7     | 6     | 7     | 6     |
 344  *        | stop      | 0     | 0     | 0     | 1     |
 345  *        +-----------+-------+-------+-------+-------+
 346  *
 347  * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
 348  *
 349  *        +-----------+-------+-------+-------+-------+
 350  *        |           | vec_0 | vec_1 | vec_2 | vec_3 |
 351  *        +-----------+-------+-------+-------+-------+
 352  *        | start     | 0x16  | 0xe   | 0x6   | 0x0   |
 353  *        | direction | 1     | 1     | 1     | 1     |
 354  *        | length    | 7     | 7     | 6     | 0     |
 355  *        | stop      | 0     | 0     | 1     | 0     |
 356  *        +-----------+-------+-------+-------+-------+
 357  *
 358  */
 359
 360 #define NUM_PACKING_VECTORS 4
 361 #define PACKING_START_SHIFT 5
 362 #define PACKING_DIR_SHIFT 4
 363 #define PACKING_LEN_SHIFT 1
 364 #define PACKING_STOP_BIT BIT(0)
 365 #define PACKING_VECTOR_SHIFT 10
 366 /**
 367  * geni_se_config_packing() - Packing configuration of the serial engine
 368  * @se:         Pointer to the concerned serial engine
 369  * @bpw:        Bits of data per transfer word.
 370  * @pack_words: Number of words per fifo element.
 371  * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
 372  * @tx_cfg:     Flag to configure the TX Packing.
 373  * @rx_cfg:     Flag to configure the RX Packing.
 374  *
 375  * This function is used to configure the packing rules for the current
 376  * transfer.
 377  */
 378 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
 379                             bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
 380 {
 381         u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
 382         int len;
 383         int temp_bpw = bpw;
 384         int idx_start = msb_to_lsb ? bpw - 1 : 0;
 385         int idx = idx_start;
 386         int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
 387         int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
 388         int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
 389         int i;
 390
 391         if (iter <= 0 || iter > NUM_PACKING_VECTORS)
 392                 return;
 393
 394         for (i = 0; i < iter; i++) {
 395                 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
 396                 cfg[i] = idx << PACKING_START_SHIFT;
 397                 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
 398                 cfg[i] |= len << PACKING_LEN_SHIFT;
 399
 400                 if (temp_bpw <= BITS_PER_BYTE) {
 401                         idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
 402                         temp_bpw = bpw;
 403                 } else {
 404                         idx = idx + idx_delta;
 405                         temp_bpw = temp_bpw - BITS_PER_BYTE;
 406                 }
 407         }
 408         cfg[iter - 1] |= PACKING_STOP_BIT;
 409         cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
 410         cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
 411
 412         if (tx_cfg) {
 413                 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
 414                 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
 415         }
 416         if (rx_cfg) {
 417                 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
 418                 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
 419         }
 420
 421         /*
 422          * Number of protocol words in each FIFO entry
 423          * 0 - 4x8, four words in each entry, max word size of 8 bits
 424          * 1 - 2x16, two words in each entry, max word size of 16 bits
 425          * 2 - 1x32, one word in each entry, max word size of 32 bits
 426          * 3 - undefined
 427          */
 428         if (pack_words || bpw == 32)
 429                 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
 430 }
 431 EXPORT_SYMBOL(geni_se_config_packing);
 432
 433 static void geni_se_clks_off(struct geni_se *se)
 434 {
 435         struct geni_wrapper *wrapper = se->wrapper;
 436
 437         clk_disable_unprepare(se->clk);
 438         clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
 439                                                 wrapper->ahb_clks);
 440 }
 441
 442 /**
 443  * geni_se_resources_off() - Turn off resources associated with the serial
 444  *                           engine
 445  * @se: Pointer to the concerned serial engine.
 446  *
 447  * Return: 0 on success, standard Linux error codes on failure/error.
 448  */
 449 int geni_se_resources_off(struct geni_se *se)
 450 {
 451         int ret;
 452
 453         ret = pinctrl_pm_select_sleep_state(se->dev);
 454         if (ret)
 455                 return ret;
 456
 457         geni_se_clks_off(se);
 458         return 0;
 459 }
 460 EXPORT_SYMBOL(geni_se_resources_off);
 461
 462 static int geni_se_clks_on(struct geni_se *se)
 463 {
 464         int ret;
 465         struct geni_wrapper *wrapper = se->wrapper;
 466
 467         ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
 468                                                 wrapper->ahb_clks);
 469         if (ret)
 470                 return ret;
 471
 472         ret = clk_prepare_enable(se->clk);
 473         if (ret)
 474                 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
 475                                                         wrapper->ahb_clks);
 476         return ret;
 477 }
 478
 479 /**
 480  * geni_se_resources_on() - Turn on resources associated with the serial
 481  *                          engine
 482  * @se: Pointer to the concerned serial engine.
 483  *
 484  * Return: 0 on success, standard Linux error codes on failure/error.
 485  */
 486 int geni_se_resources_on(struct geni_se *se)
 487 {
 488         int ret;
 489
 490         ret = geni_se_clks_on(se);
 491         if (ret)
 492                 return ret;
 493
 494         ret = pinctrl_pm_select_default_state(se->dev);
 495         if (ret)
 496                 geni_se_clks_off(se);
 497
 498         return ret;
 499 }
 500 EXPORT_SYMBOL(geni_se_resources_on);
 501
 502 /**
 503  * geni_se_clk_tbl_get() - Get the clock table to program DFS
 504  * @se:         Pointer to the concerned serial engine.
 505  * @tbl:        Table in which the output is returned.
 506  *
 507  * This function is called by the protocol drivers to determine the different
 508  * clock frequencies supported by serial engine core clock. The protocol
 509  * drivers use the output to determine the clock frequency index to be
 510  * programmed into DFS.
 511  *
 512  * Return: number of valid performance levels in the table on success,
 513  *         standard Linux error codes on failure.
 514  */
 515 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
 516 {
 517         long freq = 0;
 518         int i;
 519
 520         if (se->clk_perf_tbl) {
 521                 *tbl = se->clk_perf_tbl;
 522                 return se->num_clk_levels;
 523         }
 524
 525         se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
 526                                         sizeof(*se->clk_perf_tbl),
 527                                         GFP_KERNEL);
 528         if (!se->clk_perf_tbl)
 529                 return -ENOMEM;
 530
 531         for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
 532                 freq = clk_round_rate(se->clk, freq + 1);
 533                 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
 534                         break;
 535                 se->clk_perf_tbl[i] = freq;
 536         }
 537         se->num_clk_levels = i;
 538         *tbl = se->clk_perf_tbl;
 539         return se->num_clk_levels;
 540 }
 541 EXPORT_SYMBOL(geni_se_clk_tbl_get);
 542
 543 /**
 544  * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
 545  * @se:         Pointer to the concerned serial engine.
 546  * @req_freq:   Requested clock frequency.
 547  * @index:      Index of the resultant frequency in the table.
 548  * @res_freq:   Resultant frequency of the source clock.
 549  * @exact:      Flag to indicate exact multiple requirement of the requested
 550  *              frequency.
 551  *
 552  * This function is called by the protocol drivers to determine the best match
 553  * of the requested frequency as provided by the serial engine clock in order
 554  * to meet the performance requirements.
 555  *
 556  * If we return success:
 557  * - if @exact is true  then @res_freq / <an_integer> == @req_freq
 558  * - if @exact is false then @res_freq / <an_integer> <= @req_freq
 559  *
 560  * Return: 0 on success, standard Linux error codes on failure.
 561  */
 562 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
 563                            unsigned int *index, unsigned long *res_freq,
 564                            bool exact)
 565 {
 566         unsigned long *tbl;
 567         int num_clk_levels;
 568         int i;
 569         unsigned long best_delta;
 570         unsigned long new_delta;
 571         unsigned int divider;
 572
 573         num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
 574         if (num_clk_levels < 0)
 575                 return num_clk_levels;
 576
 577         if (num_clk_levels == 0)
 578                 return -EINVAL;
 579
 580         best_delta = ULONG_MAX;
 581         for (i = 0; i < num_clk_levels; i++) {
 582                 divider = DIV_ROUND_UP(tbl[i], req_freq);
 583                 new_delta = req_freq - tbl[i] / divider;
 584                 if (new_delta < best_delta) {
 585                         /* We have a new best! */
 586                         *index = i;
 587                         *res_freq = tbl[i];
 588
 589                         /* If the new best is exact then we're done */
 590                         if (new_delta == 0)
 591                                 return 0;
 592
 593                         /* Record how close we got */
 594                         best_delta = new_delta;
 595                 }
 596         }
 597
 598         if (exact)
 599                 return -EINVAL;
 600
 601         return 0;
 602 }
 603 EXPORT_SYMBOL(geni_se_clk_freq_match);
 604
 605 #define GENI_SE_DMA_DONE_EN BIT(0)
 606 #define GENI_SE_DMA_EOT_EN BIT(1)
 607 #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
 608 #define GENI_SE_DMA_EOT_BUF BIT(0)
 609 /**
 610  * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
 611  * @se:                 Pointer to the concerned serial engine.
 612  * @buf:                Pointer to the TX buffer.
 613  * @len:                Length of the TX buffer.
 614  * @iova:               Pointer to store the mapped DMA address.
 615  *
 616  * This function is used to prepare the buffers for DMA TX.
 617  *
 618  * Return: 0 on success, standard Linux error codes on failure.
 619  */
 620 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
 621                         dma_addr_t *iova)
 622 {
 623         struct geni_wrapper *wrapper = se->wrapper;
 624         u32 val;
 625
 626         *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
 627         if (dma_mapping_error(wrapper->dev, *iova))
 628                 return -EIO;
 629
 630         val = GENI_SE_DMA_DONE_EN;
 631         val |= GENI_SE_DMA_EOT_EN;
 632         val |= GENI_SE_DMA_AHB_ERR_EN;
 633         writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
 634         writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
 635         writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
 636         writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
 637         writel_relaxed(len, se->base + SE_DMA_TX_LEN);
 638         return 0;
 639 }
 640 EXPORT_SYMBOL(geni_se_tx_dma_prep);
 641
 642 /**
 643  * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
 644  * @se:                 Pointer to the concerned serial engine.
 645  * @buf:                Pointer to the RX buffer.
 646  * @len:                Length of the RX buffer.
 647  * @iova:               Pointer to store the mapped DMA address.
 648  *
 649  * This function is used to prepare the buffers for DMA RX.
 650  *
 651  * Return: 0 on success, standard Linux error codes on failure.
 652  */
 653 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
 654                         dma_addr_t *iova)
 655 {
 656         struct geni_wrapper *wrapper = se->wrapper;
 657         u32 val;
 658
 659         *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
 660         if (dma_mapping_error(wrapper->dev, *iova))
 661                 return -EIO;
 662
 663         val = GENI_SE_DMA_DONE_EN;
 664         val |= GENI_SE_DMA_EOT_EN;
 665         val |= GENI_SE_DMA_AHB_ERR_EN;
 666         writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
 667         writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
 668         writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
 669         /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
 670         writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
 671         writel_relaxed(len, se->base + SE_DMA_RX_LEN);
 672         return 0;
 673 }
 674 EXPORT_SYMBOL(geni_se_rx_dma_prep);
 675
 676 /**
 677  * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
 678  * @se:                 Pointer to the concerned serial engine.
 679  * @iova:               DMA address of the TX buffer.
 680  * @len:                Length of the TX buffer.
 681  *
 682  * This function is used to unprepare the DMA buffers after DMA TX.
 683  */
 684 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
 685 {
 686         struct geni_wrapper *wrapper = se->wrapper;
 687
 688         if (iova && !dma_mapping_error(wrapper->dev, iova))
 689                 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
 690 }
 691 EXPORT_SYMBOL(geni_se_tx_dma_unprep);
 692
 693 /**
 694  * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
 695  * @se:                 Pointer to the concerned serial engine.
 696  * @iova:               DMA address of the RX buffer.
 697  * @len:                Length of the RX buffer.
 698  *
 699  * This function is used to unprepare the DMA buffers after DMA RX.
 700  */
 701 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
 702 {
 703         struct geni_wrapper *wrapper = se->wrapper;
 704
 705         if (iova && !dma_mapping_error(wrapper->dev, iova))
 706                 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
 707 }
 708 EXPORT_SYMBOL(geni_se_rx_dma_unprep);
 709
 710 static int geni_se_probe(struct platform_device *pdev)
 711 {
 712         struct device *dev = &pdev->dev;
 713         struct resource *res;
 714         struct geni_wrapper *wrapper;
 715         int ret;
 716
 717         wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
 718         if (!wrapper)
 719                 return -ENOMEM;
 720
 721         wrapper->dev = dev;
 722         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 723         wrapper->base = devm_ioremap_resource(dev, res);
 724         if (IS_ERR(wrapper->base))
 725                 return PTR_ERR(wrapper->base);
 726
 727         wrapper->ahb_clks[0].id = "m-ahb";
 728         wrapper->ahb_clks[1].id = "s-ahb";
 729         ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
 730         if (ret) {
 731                 dev_err(dev, "Err getting AHB clks %d\n", ret);
 732                 return ret;
 733         }
 734
 735         dev_set_drvdata(dev, wrapper);
 736         dev_dbg(dev, "GENI SE Driver probed\n");
 737         return devm_of_platform_populate(dev);
 738 }
 739
 740 static const struct of_device_id geni_se_dt_match[] = {
 741         { .compatible = "qcom,geni-se-qup", },
 742         {}
 743 };
 744 MODULE_DEVICE_TABLE(of, geni_se_dt_match);
 745
 746 static struct platform_driver geni_se_driver = {
 747         .driver = {
 748                 .name = "geni_se_qup",
 749                 .of_match_table = geni_se_dt_match,
 750         },
 751         .probe = geni_se_probe,
 752 };
 753 module_platform_driver(geni_se_driver);
 754
 755 MODULE_DESCRIPTION("GENI Serial Engine Driver");
 756 MODULE_LICENSE("GPL v2");