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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / soc / renesas / rcar-sysc.c
blob0c80fab4f8de6bc85f573006f43a62406d23aeb9
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car SYSC Power management support
4 *
5 * Copyright (C) 2014 Magnus Damm
6 * Copyright (C) 2015-2017 Glider bvba
7 */
8
9 #include <linux/clk/renesas.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/mm.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_domain.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/io.h>
18 #include <linux/soc/renesas/rcar-sysc.h>
19
20 #include "rcar-sysc.h"
21
22 /* SYSC Common */
23 #define SYSCSR 0x00 /* SYSC Status Register */
24 #define SYSCISR 0x04 /* Interrupt Status Register */
25 #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
26 #define SYSCIER 0x0c /* Interrupt Enable Register */
27 #define SYSCIMR 0x10 /* Interrupt Mask Register */
28
29 /* SYSC Status Register */
30 #define SYSCSR_PONENB 1 /* Ready for power resume requests */
31 #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
32
33 /*
34 * Power Control Register Offsets inside the register block for each domain
35 * Note: The "CR" registers for ARM cores exist on H1 only
36 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
37 * Use PSCI on R-Car Gen3
38 */
39 #define PWRSR_OFFS 0x00 /* Power Status Register */
40 #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
41 #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
42 #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
43 #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
44 #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
45
46
47 #define SYSCSR_RETRIES 100
48 #define SYSCSR_DELAY_US 1
49
50 #define PWRER_RETRIES 100
51 #define PWRER_DELAY_US 1
52
53 #define SYSCISR_RETRIES 1000
54 #define SYSCISR_DELAY_US 1
55
56 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
57
58 struct rcar_sysc_ch {
59 u16 chan_offs;
60 u8 chan_bit;
61 u8 isr_bit;
62 };
63
64 static void __iomem *rcar_sysc_base;
65 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
66
67 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
68 {
69 unsigned int sr_bit, reg_offs;
70 int k;
71
72 if (on) {
73 sr_bit = SYSCSR_PONENB;
74 reg_offs = PWRONCR_OFFS;
75 } else {
76 sr_bit = SYSCSR_POFFENB;
77 reg_offs = PWROFFCR_OFFS;
78 }
79
80 /* Wait until SYSC is ready to accept a power request */
81 for (k = 0; k < SYSCSR_RETRIES; k++) {
82 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
83 break;
84 udelay(SYSCSR_DELAY_US);
85 }
86
87 if (k == SYSCSR_RETRIES)
88 return -EAGAIN;
89
90 /* Submit power shutoff or power resume request */
91 iowrite32(BIT(sysc_ch->chan_bit),
92 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
93
94 return 0;
95 }
96
97 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
98 {
99 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
100 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
101 unsigned int status;
102 unsigned long flags;
103 int ret = 0;
104 int k;
105
106 spin_lock_irqsave(&rcar_sysc_lock, flags);
107
108 /*
109 * The interrupt source needs to be enabled, but masked, to prevent the
110 * CPU from receiving it.
111 */
112 iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
113 rcar_sysc_base + SYSCIMR);
114 iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
115 rcar_sysc_base + SYSCIER);
116
117 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
118
119 /* Submit power shutoff or resume request until it was accepted */
120 for (k = 0; k < PWRER_RETRIES; k++) {
121 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
122 if (ret)
123 goto out;
124
125 status = ioread32(rcar_sysc_base +
126 sysc_ch->chan_offs + PWRER_OFFS);
127 if (!(status & chan_mask))
128 break;
129
130 udelay(PWRER_DELAY_US);
131 }
132
133 if (k == PWRER_RETRIES) {
134 ret = -EIO;
135 goto out;
136 }
137
138 /* Wait until the power shutoff or resume request has completed * */
139 for (k = 0; k < SYSCISR_RETRIES; k++) {
140 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
141 break;
142 udelay(SYSCISR_DELAY_US);
143 }
144
145 if (k == SYSCISR_RETRIES)
146 ret = -EIO;
147
148 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
149
150 out:
151 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
152
153 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
154 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
155 return ret;
156 }
157
158 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
159 {
160 unsigned int st;
161
162 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
163 if (st & BIT(sysc_ch->chan_bit))
164 return true;
165
166 return false;
167 }
168
169 struct rcar_sysc_pd {
170 struct generic_pm_domain genpd;
171 struct rcar_sysc_ch ch;
172 unsigned int flags;
173 char name[0];
174 };
175
176 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
177 {
178 return container_of(d, struct rcar_sysc_pd, genpd);
179 }
180
181 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
182 {
183 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
184
185 pr_debug("%s: %s\n", __func__, genpd->name);
186 return rcar_sysc_power(&pd->ch, false);
187 }
188
189 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
190 {
191 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
192
193 pr_debug("%s: %s\n", __func__, genpd->name);
194 return rcar_sysc_power(&pd->ch, true);
195 }
196
197 static bool has_cpg_mstp;
198
199 static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
200 {
201 struct generic_pm_domain *genpd = &pd->genpd;
202 const char *name = pd->genpd.name;
203 struct dev_power_governor *gov = &simple_qos_governor;
204 int error;
205
206 if (pd->flags & PD_CPU) {
207 /*
208 * This domain contains a CPU core and therefore it should
209 * only be turned off if the CPU is not in use.
210 */
211 pr_debug("PM domain %s contains %s\n", name, "CPU");
212 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
213 } else if (pd->flags & PD_SCU) {
214 /*
215 * This domain contains an SCU and cache-controller, and
216 * therefore it should only be turned off if the CPU cores are
217 * not in use.
218 */
219 pr_debug("PM domain %s contains %s\n", name, "SCU");
220 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
221 } else if (pd->flags & PD_NO_CR) {
222 /*
223 * This domain cannot be turned off.
224 */
225 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
226 }
227
228 if (!(pd->flags & (PD_CPU | PD_SCU))) {
229 /* Enable Clock Domain for I/O devices */
230 genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
231 if (has_cpg_mstp) {
232 genpd->attach_dev = cpg_mstp_attach_dev;
233 genpd->detach_dev = cpg_mstp_detach_dev;
234 } else {
235 genpd->attach_dev = cpg_mssr_attach_dev;
236 genpd->detach_dev = cpg_mssr_detach_dev;
237 }
238 }
239
240 genpd->power_off = rcar_sysc_pd_power_off;
241 genpd->power_on = rcar_sysc_pd_power_on;
242
243 if (pd->flags & (PD_CPU | PD_NO_CR)) {
244 /* Skip CPUs (handled by SMP code) and areas without control */
245 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
246 goto finalize;
247 }
248
249 if (!rcar_sysc_power_is_off(&pd->ch)) {
250 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
251 goto finalize;
252 }
253
254 rcar_sysc_power(&pd->ch, true);
255
256 finalize:
257 error = pm_genpd_init(genpd, gov, false);
258 if (error)
259 pr_err("Failed to init PM domain %s: %d\n", name, error);
260
261 return error;
262 }
263
264 static const struct of_device_id rcar_sysc_matches[] __initconst = {
265 #ifdef CONFIG_SYSC_R8A7743
266 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
267 /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
268 { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
269 #endif
270 #ifdef CONFIG_SYSC_R8A7745
271 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
272 #endif
273 #ifdef CONFIG_SYSC_R8A77470
274 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
275 #endif
276 #ifdef CONFIG_SYSC_R8A774A1
277 { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
278 #endif
279 #ifdef CONFIG_SYSC_R8A774C0
280 { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
281 #endif
282 #ifdef CONFIG_SYSC_R8A7779
283 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
284 #endif
285 #ifdef CONFIG_SYSC_R8A7790
286 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
287 #endif
288 #ifdef CONFIG_SYSC_R8A7791
289 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
290 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
291 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
292 #endif
293 #ifdef CONFIG_SYSC_R8A7792
294 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
295 #endif
296 #ifdef CONFIG_SYSC_R8A7794
297 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
298 #endif
299 #ifdef CONFIG_SYSC_R8A7795
300 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
301 #endif
302 #ifdef CONFIG_SYSC_R8A7796
303 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
304 #endif
305 #ifdef CONFIG_SYSC_R8A77965
306 { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
307 #endif
308 #ifdef CONFIG_SYSC_R8A77970
309 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
310 #endif
311 #ifdef CONFIG_SYSC_R8A77980
312 { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
313 #endif
314 #ifdef CONFIG_SYSC_R8A77990
315 { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
316 #endif
317 #ifdef CONFIG_SYSC_R8A77995
318 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
319 #endif
320 { /* sentinel */ }
321 };
322
323 struct rcar_pm_domains {
324 struct genpd_onecell_data onecell_data;
325 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
326 };
327
328 static struct genpd_onecell_data *rcar_sysc_onecell_data;
329
330 static int __init rcar_sysc_pd_init(void)
331 {
332 const struct rcar_sysc_info *info;
333 const struct of_device_id *match;
334 struct rcar_pm_domains *domains;
335 struct device_node *np;
336 void __iomem *base;
337 unsigned int i;
338 int error;
339
340 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
341 if (!np)
342 return -ENODEV;
343
344 info = match->data;
345
346 if (info->init) {
347 error = info->init();
348 if (error)
349 return error;
350 }
351
352 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
353 "renesas,cpg-mstp-clocks");
354
355 base = of_iomap(np, 0);
356 if (!base) {
357 pr_warn("%pOF: Cannot map regs\n", np);
358 error = -ENOMEM;
359 goto out_put;
360 }
361
362 rcar_sysc_base = base;
363
364 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
365 if (!domains) {
366 error = -ENOMEM;
367 goto out_put;
368 }
369
370 domains->onecell_data.domains = domains->domains;
371 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
372 rcar_sysc_onecell_data = &domains->onecell_data;
373
374 for (i = 0; i < info->num_areas; i++) {
375 const struct rcar_sysc_area *area = &info->areas[i];
376 struct rcar_sysc_pd *pd;
377
378 if (!area->name) {
379 /* Skip NULLified area */
380 continue;
381 }
382
383 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
384 if (!pd) {
385 error = -ENOMEM;
386 goto out_put;
387 }
388
389 strcpy(pd->name, area->name);
390 pd->genpd.name = pd->name;
391 pd->ch.chan_offs = area->chan_offs;
392 pd->ch.chan_bit = area->chan_bit;
393 pd->ch.isr_bit = area->isr_bit;
394 pd->flags = area->flags;
395
396 error = rcar_sysc_pd_setup(pd);
397 if (error)
398 goto out_put;
399
400 domains->domains[area->isr_bit] = &pd->genpd;
401
402 if (area->parent < 0)
403 continue;
404
405 error = pm_genpd_add_subdomain(domains->domains[area->parent],
406 &pd->genpd);
407 if (error) {
408 pr_warn("Failed to add PM subdomain %s to parent %u\n",
409 area->name, area->parent);
410 goto out_put;
411 }
412 }
413
414 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
415
416 out_put:
417 of_node_put(np);
418 return error;
419 }
420 early_initcall(rcar_sysc_pd_init);
421
422 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
423 unsigned int num_areas, u8 id)
424 {
425 unsigned int i;
426
427 for (i = 0; i < num_areas; i++)
428 if (areas[i].isr_bit == id) {
429 areas[i].name = NULL;
430 return;
431 }
432 }
433
434 #ifdef CONFIG_ARCH_R8A7779
435 static int rcar_sysc_power_cpu(unsigned int idx, bool on)
436 {
437 struct generic_pm_domain *genpd;
438 struct rcar_sysc_pd *pd;
439 unsigned int i;
440
441 if (!rcar_sysc_onecell_data)
442 return -ENODEV;
443
444 for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
445 genpd = rcar_sysc_onecell_data->domains[i];
446 if (!genpd)
447 continue;
448
449 pd = to_rcar_pd(genpd);
450 if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
451 continue;
452
453 return rcar_sysc_power(&pd->ch, on);
454 }
455
456 return -ENOENT;
457 }
458
459 int rcar_sysc_power_down_cpu(unsigned int cpu)
460 {
461 return rcar_sysc_power_cpu(cpu, false);
462 }
463
464 int rcar_sysc_power_up_cpu(unsigned int cpu)
465 {
466 return rcar_sysc_power_cpu(cpu, true);
467 }
468 #endif /* CONFIG_ARCH_R8A7779 */
Linux with added FPC-III support