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dt-bindings: mtd: ingenic: Use standard ecc-engine property
[linux/fpc-iii.git] / drivers / usb / host / xhci-tegra.c
blobefb0cad8710e3dcbc484ec2e78742fa14e79dbb8
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (C) 2014 NVIDIA Corporation
6 * Copyright (C) 2014 Google, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/tegra/xusb.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <soc/tegra/pmc.h>
27
28 #include "xhci.h"
29
30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
32
33 /* FPCI CFG registers */
34 #define XUSB_CFG_1 0x004
35 #define XUSB_IO_SPACE_EN BIT(0)
36 #define XUSB_MEM_SPACE_EN BIT(1)
37 #define XUSB_BUS_MASTER_EN BIT(2)
38 #define XUSB_CFG_4 0x010
39 #define XUSB_BASE_ADDR_SHIFT 15
40 #define XUSB_BASE_ADDR_MASK 0x1ffff
41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
42 #define XUSB_CFG_CSB_BASE_ADDR 0x800
43
44 /* FPCI mailbox registers */
45 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4
46 #define MBOX_DEST_FALC BIT(27)
47 #define MBOX_DEST_PME BIT(28)
48 #define MBOX_DEST_SMI BIT(29)
49 #define MBOX_DEST_XHCI BIT(30)
50 #define MBOX_INT_EN BIT(31)
51 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
52 #define CMD_DATA_SHIFT 0
53 #define CMD_DATA_MASK 0xffffff
54 #define CMD_TYPE_SHIFT 24
55 #define CMD_TYPE_MASK 0xff
56 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
57 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
58 #define MBOX_OWNER_NONE 0
59 #define MBOX_OWNER_FW 1
60 #define MBOX_OWNER_SW 2
61 #define XUSB_CFG_ARU_SMI_INTR 0x428
62 #define MBOX_SMI_INTR_FW_HANG BIT(1)
63 #define MBOX_SMI_INTR_EN BIT(3)
64
65 /* IPFS registers */
66 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
67 #define IPFS_EN_FPCI BIT(0)
68 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
69 #define IPFS_IP_INT_MASK BIT(16)
70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
71
72 #define CSB_PAGE_SELECT_MASK 0x7fffff
73 #define CSB_PAGE_SELECT_SHIFT 9
74 #define CSB_PAGE_OFFSET_MASK 0x1ff
75 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
76 CSB_PAGE_SELECT_MASK)
77 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
78
79 /* Falcon CSB registers */
80 #define XUSB_FALC_CPUCTL 0x100
81 #define CPUCTL_STARTCPU BIT(1)
82 #define CPUCTL_STATE_HALTED BIT(4)
83 #define CPUCTL_STATE_STOPPED BIT(5)
84 #define XUSB_FALC_BOOTVEC 0x104
85 #define XUSB_FALC_DMACTL 0x10c
86 #define XUSB_FALC_IMFILLRNG1 0x154
87 #define IMFILLRNG1_TAG_MASK 0xffff
88 #define IMFILLRNG1_TAG_LO_SHIFT 0
89 #define IMFILLRNG1_TAG_HI_SHIFT 16
90 #define XUSB_FALC_IMFILLCTL 0x158
91
92 /* MP CSB registers */
93 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
94 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
95 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
96 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
97 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
98 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
99 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
100 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
101 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
102 #define L2IMEMOP_ACTION_SHIFT 24
103 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
104 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
105 #define XUSB_CSB_MP_APMAP 0x10181c
106 #define APMAP_BOOTPATH BIT(31)
107
108 #define IMEM_BLOCK_SIZE 256
109
110 struct tegra_xusb_fw_header {
111 __le32 boot_loadaddr_in_imem;
112 __le32 boot_codedfi_offset;
113 __le32 boot_codetag;
114 __le32 boot_codesize;
115 __le32 phys_memaddr;
116 __le16 reqphys_memsize;
117 __le16 alloc_phys_memsize;
118 __le32 rodata_img_offset;
119 __le32 rodata_section_start;
120 __le32 rodata_section_end;
121 __le32 main_fnaddr;
122 __le32 fwimg_cksum;
123 __le32 fwimg_created_time;
124 __le32 imem_resident_start;
125 __le32 imem_resident_end;
126 __le32 idirect_start;
127 __le32 idirect_end;
128 __le32 l2_imem_start;
129 __le32 l2_imem_end;
130 __le32 version_id;
131 u8 init_ddirect;
132 u8 reserved[3];
133 __le32 phys_addr_log_buffer;
134 __le32 total_log_entries;
135 __le32 dequeue_ptr;
136 __le32 dummy_var[2];
137 __le32 fwimg_len;
138 u8 magic[8];
139 __le32 ss_low_power_entry_timeout;
140 u8 num_hsic_port;
141 u8 padding[139]; /* Pad to 256 bytes */
142 };
143
144 struct tegra_xusb_phy_type {
145 const char *name;
146 unsigned int num;
147 };
148
149 struct tegra_xusb_soc {
150 const char *firmware;
151 const char * const *supply_names;
152 unsigned int num_supplies;
153 const struct tegra_xusb_phy_type *phy_types;
154 unsigned int num_types;
155
156 struct {
157 struct {
158 unsigned int offset;
159 unsigned int count;
160 } usb2, ulpi, hsic, usb3;
161 } ports;
162
163 bool scale_ss_clock;
164 };
165
166 struct tegra_xusb {
167 struct device *dev;
168 void __iomem *regs;
169 struct usb_hcd *hcd;
170
171 struct mutex lock;
172
173 int xhci_irq;
174 int mbox_irq;
175
176 void __iomem *ipfs_base;
177 void __iomem *fpci_base;
178
179 const struct tegra_xusb_soc *soc;
180
181 struct regulator_bulk_data *supplies;
182
183 struct tegra_xusb_padctl *padctl;
184
185 struct clk *host_clk;
186 struct clk *falcon_clk;
187 struct clk *ss_clk;
188 struct clk *ss_src_clk;
189 struct clk *hs_src_clk;
190 struct clk *fs_src_clk;
191 struct clk *pll_u_480m;
192 struct clk *clk_m;
193 struct clk *pll_e;
194
195 struct reset_control *host_rst;
196 struct reset_control *ss_rst;
197
198 struct device *genpd_dev_host;
199 struct device *genpd_dev_ss;
200 struct device_link *genpd_dl_host;
201 struct device_link *genpd_dl_ss;
202
203 struct phy **phys;
204 unsigned int num_phys;
205
206 /* Firmware loading related */
207 struct {
208 size_t size;
209 void *virt;
210 dma_addr_t phys;
211 } fw;
212 };
213
214 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
215
216 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
217 {
218 return readl(tegra->fpci_base + offset);
219 }
220
221 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
222 unsigned int offset)
223 {
224 writel(value, tegra->fpci_base + offset);
225 }
226
227 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
228 {
229 return readl(tegra->ipfs_base + offset);
230 }
231
232 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
233 unsigned int offset)
234 {
235 writel(value, tegra->ipfs_base + offset);
236 }
237
238 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
239 {
240 u32 page = CSB_PAGE_SELECT(offset);
241 u32 ofs = CSB_PAGE_OFFSET(offset);
242
243 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
244
245 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
246 }
247
248 static void csb_writel(struct tegra_xusb *tegra, u32 value,
249 unsigned int offset)
250 {
251 u32 page = CSB_PAGE_SELECT(offset);
252 u32 ofs = CSB_PAGE_OFFSET(offset);
253
254 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
255 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
256 }
257
258 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
259 unsigned long rate)
260 {
261 unsigned long new_parent_rate, old_parent_rate;
262 struct clk *clk = tegra->ss_src_clk;
263 unsigned int div;
264 int err;
265
266 if (clk_get_rate(clk) == rate)
267 return 0;
268
269 switch (rate) {
270 case TEGRA_XHCI_SS_HIGH_SPEED:
271 /*
272 * Reparent to PLLU_480M. Set divider first to avoid
273 * overclocking.
274 */
275 old_parent_rate = clk_get_rate(clk_get_parent(clk));
276 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
277 div = new_parent_rate / rate;
278
279 err = clk_set_rate(clk, old_parent_rate / div);
280 if (err)
281 return err;
282
283 err = clk_set_parent(clk, tegra->pll_u_480m);
284 if (err)
285 return err;
286
287 /*
288 * The rate should already be correct, but set it again just
289 * to be sure.
290 */
291 err = clk_set_rate(clk, rate);
292 if (err)
293 return err;
294
295 break;
296
297 case TEGRA_XHCI_SS_LOW_SPEED:
298 /* Reparent to CLK_M */
299 err = clk_set_parent(clk, tegra->clk_m);
300 if (err)
301 return err;
302
303 err = clk_set_rate(clk, rate);
304 if (err)
305 return err;
306
307 break;
308
309 default:
310 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
311 return -EINVAL;
312 }
313
314 if (clk_get_rate(clk) != rate) {
315 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
316 return -EINVAL;
317 }
318
319 return 0;
320 }
321
322 static unsigned long extract_field(u32 value, unsigned int start,
323 unsigned int count)
324 {
325 return (value >> start) & ((1 << count) - 1);
326 }
327
328 /* Command requests from the firmware */
329 enum tegra_xusb_mbox_cmd {
330 MBOX_CMD_MSG_ENABLED = 1,
331 MBOX_CMD_INC_FALC_CLOCK,
332 MBOX_CMD_DEC_FALC_CLOCK,
333 MBOX_CMD_INC_SSPI_CLOCK,
334 MBOX_CMD_DEC_SSPI_CLOCK,
335 MBOX_CMD_SET_BW, /* no ACK/NAK required */
336 MBOX_CMD_SET_SS_PWR_GATING,
337 MBOX_CMD_SET_SS_PWR_UNGATING,
338 MBOX_CMD_SAVE_DFE_CTLE_CTX,
339 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
340 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
341 MBOX_CMD_START_HSIC_IDLE,
342 MBOX_CMD_STOP_HSIC_IDLE,
343 MBOX_CMD_DBC_WAKE_STACK, /* unused */
344 MBOX_CMD_HSIC_PRETEND_CONNECT,
345 MBOX_CMD_RESET_SSPI,
346 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
347 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
348
349 MBOX_CMD_MAX,
350
351 /* Response message to above commands */
352 MBOX_CMD_ACK = 128,
353 MBOX_CMD_NAK
354 };
355
356 static const char * const mbox_cmd_name[] = {
357 [ 1] = "MSG_ENABLE",
358 [ 2] = "INC_FALCON_CLOCK",
359 [ 3] = "DEC_FALCON_CLOCK",
360 [ 4] = "INC_SSPI_CLOCK",
361 [ 5] = "DEC_SSPI_CLOCK",
362 [ 6] = "SET_BW",
363 [ 7] = "SET_SS_PWR_GATING",
364 [ 8] = "SET_SS_PWR_UNGATING",
365 [ 9] = "SAVE_DFE_CTLE_CTX",
366 [ 10] = "AIRPLANE_MODE_ENABLED",
367 [ 11] = "AIRPLANE_MODE_DISABLED",
368 [ 12] = "START_HSIC_IDLE",
369 [ 13] = "STOP_HSIC_IDLE",
370 [ 14] = "DBC_WAKE_STACK",
371 [ 15] = "HSIC_PRETEND_CONNECT",
372 [ 16] = "RESET_SSPI",
373 [ 17] = "DISABLE_SS_LFPS_DETECTION",
374 [ 18] = "ENABLE_SS_LFPS_DETECTION",
375 [128] = "ACK",
376 [129] = "NAK",
377 };
378
379 struct tegra_xusb_mbox_msg {
380 u32 cmd;
381 u32 data;
382 };
383
384 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
385 {
386 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
387 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
388 }
389 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
390 u32 value)
391 {
392 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
393 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
394 }
395
396 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
397 {
398 switch (cmd) {
399 case MBOX_CMD_SET_BW:
400 case MBOX_CMD_ACK:
401 case MBOX_CMD_NAK:
402 return false;
403
404 default:
405 return true;
406 }
407 }
408
409 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
410 const struct tegra_xusb_mbox_msg *msg)
411 {
412 bool wait_for_idle = false;
413 u32 value;
414
415 /*
416 * Acquire the mailbox. The firmware still owns the mailbox for
417 * ACK/NAK messages.
418 */
419 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
420 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
421 if (value != MBOX_OWNER_NONE) {
422 dev_err(tegra->dev, "mailbox is busy\n");
423 return -EBUSY;
424 }
425
426 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
427
428 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
429 if (value != MBOX_OWNER_SW) {
430 dev_err(tegra->dev, "failed to acquire mailbox\n");
431 return -EBUSY;
432 }
433
434 wait_for_idle = true;
435 }
436
437 value = tegra_xusb_mbox_pack(msg);
438 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
439
440 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
441 value |= MBOX_INT_EN | MBOX_DEST_FALC;
442 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
443
444 if (wait_for_idle) {
445 unsigned long timeout = jiffies + msecs_to_jiffies(250);
446
447 while (time_before(jiffies, timeout)) {
448 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
449 if (value == MBOX_OWNER_NONE)
450 break;
451
452 usleep_range(10, 20);
453 }
454
455 if (time_after(jiffies, timeout))
456 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
457
458 if (value != MBOX_OWNER_NONE)
459 return -ETIMEDOUT;
460 }
461
462 return 0;
463 }
464
465 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
466 {
467 struct tegra_xusb *tegra = data;
468 u32 value;
469
470 /* clear mailbox interrupts */
471 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
472 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
473
474 if (value & MBOX_SMI_INTR_FW_HANG)
475 dev_err(tegra->dev, "controller firmware hang\n");
476
477 return IRQ_WAKE_THREAD;
478 }
479
480 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
481 const struct tegra_xusb_mbox_msg *msg)
482 {
483 struct tegra_xusb_padctl *padctl = tegra->padctl;
484 const struct tegra_xusb_soc *soc = tegra->soc;
485 struct device *dev = tegra->dev;
486 struct tegra_xusb_mbox_msg rsp;
487 unsigned long mask;
488 unsigned int port;
489 bool idle, enable;
490 int err = 0;
491
492 memset(&rsp, 0, sizeof(rsp));
493
494 switch (msg->cmd) {
495 case MBOX_CMD_INC_FALC_CLOCK:
496 case MBOX_CMD_DEC_FALC_CLOCK:
497 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
498 if (rsp.data != msg->data)
499 rsp.cmd = MBOX_CMD_NAK;
500 else
501 rsp.cmd = MBOX_CMD_ACK;
502
503 break;
504
505 case MBOX_CMD_INC_SSPI_CLOCK:
506 case MBOX_CMD_DEC_SSPI_CLOCK:
507 if (tegra->soc->scale_ss_clock) {
508 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
509 if (err < 0)
510 rsp.cmd = MBOX_CMD_NAK;
511 else
512 rsp.cmd = MBOX_CMD_ACK;
513
514 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
515 } else {
516 rsp.cmd = MBOX_CMD_ACK;
517 rsp.data = msg->data;
518 }
519
520 break;
521
522 case MBOX_CMD_SET_BW:
523 /*
524 * TODO: Request bandwidth once EMC scaling is supported.
525 * Ignore for now since ACK/NAK is not required for SET_BW
526 * messages.
527 */
528 break;
529
530 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
531 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
532 if (err < 0) {
533 dev_err(dev, "failed to save context for USB3#%u: %d\n",
534 msg->data, err);
535 rsp.cmd = MBOX_CMD_NAK;
536 } else {
537 rsp.cmd = MBOX_CMD_ACK;
538 }
539
540 rsp.data = msg->data;
541 break;
542
543 case MBOX_CMD_START_HSIC_IDLE:
544 case MBOX_CMD_STOP_HSIC_IDLE:
545 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
546 idle = false;
547 else
548 idle = true;
549
550 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
551 soc->ports.hsic.count);
552
553 for_each_set_bit(port, &mask, 32) {
554 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
555 idle);
556 if (err < 0)
557 break;
558 }
559
560 if (err < 0) {
561 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
562 idle ? "idle" : "busy", err);
563 rsp.cmd = MBOX_CMD_NAK;
564 } else {
565 rsp.cmd = MBOX_CMD_ACK;
566 }
567
568 rsp.data = msg->data;
569 break;
570
571 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
572 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
573 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
574 enable = false;
575 else
576 enable = true;
577
578 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
579 soc->ports.usb3.count);
580
581 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
582 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
583 port,
584 enable);
585 if (err < 0)
586 break;
587 }
588
589 if (err < 0) {
590 dev_err(dev,
591 "failed to %s LFPS detection on USB3#%u: %d\n",
592 enable ? "enable" : "disable", port, err);
593 rsp.cmd = MBOX_CMD_NAK;
594 } else {
595 rsp.cmd = MBOX_CMD_ACK;
596 }
597
598 rsp.data = msg->data;
599 break;
600
601 default:
602 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
603 break;
604 }
605
606 if (rsp.cmd) {
607 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
608
609 err = tegra_xusb_mbox_send(tegra, &rsp);
610 if (err < 0)
611 dev_err(dev, "failed to send %s: %d\n", cmd, err);
612 }
613 }
614
615 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
616 {
617 struct tegra_xusb *tegra = data;
618 struct tegra_xusb_mbox_msg msg;
619 u32 value;
620
621 mutex_lock(&tegra->lock);
622
623 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
624 tegra_xusb_mbox_unpack(&msg, value);
625
626 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
627 value &= ~MBOX_DEST_SMI;
628 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
629
630 /* clear mailbox owner if no ACK/NAK is required */
631 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
632 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
633
634 tegra_xusb_mbox_handle(tegra, &msg);
635
636 mutex_unlock(&tegra->lock);
637 return IRQ_HANDLED;
638 }
639
640 static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
641 struct resource *regs)
642 {
643 u32 value;
644
645 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
646 value |= IPFS_EN_FPCI;
647 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
648
649 usleep_range(10, 20);
650
651 /* Program BAR0 space */
652 value = fpci_readl(tegra, XUSB_CFG_4);
653 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
654 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
655 fpci_writel(tegra, value, XUSB_CFG_4);
656
657 usleep_range(100, 200);
658
659 /* Enable bus master */
660 value = fpci_readl(tegra, XUSB_CFG_1);
661 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
662 fpci_writel(tegra, value, XUSB_CFG_1);
663
664 /* Enable interrupt assertion */
665 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
666 value |= IPFS_IP_INT_MASK;
667 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
668
669 /* Set hysteresis */
670 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
671 }
672
673 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
674 {
675 int err;
676
677 err = clk_prepare_enable(tegra->pll_e);
678 if (err < 0)
679 return err;
680
681 err = clk_prepare_enable(tegra->host_clk);
682 if (err < 0)
683 goto disable_plle;
684
685 err = clk_prepare_enable(tegra->ss_clk);
686 if (err < 0)
687 goto disable_host;
688
689 err = clk_prepare_enable(tegra->falcon_clk);
690 if (err < 0)
691 goto disable_ss;
692
693 err = clk_prepare_enable(tegra->fs_src_clk);
694 if (err < 0)
695 goto disable_falc;
696
697 err = clk_prepare_enable(tegra->hs_src_clk);
698 if (err < 0)
699 goto disable_fs_src;
700
701 if (tegra->soc->scale_ss_clock) {
702 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
703 if (err < 0)
704 goto disable_hs_src;
705 }
706
707 return 0;
708
709 disable_hs_src:
710 clk_disable_unprepare(tegra->hs_src_clk);
711 disable_fs_src:
712 clk_disable_unprepare(tegra->fs_src_clk);
713 disable_falc:
714 clk_disable_unprepare(tegra->falcon_clk);
715 disable_ss:
716 clk_disable_unprepare(tegra->ss_clk);
717 disable_host:
718 clk_disable_unprepare(tegra->host_clk);
719 disable_plle:
720 clk_disable_unprepare(tegra->pll_e);
721 return err;
722 }
723
724 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
725 {
726 clk_disable_unprepare(tegra->pll_e);
727 clk_disable_unprepare(tegra->host_clk);
728 clk_disable_unprepare(tegra->ss_clk);
729 clk_disable_unprepare(tegra->falcon_clk);
730 clk_disable_unprepare(tegra->fs_src_clk);
731 clk_disable_unprepare(tegra->hs_src_clk);
732 }
733
734 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
735 {
736 unsigned int i;
737 int err;
738
739 for (i = 0; i < tegra->num_phys; i++) {
740 err = phy_init(tegra->phys[i]);
741 if (err)
742 goto disable_phy;
743
744 err = phy_power_on(tegra->phys[i]);
745 if (err) {
746 phy_exit(tegra->phys[i]);
747 goto disable_phy;
748 }
749 }
750
751 return 0;
752
753 disable_phy:
754 while (i--) {
755 phy_power_off(tegra->phys[i]);
756 phy_exit(tegra->phys[i]);
757 }
758
759 return err;
760 }
761
762 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
763 {
764 unsigned int i;
765
766 for (i = 0; i < tegra->num_phys; i++) {
767 phy_power_off(tegra->phys[i]);
768 phy_exit(tegra->phys[i]);
769 }
770 }
771
772 static int tegra_xusb_runtime_suspend(struct device *dev)
773 {
774 struct tegra_xusb *tegra = dev_get_drvdata(dev);
775
776 tegra_xusb_phy_disable(tegra);
777 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
778 tegra_xusb_clk_disable(tegra);
779
780 return 0;
781 }
782
783 static int tegra_xusb_runtime_resume(struct device *dev)
784 {
785 struct tegra_xusb *tegra = dev_get_drvdata(dev);
786 int err;
787
788 err = tegra_xusb_clk_enable(tegra);
789 if (err) {
790 dev_err(dev, "failed to enable clocks: %d\n", err);
791 return err;
792 }
793
794 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
795 if (err) {
796 dev_err(dev, "failed to enable regulators: %d\n", err);
797 goto disable_clk;
798 }
799
800 err = tegra_xusb_phy_enable(tegra);
801 if (err < 0) {
802 dev_err(dev, "failed to enable PHYs: %d\n", err);
803 goto disable_regulator;
804 }
805
806 return 0;
807
808 disable_regulator:
809 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
810 disable_clk:
811 tegra_xusb_clk_disable(tegra);
812 return err;
813 }
814
815 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
816 {
817 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
818 struct tegra_xusb_fw_header *header;
819 struct device *dev = tegra->dev;
820 const struct firmware *fw;
821 unsigned long timeout;
822 time64_t timestamp;
823 struct tm time;
824 u64 address;
825 u32 value;
826 int err;
827
828 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
829 if (err < 0) {
830 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
831 return err;
832 }
833
834 /* Load Falcon controller with its firmware. */
835 header = (struct tegra_xusb_fw_header *)fw->data;
836 tegra->fw.size = le32_to_cpu(header->fwimg_len);
837
838 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
839 &tegra->fw.phys, GFP_KERNEL);
840 if (!tegra->fw.virt) {
841 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
842 release_firmware(fw);
843 return -ENOMEM;
844 }
845
846 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
847 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
848 release_firmware(fw);
849
850 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
851 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
852 csb_readl(tegra, XUSB_FALC_CPUCTL));
853 return 0;
854 }
855
856 /* Program the size of DFI into ILOAD_ATTR. */
857 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
858
859 /*
860 * Boot code of the firmware reads the ILOAD_BASE registers
861 * to get to the start of the DFI in system memory.
862 */
863 address = tegra->fw.phys + sizeof(*header);
864 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
865 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
866
867 /* Set BOOTPATH to 1 in APMAP. */
868 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
869
870 /* Invalidate L2IMEM. */
871 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
872
873 /*
874 * Initiate fetch of bootcode from system memory into L2IMEM.
875 * Program bootcode location and size in system memory.
876 */
877 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
878 IMEM_BLOCK_SIZE);
879 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
880 IMEM_BLOCK_SIZE);
881 code_blocks = code_tag_blocks + code_size_blocks;
882
883 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
884 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
885 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
886 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
887 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
888
889 /* Trigger L2IMEM load operation. */
890 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
891 XUSB_CSB_MP_L2IMEMOP_TRIG);
892
893 /* Setup Falcon auto-fill. */
894 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
895
896 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
897 IMFILLRNG1_TAG_LO_SHIFT) |
898 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
899 IMFILLRNG1_TAG_HI_SHIFT);
900 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
901
902 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
903
904 msleep(50);
905
906 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
907 XUSB_FALC_BOOTVEC);
908
909 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
910 timeout = jiffies + msecs_to_jiffies(5);
911
912 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
913
914 while (time_before(jiffies, timeout)) {
915 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
916 break;
917
918 usleep_range(100, 200);
919 }
920
921 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
922 dev_err(dev, "Falcon failed to start, state: %#x\n",
923 csb_readl(tegra, XUSB_FALC_CPUCTL));
924 return -EIO;
925 }
926
927 timestamp = le32_to_cpu(header->fwimg_created_time);
928 time64_to_tm(timestamp, 0, &time);
929
930 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
931 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
932 time.tm_hour, time.tm_min, time.tm_sec);
933
934 return 0;
935 }
936
937 static void tegra_xusb_powerdomain_remove(struct device *dev,
938 struct tegra_xusb *tegra)
939 {
940 if (tegra->genpd_dl_ss)
941 device_link_del(tegra->genpd_dl_ss);
942 if (tegra->genpd_dl_host)
943 device_link_del(tegra->genpd_dl_host);
944 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
945 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
946 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
947 dev_pm_domain_detach(tegra->genpd_dev_host, true);
948 }
949
950 static int tegra_xusb_powerdomain_init(struct device *dev,
951 struct tegra_xusb *tegra)
952 {
953 int err;
954
955 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
956 if (IS_ERR(tegra->genpd_dev_host)) {
957 err = PTR_ERR(tegra->genpd_dev_host);
958 dev_err(dev, "failed to get host pm-domain: %d\n", err);
959 return err;
960 }
961
962 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
963 if (IS_ERR(tegra->genpd_dev_ss)) {
964 err = PTR_ERR(tegra->genpd_dev_ss);
965 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
966 return err;
967 }
968
969 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
970 DL_FLAG_PM_RUNTIME |
971 DL_FLAG_STATELESS);
972 if (!tegra->genpd_dl_host) {
973 dev_err(dev, "adding host device link failed!\n");
974 return -ENODEV;
975 }
976
977 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
978 DL_FLAG_PM_RUNTIME |
979 DL_FLAG_STATELESS);
980 if (!tegra->genpd_dl_ss) {
981 dev_err(dev, "adding superspeed device link failed!\n");
982 return -ENODEV;
983 }
984
985 return 0;
986 }
987
988 static int tegra_xusb_probe(struct platform_device *pdev)
989 {
990 struct tegra_xusb_mbox_msg msg;
991 struct resource *res, *regs;
992 struct tegra_xusb *tegra;
993 struct xhci_hcd *xhci;
994 unsigned int i, j, k;
995 struct phy *phy;
996 int err;
997
998 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
999
1000 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1001 if (!tegra)
1002 return -ENOMEM;
1003
1004 tegra->soc = of_device_get_match_data(&pdev->dev);
1005 mutex_init(&tegra->lock);
1006 tegra->dev = &pdev->dev;
1007
1008 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1009 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
1010 if (IS_ERR(tegra->regs))
1011 return PTR_ERR(tegra->regs);
1012
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1014 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
1015 if (IS_ERR(tegra->fpci_base))
1016 return PTR_ERR(tegra->fpci_base);
1017
1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1019 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
1020 if (IS_ERR(tegra->ipfs_base))
1021 return PTR_ERR(tegra->ipfs_base);
1022
1023 tegra->xhci_irq = platform_get_irq(pdev, 0);
1024 if (tegra->xhci_irq < 0)
1025 return tegra->xhci_irq;
1026
1027 tegra->mbox_irq = platform_get_irq(pdev, 1);
1028 if (tegra->mbox_irq < 0)
1029 return tegra->mbox_irq;
1030
1031 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1032 if (IS_ERR(tegra->padctl))
1033 return PTR_ERR(tegra->padctl);
1034
1035 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1036 if (IS_ERR(tegra->host_clk)) {
1037 err = PTR_ERR(tegra->host_clk);
1038 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1039 goto put_padctl;
1040 }
1041
1042 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1043 if (IS_ERR(tegra->falcon_clk)) {
1044 err = PTR_ERR(tegra->falcon_clk);
1045 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1046 goto put_padctl;
1047 }
1048
1049 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1050 if (IS_ERR(tegra->ss_clk)) {
1051 err = PTR_ERR(tegra->ss_clk);
1052 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1053 goto put_padctl;
1054 }
1055
1056 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1057 if (IS_ERR(tegra->ss_src_clk)) {
1058 err = PTR_ERR(tegra->ss_src_clk);
1059 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1060 goto put_padctl;
1061 }
1062
1063 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1064 if (IS_ERR(tegra->hs_src_clk)) {
1065 err = PTR_ERR(tegra->hs_src_clk);
1066 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1067 goto put_padctl;
1068 }
1069
1070 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1071 if (IS_ERR(tegra->fs_src_clk)) {
1072 err = PTR_ERR(tegra->fs_src_clk);
1073 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1074 goto put_padctl;
1075 }
1076
1077 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1078 if (IS_ERR(tegra->pll_u_480m)) {
1079 err = PTR_ERR(tegra->pll_u_480m);
1080 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1081 goto put_padctl;
1082 }
1083
1084 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1085 if (IS_ERR(tegra->clk_m)) {
1086 err = PTR_ERR(tegra->clk_m);
1087 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1088 goto put_padctl;
1089 }
1090
1091 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1092 if (IS_ERR(tegra->pll_e)) {
1093 err = PTR_ERR(tegra->pll_e);
1094 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1095 goto put_padctl;
1096 }
1097
1098 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1099 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1100 "xusb_host");
1101 if (IS_ERR(tegra->host_rst)) {
1102 err = PTR_ERR(tegra->host_rst);
1103 dev_err(&pdev->dev,
1104 "failed to get xusb_host reset: %d\n", err);
1105 goto put_padctl;
1106 }
1107
1108 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1109 if (IS_ERR(tegra->ss_rst)) {
1110 err = PTR_ERR(tegra->ss_rst);
1111 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1112 err);
1113 goto put_padctl;
1114 }
1115
1116 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1117 tegra->ss_clk,
1118 tegra->ss_rst);
1119 if (err) {
1120 dev_err(&pdev->dev,
1121 "failed to enable XUSBA domain: %d\n", err);
1122 goto put_padctl;
1123 }
1124
1125 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1126 tegra->host_clk,
1127 tegra->host_rst);
1128 if (err) {
1129 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1130 dev_err(&pdev->dev,
1131 "failed to enable XUSBC domain: %d\n", err);
1132 goto put_padctl;
1133 }
1134 } else {
1135 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1136 if (err)
1137 goto put_powerdomains;
1138 }
1139
1140 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1141 sizeof(*tegra->supplies), GFP_KERNEL);
1142 if (!tegra->supplies) {
1143 err = -ENOMEM;
1144 goto put_powerdomains;
1145 }
1146
1147 for (i = 0; i < tegra->soc->num_supplies; i++)
1148 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1149
1150 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1151 tegra->supplies);
1152 if (err) {
1153 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1154 goto put_powerdomains;
1155 }
1156
1157 for (i = 0; i < tegra->soc->num_types; i++)
1158 tegra->num_phys += tegra->soc->phy_types[i].num;
1159
1160 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1161 sizeof(*tegra->phys), GFP_KERNEL);
1162 if (!tegra->phys) {
1163 err = -ENOMEM;
1164 goto put_powerdomains;
1165 }
1166
1167 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1168 char prop[8];
1169
1170 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1171 snprintf(prop, sizeof(prop), "%s-%d",
1172 tegra->soc->phy_types[i].name, j);
1173
1174 phy = devm_phy_optional_get(&pdev->dev, prop);
1175 if (IS_ERR(phy)) {
1176 dev_err(&pdev->dev,
1177 "failed to get PHY %s: %ld\n", prop,
1178 PTR_ERR(phy));
1179 err = PTR_ERR(phy);
1180 goto put_powerdomains;
1181 }
1182
1183 tegra->phys[k++] = phy;
1184 }
1185 }
1186
1187 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1188 dev_name(&pdev->dev));
1189 if (!tegra->hcd) {
1190 err = -ENOMEM;
1191 goto put_powerdomains;
1192 }
1193
1194 /*
1195 * This must happen after usb_create_hcd(), because usb_create_hcd()
1196 * will overwrite the drvdata of the device with the hcd it creates.
1197 */
1198 platform_set_drvdata(pdev, tegra);
1199
1200 pm_runtime_enable(&pdev->dev);
1201 if (pm_runtime_enabled(&pdev->dev))
1202 err = pm_runtime_get_sync(&pdev->dev);
1203 else
1204 err = tegra_xusb_runtime_resume(&pdev->dev);
1205
1206 if (err < 0) {
1207 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1208 goto disable_rpm;
1209 }
1210
1211 tegra_xusb_ipfs_config(tegra, regs);
1212
1213 err = tegra_xusb_load_firmware(tegra);
1214 if (err < 0) {
1215 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1216 goto put_rpm;
1217 }
1218
1219 tegra->hcd->regs = tegra->regs;
1220 tegra->hcd->rsrc_start = regs->start;
1221 tegra->hcd->rsrc_len = resource_size(regs);
1222
1223 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1224 if (err < 0) {
1225 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1226 goto put_rpm;
1227 }
1228
1229 device_wakeup_enable(tegra->hcd->self.controller);
1230
1231 xhci = hcd_to_xhci(tegra->hcd);
1232
1233 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1234 &pdev->dev,
1235 dev_name(&pdev->dev),
1236 tegra->hcd);
1237 if (!xhci->shared_hcd) {
1238 dev_err(&pdev->dev, "failed to create shared HCD\n");
1239 err = -ENOMEM;
1240 goto remove_usb2;
1241 }
1242
1243 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1244 if (err < 0) {
1245 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1246 goto put_usb3;
1247 }
1248
1249 mutex_lock(&tegra->lock);
1250
1251 /* Enable firmware messages from controller. */
1252 msg.cmd = MBOX_CMD_MSG_ENABLED;
1253 msg.data = 0;
1254
1255 err = tegra_xusb_mbox_send(tegra, &msg);
1256 if (err < 0) {
1257 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1258 mutex_unlock(&tegra->lock);
1259 goto remove_usb3;
1260 }
1261
1262 mutex_unlock(&tegra->lock);
1263
1264 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1265 tegra_xusb_mbox_irq,
1266 tegra_xusb_mbox_thread, 0,
1267 dev_name(&pdev->dev), tegra);
1268 if (err < 0) {
1269 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1270 goto remove_usb3;
1271 }
1272
1273 return 0;
1274
1275 remove_usb3:
1276 usb_remove_hcd(xhci->shared_hcd);
1277 put_usb3:
1278 usb_put_hcd(xhci->shared_hcd);
1279 remove_usb2:
1280 usb_remove_hcd(tegra->hcd);
1281 put_rpm:
1282 if (!pm_runtime_status_suspended(&pdev->dev))
1283 tegra_xusb_runtime_suspend(&pdev->dev);
1284 disable_rpm:
1285 pm_runtime_disable(&pdev->dev);
1286 usb_put_hcd(tegra->hcd);
1287 put_powerdomains:
1288 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1289 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1290 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1291 } else {
1292 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1293 }
1294 put_padctl:
1295 tegra_xusb_padctl_put(tegra->padctl);
1296 return err;
1297 }
1298
1299 static int tegra_xusb_remove(struct platform_device *pdev)
1300 {
1301 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1302 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1303
1304 usb_remove_hcd(xhci->shared_hcd);
1305 usb_put_hcd(xhci->shared_hcd);
1306 xhci->shared_hcd = NULL;
1307 usb_remove_hcd(tegra->hcd);
1308 usb_put_hcd(tegra->hcd);
1309
1310 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1311 tegra->fw.phys);
1312
1313 pm_runtime_put_sync(&pdev->dev);
1314 pm_runtime_disable(&pdev->dev);
1315
1316 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1317 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1318 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1319 } else {
1320 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1321 }
1322
1323 tegra_xusb_padctl_put(tegra->padctl);
1324
1325 return 0;
1326 }
1327
1328 #ifdef CONFIG_PM_SLEEP
1329 static int tegra_xusb_suspend(struct device *dev)
1330 {
1331 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1332 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1333 bool wakeup = device_may_wakeup(dev);
1334
1335 /* TODO: Powergate controller across suspend/resume. */
1336 return xhci_suspend(xhci, wakeup);
1337 }
1338
1339 static int tegra_xusb_resume(struct device *dev)
1340 {
1341 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1342 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1343
1344 return xhci_resume(xhci, 0);
1345 }
1346 #endif
1347
1348 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1349 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1350 tegra_xusb_runtime_resume, NULL)
1351 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1352 };
1353
1354 static const char * const tegra124_supply_names[] = {
1355 "avddio-pex",
1356 "dvddio-pex",
1357 "avdd-usb",
1358 "avdd-pll-utmip",
1359 "avdd-pll-erefe",
1360 "avdd-usb-ss-pll",
1361 "hvdd-usb-ss",
1362 "hvdd-usb-ss-pll-e",
1363 };
1364
1365 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1366 { .name = "usb3", .num = 2, },
1367 { .name = "usb2", .num = 3, },
1368 { .name = "hsic", .num = 2, },
1369 };
1370
1371 static const struct tegra_xusb_soc tegra124_soc = {
1372 .firmware = "nvidia/tegra124/xusb.bin",
1373 .supply_names = tegra124_supply_names,
1374 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1375 .phy_types = tegra124_phy_types,
1376 .num_types = ARRAY_SIZE(tegra124_phy_types),
1377 .ports = {
1378 .usb2 = { .offset = 4, .count = 4, },
1379 .hsic = { .offset = 6, .count = 2, },
1380 .usb3 = { .offset = 0, .count = 2, },
1381 },
1382 .scale_ss_clock = true,
1383 };
1384 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1385
1386 static const char * const tegra210_supply_names[] = {
1387 "dvddio-pex",
1388 "hvddio-pex",
1389 "avdd-usb",
1390 "avdd-pll-utmip",
1391 "avdd-pll-uerefe",
1392 "dvdd-pex-pll",
1393 "hvdd-pex-pll-e",
1394 };
1395
1396 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1397 { .name = "usb3", .num = 4, },
1398 { .name = "usb2", .num = 4, },
1399 { .name = "hsic", .num = 1, },
1400 };
1401
1402 static const struct tegra_xusb_soc tegra210_soc = {
1403 .firmware = "nvidia/tegra210/xusb.bin",
1404 .supply_names = tegra210_supply_names,
1405 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1406 .phy_types = tegra210_phy_types,
1407 .num_types = ARRAY_SIZE(tegra210_phy_types),
1408 .ports = {
1409 .usb2 = { .offset = 4, .count = 4, },
1410 .hsic = { .offset = 8, .count = 1, },
1411 .usb3 = { .offset = 0, .count = 4, },
1412 },
1413 .scale_ss_clock = false,
1414 };
1415 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1416
1417 static const struct of_device_id tegra_xusb_of_match[] = {
1418 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1419 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1420 { },
1421 };
1422 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1423
1424 static struct platform_driver tegra_xusb_driver = {
1425 .probe = tegra_xusb_probe,
1426 .remove = tegra_xusb_remove,
1427 .driver = {
1428 .name = "tegra-xusb",
1429 .pm = &tegra_xusb_pm_ops,
1430 .of_match_table = tegra_xusb_of_match,
1431 },
1432 };
1433
1434 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1435 {
1436 xhci->quirks |= XHCI_PLAT;
1437 }
1438
1439 static int tegra_xhci_setup(struct usb_hcd *hcd)
1440 {
1441 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1442 }
1443
1444 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1445 .reset = tegra_xhci_setup,
1446 };
1447
1448 static int __init tegra_xusb_init(void)
1449 {
1450 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1451
1452 return platform_driver_register(&tegra_xusb_driver);
1453 }
1454 module_init(tegra_xusb_init);
1455
1456 static void __exit tegra_xusb_exit(void)
1457 {
1458 platform_driver_unregister(&tegra_xusb_driver);
1459 }
1460 module_exit(tegra_xusb_exit);
1461
1462 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1463 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1464 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support