drivers/usb/isp1760/isp1760-regs.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the NXP ISP1760 chip
   4  *
   5  * Copyright 2014 Laurent Pinchart
   6  * Copyright 2007 Sebastian Siewior
   7  *
   8  * Contacts:
   9  *     Sebastian Siewior <bigeasy@linutronix.de>
  10  *     Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  11  */
  12
  13 #ifndef _ISP1760_REGS_H_
  14 #define _ISP1760_REGS_H_
  15
  16 /* -----------------------------------------------------------------------------
  17  * Host Controller
  18  */
  19
  20 /* EHCI capability registers */
  21 #define HC_CAPLENGTH            0x000
  22 #define HC_LENGTH(p)            (((p) >> 00) & 0x00ff)  /* bits 7:0 */
  23 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)  /* bits 31:16 */
  24
  25 #define HC_HCSPARAMS            0x004
  26 #define HCS_INDICATOR(p)        ((p) & (1 << 16))       /* true: has port indicators */
  27 #define HCS_PPC(p)              ((p) & (1 << 4))        /* true: port power control */
  28 #define HCS_N_PORTS(p)          (((p) >> 0) & 0xf)      /* bits 3:0, ports on HC */
  29
  30 #define HC_HCCPARAMS            0x008
  31 #define HCC_ISOC_CACHE(p)       ((p) & (1 << 7))        /* true: can cache isoc frame */
  32 #define HCC_ISOC_THRES(p)       (((p) >> 4) & 0x7)      /* bits 6:4, uframes cached */
  33
  34 /* EHCI operational registers */
  35 #define HC_USBCMD               0x020
  36 #define CMD_LRESET              (1 << 7)                /* partial reset (no ports, etc) */
  37 #define CMD_RESET               (1 << 1)                /* reset HC not bus */
  38 #define CMD_RUN                 (1 << 0)                /* start/stop HC */
  39
  40 #define HC_USBSTS               0x024
  41 #define STS_PCD                 (1 << 2)                /* port change detect */
  42
  43 #define HC_FRINDEX              0x02c
  44
  45 #define HC_CONFIGFLAG           0x060
  46 #define FLAG_CF                 (1 << 0)                /* true: we'll support "high speed" */
  47
  48 #define HC_PORTSC1              0x064
  49 #define PORT_OWNER              (1 << 13)               /* true: companion hc owns this port */
  50 #define PORT_POWER              (1 << 12)               /* true: has power (see PPC) */
  51 #define PORT_USB11(x)           (((x) & (3 << 10)) == (1 << 10))        /* USB 1.1 device */
  52 #define PORT_RESET              (1 << 8)                /* reset port */
  53 #define PORT_SUSPEND            (1 << 7)                /* suspend port */
  54 #define PORT_RESUME             (1 << 6)                /* resume it */
  55 #define PORT_PE                 (1 << 2)                /* port enable */
  56 #define PORT_CSC                (1 << 1)                /* connect status change */
  57 #define PORT_CONNECT            (1 << 0)                /* device connected */
  58 #define PORT_RWC_BITS           (PORT_CSC)
  59
  60 #define HC_ISO_PTD_DONEMAP_REG  0x130
  61 #define HC_ISO_PTD_SKIPMAP_REG  0x134
  62 #define HC_ISO_PTD_LASTPTD_REG  0x138
  63 #define HC_INT_PTD_DONEMAP_REG  0x140
  64 #define HC_INT_PTD_SKIPMAP_REG  0x144
  65 #define HC_INT_PTD_LASTPTD_REG  0x148
  66 #define HC_ATL_PTD_DONEMAP_REG  0x150
  67 #define HC_ATL_PTD_SKIPMAP_REG  0x154
  68 #define HC_ATL_PTD_LASTPTD_REG  0x158
  69
  70 /* Configuration Register */
  71 #define HC_HW_MODE_CTRL         0x300
  72 #define ALL_ATX_RESET           (1 << 31)
  73 #define HW_ANA_DIGI_OC          (1 << 15)
  74 #define HW_DEV_DMA              (1 << 11)
  75 #define HW_COMN_IRQ             (1 << 10)
  76 #define HW_COMN_DMA             (1 << 9)
  77 #define HW_DATA_BUS_32BIT       (1 << 8)
  78 #define HW_DACK_POL_HIGH        (1 << 6)
  79 #define HW_DREQ_POL_HIGH        (1 << 5)
  80 #define HW_INTR_HIGH_ACT        (1 << 2)
  81 #define HW_INTR_EDGE_TRIG       (1 << 1)
  82 #define HW_GLOBAL_INTR_EN       (1 << 0)
  83
  84 #define HC_CHIP_ID_REG          0x304
  85 #define HC_SCRATCH_REG          0x308
  86
  87 #define HC_RESET_REG            0x30c
  88 #define SW_RESET_RESET_HC       (1 << 1)
  89 #define SW_RESET_RESET_ALL      (1 << 0)
  90
  91 #define HC_BUFFER_STATUS_REG    0x334
  92 #define ISO_BUF_FILL            (1 << 2)
  93 #define INT_BUF_FILL            (1 << 1)
  94 #define ATL_BUF_FILL            (1 << 0)
  95
  96 #define HC_MEMORY_REG           0x33c
  97 #define ISP_BANK(x)             ((x) << 16)
  98
  99 #define HC_PORT1_CTRL           0x374
 100 #define PORT1_POWER             (3 << 3)
 101 #define PORT1_INIT1             (1 << 7)
 102 #define PORT1_INIT2             (1 << 23)
 103 #define HW_OTG_CTRL_SET         0x374
 104 #define HW_OTG_CTRL_CLR         0x376
 105 #define HW_OTG_DISABLE          (1 << 10)
 106 #define HW_OTG_SE0_EN           (1 << 9)
 107 #define HW_BDIS_ACON_EN         (1 << 8)
 108 #define HW_SW_SEL_HC_DC         (1 << 7)
 109 #define HW_VBUS_CHRG            (1 << 6)
 110 #define HW_VBUS_DISCHRG         (1 << 5)
 111 #define HW_VBUS_DRV             (1 << 4)
 112 #define HW_SEL_CP_EXT           (1 << 3)
 113 #define HW_DM_PULLDOWN          (1 << 2)
 114 #define HW_DP_PULLDOWN          (1 << 1)
 115 #define HW_DP_PULLUP            (1 << 0)
 116
 117 /* Interrupt Register */
 118 #define HC_INTERRUPT_REG        0x310
 119
 120 #define HC_INTERRUPT_ENABLE     0x314
 121 #define HC_ISO_INT              (1 << 9)
 122 #define HC_ATL_INT              (1 << 8)
 123 #define HC_INTL_INT             (1 << 7)
 124 #define HC_EOT_INT              (1 << 3)
 125 #define HC_SOT_INT              (1 << 1)
 126 #define INTERRUPT_ENABLE_MASK   (HC_INTL_INT | HC_ATL_INT)
 127
 128 #define HC_ISO_IRQ_MASK_OR_REG  0x318
 129 #define HC_INT_IRQ_MASK_OR_REG  0x31c
 130 #define HC_ATL_IRQ_MASK_OR_REG  0x320
 131 #define HC_ISO_IRQ_MASK_AND_REG 0x324
 132 #define HC_INT_IRQ_MASK_AND_REG 0x328
 133 #define HC_ATL_IRQ_MASK_AND_REG 0x32c
 134
 135 /* -----------------------------------------------------------------------------
 136  * Peripheral Controller
 137  */
 138
 139 /* Initialization Registers */
 140 #define DC_ADDRESS                      0x0200
 141 #define DC_DEVEN                        (1 << 7)
 142
 143 #define DC_MODE                         0x020c
 144 #define DC_DMACLKON                     (1 << 9)
 145 #define DC_VBUSSTAT                     (1 << 8)
 146 #define DC_CLKAON                       (1 << 7)
 147 #define DC_SNDRSU                       (1 << 6)
 148 #define DC_GOSUSP                       (1 << 5)
 149 #define DC_SFRESET                      (1 << 4)
 150 #define DC_GLINTENA                     (1 << 3)
 151 #define DC_WKUPCS                       (1 << 2)
 152
 153 #define DC_INTCONF                      0x0210
 154 #define DC_CDBGMOD_ACK_NAK              (0 << 6)
 155 #define DC_CDBGMOD_ACK                  (1 << 6)
 156 #define DC_CDBGMOD_ACK_1NAK             (2 << 6)
 157 #define DC_DDBGMODIN_ACK_NAK            (0 << 4)
 158 #define DC_DDBGMODIN_ACK                (1 << 4)
 159 #define DC_DDBGMODIN_ACK_1NAK           (2 << 4)
 160 #define DC_DDBGMODOUT_ACK_NYET_NAK      (0 << 2)
 161 #define DC_DDBGMODOUT_ACK_NYET          (1 << 2)
 162 #define DC_DDBGMODOUT_ACK_NYET_1NAK     (2 << 2)
 163 #define DC_INTLVL                       (1 << 1)
 164 #define DC_INTPOL                       (1 << 0)
 165
 166 #define DC_DEBUG                        0x0212
 167 #define DC_INTENABLE                    0x0214
 168 #define DC_IEPTX(n)                     (1 << (11 + 2 * (n)))
 169 #define DC_IEPRX(n)                     (1 << (10 + 2 * (n)))
 170 #define DC_IEPRXTX(n)                   (3 << (10 + 2 * (n)))
 171 #define DC_IEP0SETUP                    (1 << 8)
 172 #define DC_IEVBUS                       (1 << 7)
 173 #define DC_IEDMA                        (1 << 6)
 174 #define DC_IEHS_STA                     (1 << 5)
 175 #define DC_IERESM                       (1 << 4)
 176 #define DC_IESUSP                       (1 << 3)
 177 #define DC_IEPSOF                       (1 << 2)
 178 #define DC_IESOF                        (1 << 1)
 179 #define DC_IEBRST                       (1 << 0)
 180
 181 /* Data Flow Registers */
 182 #define DC_EPINDEX                      0x022c
 183 #define DC_EP0SETUP                     (1 << 5)
 184 #define DC_ENDPIDX(n)                   ((n) << 1)
 185 #define DC_EPDIR                        (1 << 0)
 186
 187 #define DC_CTRLFUNC                     0x0228
 188 #define DC_CLBUF                        (1 << 4)
 189 #define DC_VENDP                        (1 << 3)
 190 #define DC_DSEN                         (1 << 2)
 191 #define DC_STATUS                       (1 << 1)
 192 #define DC_STALL                        (1 << 0)
 193
 194 #define DC_DATAPORT                     0x0220
 195 #define DC_BUFLEN                       0x021c
 196 #define DC_DATACOUNT_MASK               0xffff
 197 #define DC_BUFSTAT                      0x021e
 198 #define DC_EPMAXPKTSZ                   0x0204
 199
 200 #define DC_EPTYPE                       0x0208
 201 #define DC_NOEMPKT                      (1 << 4)
 202 #define DC_EPENABLE                     (1 << 3)
 203 #define DC_DBLBUF                       (1 << 2)
 204 #define DC_ENDPTYP_ISOC                 (1 << 0)
 205 #define DC_ENDPTYP_BULK                 (2 << 0)
 206 #define DC_ENDPTYP_INTERRUPT            (3 << 0)
 207
 208 /* DMA Registers */
 209 #define DC_DMACMD                       0x0230
 210 #define DC_DMATXCOUNT                   0x0234
 211 #define DC_DMACONF                      0x0238
 212 #define DC_DMAHW                        0x023c
 213 #define DC_DMAINTREASON                 0x0250
 214 #define DC_DMAINTEN                     0x0254
 215 #define DC_DMAEP                        0x0258
 216 #define DC_DMABURSTCOUNT                0x0264
 217
 218 /* General Registers */
 219 #define DC_INTERRUPT                    0x0218
 220 #define DC_CHIPID                       0x0270
 221 #define DC_FRAMENUM                     0x0274
 222 #define DC_SCRATCH                      0x0278
 223 #define DC_UNLOCKDEV                    0x027c
 224 #define DC_INTPULSEWIDTH                0x0280
 225 #define DC_TESTMODE                     0x0284
 226
 227 #endif