drivers/usb/musb/musb_dsps.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments DSPS platforms "glue layer"
   4  *
   5  * Copyright (C) 2012, by Texas Instruments
   6  *
   7  * Based on the am35x "glue layer" code.
   8  *
   9  * This file is part of the Inventra Controller Driver for Linux.
  10  *
  11  * musb_dsps.c will be a common file for all the TI DSPS platforms
  12  * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  13  * For now only ti81x is using this and in future davinci.c, am35x.c
  14  * da8xx.c would be merged to this file after testing.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/err.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/module.h>
  23 #include <linux/usb/usb_phy_generic.h>
  24 #include <linux/platform_data/usb-omap.h>
  25 #include <linux/sizes.h>
  26
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/usb/of.h>
  32
  33 #include <linux/debugfs.h>
  34
  35 #include "musb_core.h"
  36
  37 static const struct of_device_id musb_dsps_of_match[];
  38
  39 /**
  40  * DSPS musb wrapper register offset.
  41  * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  42  * musb ips.
  43  */
  44 struct dsps_musb_wrapper {
  45         u16     revision;
  46         u16     control;
  47         u16     status;
  48         u16     epintr_set;
  49         u16     epintr_clear;
  50         u16     epintr_status;
  51         u16     coreintr_set;
  52         u16     coreintr_clear;
  53         u16     coreintr_status;
  54         u16     phy_utmi;
  55         u16     mode;
  56         u16     tx_mode;
  57         u16     rx_mode;
  58
  59         /* bit positions for control */
  60         unsigned        reset:5;
  61
  62         /* bit positions for interrupt */
  63         unsigned        usb_shift:5;
  64         u32             usb_mask;
  65         u32             usb_bitmap;
  66         unsigned        drvvbus:5;
  67
  68         unsigned        txep_shift:5;
  69         u32             txep_mask;
  70         u32             txep_bitmap;
  71
  72         unsigned        rxep_shift:5;
  73         u32             rxep_mask;
  74         u32             rxep_bitmap;
  75
  76         /* bit positions for phy_utmi */
  77         unsigned        otg_disable:5;
  78
  79         /* bit positions for mode */
  80         unsigned        iddig:5;
  81         unsigned        iddig_mux:5;
  82         /* miscellaneous stuff */
  83         unsigned        poll_timeout;
  84 };
  85
  86 /*
  87  * register shadow for suspend
  88  */
  89 struct dsps_context {
  90         u32 control;
  91         u32 epintr;
  92         u32 coreintr;
  93         u32 phy_utmi;
  94         u32 mode;
  95         u32 tx_mode;
  96         u32 rx_mode;
  97 };
  98
  99 /**
 100  * DSPS glue structure.
 101  */
 102 struct dsps_glue {
 103         struct device *dev;
 104         struct platform_device *musb;   /* child musb pdev */
 105         const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
 106         int vbus_irq;                   /* optional vbus irq */
 107         unsigned long last_timer;    /* last timer data for each instance */
 108         bool sw_babble_enabled;
 109         void __iomem *usbss_base;
 110
 111         struct dsps_context context;
 112         struct debugfs_regset32 regset;
 113         struct dentry *dbgfs_root;
 114 };
 115
 116 static const struct debugfs_reg32 dsps_musb_regs[] = {
 117         { "revision",           0x00 },
 118         { "control",            0x14 },
 119         { "status",             0x18 },
 120         { "eoi",                0x24 },
 121         { "intr0_stat",         0x30 },
 122         { "intr1_stat",         0x34 },
 123         { "intr0_set",          0x38 },
 124         { "intr1_set",          0x3c },
 125         { "txmode",             0x70 },
 126         { "rxmode",             0x74 },
 127         { "autoreq",            0xd0 },
 128         { "srpfixtime",         0xd4 },
 129         { "tdown",              0xd8 },
 130         { "phy_utmi",           0xe0 },
 131         { "mode",               0xe8 },
 132 };
 133
 134 static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
 135 {
 136         struct musb *musb = platform_get_drvdata(glue->musb);
 137         int wait;
 138
 139         if (wait_ms < 0)
 140                 wait = msecs_to_jiffies(glue->wrp->poll_timeout);
 141         else
 142                 wait = msecs_to_jiffies(wait_ms);
 143
 144         mod_timer(&musb->dev_timer, jiffies + wait);
 145 }
 146
 147 /*
 148  * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
 149  */
 150 static void dsps_mod_timer_optional(struct dsps_glue *glue)
 151 {
 152         if (glue->vbus_irq)
 153                 return;
 154
 155         dsps_mod_timer(glue, -1);
 156 }
 157
 158 /* USBSS  / USB AM335x */
 159 #define USBSS_IRQ_STATUS        0x28
 160 #define USBSS_IRQ_ENABLER       0x2c
 161 #define USBSS_IRQ_CLEARR        0x30
 162
 163 #define USBSS_IRQ_PD_COMP       (1 << 2)
 164
 165 /**
 166  * dsps_musb_enable - enable interrupts
 167  */
 168 static void dsps_musb_enable(struct musb *musb)
 169 {
 170         struct device *dev = musb->controller;
 171         struct platform_device *pdev = to_platform_device(dev->parent);
 172         struct dsps_glue *glue = platform_get_drvdata(pdev);
 173         const struct dsps_musb_wrapper *wrp = glue->wrp;
 174         void __iomem *reg_base = musb->ctrl_base;
 175         u32 epmask, coremask;
 176
 177         /* Workaround: setup IRQs through both register sets. */
 178         epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
 179                ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
 180         coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
 181
 182         musb_writel(reg_base, wrp->epintr_set, epmask);
 183         musb_writel(reg_base, wrp->coreintr_set, coremask);
 184         /*
 185          * start polling for runtime PM active and idle,
 186          * and for ID change in dual-role idle mode.
 187          */
 188         if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
 189                 dsps_mod_timer(glue, -1);
 190 }
 191
 192 /**
 193  * dsps_musb_disable - disable HDRC and flush interrupts
 194  */
 195 static void dsps_musb_disable(struct musb *musb)
 196 {
 197         struct device *dev = musb->controller;
 198         struct platform_device *pdev = to_platform_device(dev->parent);
 199         struct dsps_glue *glue = platform_get_drvdata(pdev);
 200         const struct dsps_musb_wrapper *wrp = glue->wrp;
 201         void __iomem *reg_base = musb->ctrl_base;
 202
 203         musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
 204         musb_writel(reg_base, wrp->epintr_clear,
 205                          wrp->txep_bitmap | wrp->rxep_bitmap);
 206         del_timer_sync(&musb->dev_timer);
 207 }
 208
 209 /* Caller must take musb->lock */
 210 static int dsps_check_status(struct musb *musb, void *unused)
 211 {
 212         void __iomem *mregs = musb->mregs;
 213         struct device *dev = musb->controller;
 214         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 215         const struct dsps_musb_wrapper *wrp = glue->wrp;
 216         u8 devctl;
 217         int skip_session = 0;
 218
 219         if (glue->vbus_irq)
 220                 del_timer(&musb->dev_timer);
 221
 222         /*
 223          * We poll because DSPS IP's won't expose several OTG-critical
 224          * status change events (from the transceiver) otherwise.
 225          */
 226         devctl = musb_readb(mregs, MUSB_DEVCTL);
 227         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 228                                 usb_otg_state_string(musb->xceiv->otg->state));
 229
 230         switch (musb->xceiv->otg->state) {
 231         case OTG_STATE_A_WAIT_VRISE:
 232                 if (musb->port_mode == MUSB_HOST) {
 233                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
 234                         dsps_mod_timer_optional(glue);
 235                         break;
 236                 }
 237                 /* fall through */
 238
 239         case OTG_STATE_A_WAIT_BCON:
 240                 /* keep VBUS on for host-only mode */
 241                 if (musb->port_mode == MUSB_HOST) {
 242                         dsps_mod_timer_optional(glue);
 243                         break;
 244                 }
 245                 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 246                 skip_session = 1;
 247                 /* fall through */
 248
 249         case OTG_STATE_A_IDLE:
 250         case OTG_STATE_B_IDLE:
 251                 if (!glue->vbus_irq) {
 252                         if (devctl & MUSB_DEVCTL_BDEVICE) {
 253                                 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 254                                 MUSB_DEV_MODE(musb);
 255                         } else {
 256                                 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 257                                 MUSB_HST_MODE(musb);
 258                         }
 259
 260                         if (musb->port_mode == MUSB_PERIPHERAL)
 261                                 skip_session = 1;
 262
 263                         if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
 264                                 musb_writeb(mregs, MUSB_DEVCTL,
 265                                             MUSB_DEVCTL_SESSION);
 266                 }
 267                 dsps_mod_timer_optional(glue);
 268                 break;
 269         case OTG_STATE_A_WAIT_VFALL:
 270                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 271                 musb_writel(musb->ctrl_base, wrp->coreintr_set,
 272                             MUSB_INTR_VBUSERROR << wrp->usb_shift);
 273                 break;
 274         default:
 275                 break;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void otg_timer(struct timer_list *t)
 282 {
 283         struct musb *musb = from_timer(musb, t, dev_timer);
 284         struct device *dev = musb->controller;
 285         unsigned long flags;
 286         int err;
 287
 288         err = pm_runtime_get(dev);
 289         if ((err != -EINPROGRESS) && err < 0) {
 290                 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
 291                 pm_runtime_put_noidle(dev);
 292
 293                 return;
 294         }
 295
 296         spin_lock_irqsave(&musb->lock, flags);
 297         err = musb_queue_resume_work(musb, dsps_check_status, NULL);
 298         if (err < 0)
 299                 dev_err(dev, "%s resume work: %i\n", __func__, err);
 300         spin_unlock_irqrestore(&musb->lock, flags);
 301         pm_runtime_mark_last_busy(dev);
 302         pm_runtime_put_autosuspend(dev);
 303 }
 304
 305 static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
 306 {
 307         u32 epintr;
 308         struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
 309         const struct dsps_musb_wrapper *wrp = glue->wrp;
 310
 311         /* musb->lock might already been held */
 312         epintr = (1 << epnum) << wrp->rxep_shift;
 313         musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
 314 }
 315
 316 static irqreturn_t dsps_interrupt(int irq, void *hci)
 317 {
 318         struct musb  *musb = hci;
 319         void __iomem *reg_base = musb->ctrl_base;
 320         struct device *dev = musb->controller;
 321         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 322         const struct dsps_musb_wrapper *wrp = glue->wrp;
 323         unsigned long flags;
 324         irqreturn_t ret = IRQ_NONE;
 325         u32 epintr, usbintr;
 326
 327         spin_lock_irqsave(&musb->lock, flags);
 328
 329         /* Get endpoint interrupts */
 330         epintr = musb_readl(reg_base, wrp->epintr_status);
 331         musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
 332         musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
 333
 334         if (epintr)
 335                 musb_writel(reg_base, wrp->epintr_status, epintr);
 336
 337         /* Get usb core interrupts */
 338         usbintr = musb_readl(reg_base, wrp->coreintr_status);
 339         if (!usbintr && !epintr)
 340                 goto out;
 341
 342         musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
 343         if (usbintr)
 344                 musb_writel(reg_base, wrp->coreintr_status, usbintr);
 345
 346         dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
 347                         usbintr, epintr);
 348
 349         if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
 350                 int drvvbus = musb_readl(reg_base, wrp->status);
 351                 void __iomem *mregs = musb->mregs;
 352                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 353                 int err;
 354
 355                 err = musb->int_usb & MUSB_INTR_VBUSERROR;
 356                 if (err) {
 357                         /*
 358                          * The Mentor core doesn't debounce VBUS as needed
 359                          * to cope with device connect current spikes. This
 360                          * means it's not uncommon for bus-powered devices
 361                          * to get VBUS errors during enumeration.
 362                          *
 363                          * This is a workaround, but newer RTL from Mentor
 364                          * seems to allow a better one: "re"-starting sessions
 365                          * without waiting for VBUS to stop registering in
 366                          * devctl.
 367                          */
 368                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 369                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
 370                         dsps_mod_timer_optional(glue);
 371                         WARNING("VBUS error workaround (delay coming)\n");
 372                 } else if (drvvbus) {
 373                         MUSB_HST_MODE(musb);
 374                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 375                         dsps_mod_timer_optional(glue);
 376                 } else {
 377                         musb->is_active = 0;
 378                         MUSB_DEV_MODE(musb);
 379                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 380                 }
 381
 382                 /* NOTE: this must complete power-on within 100 ms. */
 383                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 384                                 drvvbus ? "on" : "off",
 385                                 usb_otg_state_string(musb->xceiv->otg->state),
 386                                 err ? " ERROR" : "",
 387                                 devctl);
 388                 ret = IRQ_HANDLED;
 389         }
 390
 391         if (musb->int_tx || musb->int_rx || musb->int_usb)
 392                 ret |= musb_interrupt(musb);
 393
 394         /* Poll for ID change and connect */
 395         switch (musb->xceiv->otg->state) {
 396         case OTG_STATE_B_IDLE:
 397         case OTG_STATE_A_WAIT_BCON:
 398                 dsps_mod_timer_optional(glue);
 399                 break;
 400         default:
 401                 break;
 402         }
 403
 404 out:
 405         spin_unlock_irqrestore(&musb->lock, flags);
 406
 407         return ret;
 408 }
 409
 410 static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
 411 {
 412         struct dentry *root;
 413         char buf[128];
 414
 415         sprintf(buf, "%s.dsps", dev_name(musb->controller));
 416         root = debugfs_create_dir(buf, NULL);
 417         glue->dbgfs_root = root;
 418
 419         glue->regset.regs = dsps_musb_regs;
 420         glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
 421         glue->regset.base = musb->ctrl_base;
 422
 423         debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
 424         return 0;
 425 }
 426
 427 static int dsps_musb_init(struct musb *musb)
 428 {
 429         struct device *dev = musb->controller;
 430         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 431         struct platform_device *parent = to_platform_device(dev->parent);
 432         const struct dsps_musb_wrapper *wrp = glue->wrp;
 433         void __iomem *reg_base;
 434         struct resource *r;
 435         u32 rev, val;
 436         int ret;
 437
 438         r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
 439         reg_base = devm_ioremap_resource(dev, r);
 440         if (IS_ERR(reg_base))
 441                 return PTR_ERR(reg_base);
 442         musb->ctrl_base = reg_base;
 443
 444         /* NOP driver needs change if supporting dual instance */
 445         musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
 446         if (IS_ERR(musb->xceiv))
 447                 return PTR_ERR(musb->xceiv);
 448
 449         musb->phy = devm_phy_get(dev->parent, "usb2-phy");
 450
 451         /* Returns zero if e.g. not clocked */
 452         rev = musb_readl(reg_base, wrp->revision);
 453         if (!rev)
 454                 return -ENODEV;
 455
 456         if (IS_ERR(musb->phy))  {
 457                 musb->phy = NULL;
 458         } else {
 459                 ret = phy_init(musb->phy);
 460                 if (ret < 0)
 461                         return ret;
 462                 ret = phy_power_on(musb->phy);
 463                 if (ret) {
 464                         phy_exit(musb->phy);
 465                         return ret;
 466                 }
 467         }
 468
 469         timer_setup(&musb->dev_timer, otg_timer, 0);
 470
 471         /* Reset the musb */
 472         musb_writel(reg_base, wrp->control, (1 << wrp->reset));
 473
 474         musb->isr = dsps_interrupt;
 475
 476         /* reset the otgdisable bit, needed for host mode to work */
 477         val = musb_readl(reg_base, wrp->phy_utmi);
 478         val &= ~(1 << wrp->otg_disable);
 479         musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
 480
 481         /*
 482          *  Check whether the dsps version has babble control enabled.
 483          * In latest silicon revision the babble control logic is enabled.
 484          * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
 485          * logic enabled.
 486          */
 487         val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
 488         if (val & MUSB_BABBLE_RCV_DISABLE) {
 489                 glue->sw_babble_enabled = true;
 490                 val |= MUSB_BABBLE_SW_SESSION_CTRL;
 491                 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
 492         }
 493
 494         dsps_mod_timer(glue, -1);
 495
 496         return dsps_musb_dbg_init(musb, glue);
 497 }
 498
 499 static int dsps_musb_exit(struct musb *musb)
 500 {
 501         struct device *dev = musb->controller;
 502         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 503
 504         del_timer_sync(&musb->dev_timer);
 505         phy_power_off(musb->phy);
 506         phy_exit(musb->phy);
 507         debugfs_remove_recursive(glue->dbgfs_root);
 508
 509         return 0;
 510 }
 511
 512 static int dsps_musb_set_mode(struct musb *musb, u8 mode)
 513 {
 514         struct device *dev = musb->controller;
 515         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 516         const struct dsps_musb_wrapper *wrp = glue->wrp;
 517         void __iomem *ctrl_base = musb->ctrl_base;
 518         u32 reg;
 519
 520         reg = musb_readl(ctrl_base, wrp->mode);
 521
 522         switch (mode) {
 523         case MUSB_HOST:
 524                 reg &= ~(1 << wrp->iddig);
 525
 526                 /*
 527                  * if we're setting mode to host-only or device-only, we're
 528                  * going to ignore whatever the PHY sends us and just force
 529                  * ID pin status by SW
 530                  */
 531                 reg |= (1 << wrp->iddig_mux);
 532
 533                 musb_writel(ctrl_base, wrp->mode, reg);
 534                 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
 535                 break;
 536         case MUSB_PERIPHERAL:
 537                 reg |= (1 << wrp->iddig);
 538
 539                 /*
 540                  * if we're setting mode to host-only or device-only, we're
 541                  * going to ignore whatever the PHY sends us and just force
 542                  * ID pin status by SW
 543                  */
 544                 reg |= (1 << wrp->iddig_mux);
 545
 546                 musb_writel(ctrl_base, wrp->mode, reg);
 547                 break;
 548         case MUSB_OTG:
 549                 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
 550                 break;
 551         default:
 552                 dev_err(glue->dev, "unsupported mode %d\n", mode);
 553                 return -EINVAL;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static bool dsps_sw_babble_control(struct musb *musb)
 560 {
 561         u8 babble_ctl;
 562         bool session_restart =  false;
 563
 564         babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
 565         dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
 566                 babble_ctl);
 567         /*
 568          * check line monitor flag to check whether babble is
 569          * due to noise
 570          */
 571         dev_dbg(musb->controller, "STUCK_J is %s\n",
 572                 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
 573
 574         if (babble_ctl & MUSB_BABBLE_STUCK_J) {
 575                 int timeout = 10;
 576
 577                 /*
 578                  * babble is due to noise, then set transmit idle (d7 bit)
 579                  * to resume normal operation
 580                  */
 581                 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
 582                 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
 583                 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
 584
 585                 /* wait till line monitor flag cleared */
 586                 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
 587                 do {
 588                         babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
 589                         udelay(1);
 590                 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
 591
 592                 /* check whether stuck_at_j bit cleared */
 593                 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
 594                         /*
 595                          * real babble condition has occurred
 596                          * restart the controller to start the
 597                          * session again
 598                          */
 599                         dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
 600                                 babble_ctl);
 601                         session_restart = true;
 602                 }
 603         } else {
 604                 session_restart = true;
 605         }
 606
 607         return session_restart;
 608 }
 609
 610 static int dsps_musb_recover(struct musb *musb)
 611 {
 612         struct device *dev = musb->controller;
 613         struct dsps_glue *glue = dev_get_drvdata(dev->parent);
 614         int session_restart = 0;
 615
 616         if (glue->sw_babble_enabled)
 617                 session_restart = dsps_sw_babble_control(musb);
 618         else
 619                 session_restart = 1;
 620
 621         return session_restart ? 0 : -EPIPE;
 622 }
 623
 624 /* Similar to am35x, dm81xx support only 32-bit read operation */
 625 static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 626 {
 627         void __iomem *fifo = hw_ep->fifo;
 628
 629         if (len >= 4) {
 630                 ioread32_rep(fifo, dst, len >> 2);
 631                 dst += len & ~0x03;
 632                 len &= 0x03;
 633         }
 634
 635         /* Read any remaining 1 to 3 bytes */
 636         if (len > 0) {
 637                 u32 val = musb_readl(fifo, 0);
 638                 memcpy(dst, &val, len);
 639         }
 640 }
 641
 642 #ifdef CONFIG_USB_TI_CPPI41_DMA
 643 static void dsps_dma_controller_callback(struct dma_controller *c)
 644 {
 645         struct musb *musb = c->musb;
 646         struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
 647         void __iomem *usbss_base = glue->usbss_base;
 648         u32 status;
 649
 650         status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
 651         if (status & USBSS_IRQ_PD_COMP)
 652                 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
 653 }
 654
 655 static struct dma_controller *
 656 dsps_dma_controller_create(struct musb *musb, void __iomem *base)
 657 {
 658         struct dma_controller *controller;
 659         struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
 660         void __iomem *usbss_base = glue->usbss_base;
 661
 662         controller = cppi41_dma_controller_create(musb, base);
 663         if (IS_ERR_OR_NULL(controller))
 664                 return controller;
 665
 666         musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
 667         controller->dma_callback = dsps_dma_controller_callback;
 668
 669         return controller;
 670 }
 671
 672 #ifdef CONFIG_PM_SLEEP
 673 static void dsps_dma_controller_suspend(struct dsps_glue *glue)
 674 {
 675         void __iomem *usbss_base = glue->usbss_base;
 676
 677         musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
 678 }
 679
 680 static void dsps_dma_controller_resume(struct dsps_glue *glue)
 681 {
 682         void __iomem *usbss_base = glue->usbss_base;
 683
 684         musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
 685 }
 686 #endif
 687 #else /* CONFIG_USB_TI_CPPI41_DMA */
 688 #ifdef CONFIG_PM_SLEEP
 689 static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
 690 static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
 691 #endif
 692 #endif /* CONFIG_USB_TI_CPPI41_DMA */
 693
 694 static struct musb_platform_ops dsps_ops = {
 695         .quirks         = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
 696         .init           = dsps_musb_init,
 697         .exit           = dsps_musb_exit,
 698
 699 #ifdef CONFIG_USB_TI_CPPI41_DMA
 700         .dma_init       = dsps_dma_controller_create,
 701         .dma_exit       = cppi41_dma_controller_destroy,
 702 #endif
 703         .enable         = dsps_musb_enable,
 704         .disable        = dsps_musb_disable,
 705
 706         .set_mode       = dsps_musb_set_mode,
 707         .recover        = dsps_musb_recover,
 708         .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
 709 };
 710
 711 static u64 musb_dmamask = DMA_BIT_MASK(32);
 712
 713 static int get_int_prop(struct device_node *dn, const char *s)
 714 {
 715         int ret;
 716         u32 val;
 717
 718         ret = of_property_read_u32(dn, s, &val);
 719         if (ret)
 720                 return 0;
 721         return val;
 722 }
 723
 724 static int dsps_create_musb_pdev(struct dsps_glue *glue,
 725                 struct platform_device *parent)
 726 {
 727         struct musb_hdrc_platform_data pdata;
 728         struct resource resources[2];
 729         struct resource *res;
 730         struct device *dev = &parent->dev;
 731         struct musb_hdrc_config *config;
 732         struct platform_device *musb;
 733         struct device_node *dn = parent->dev.of_node;
 734         int ret, val;
 735
 736         memset(resources, 0, sizeof(resources));
 737         res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
 738         if (!res) {
 739                 dev_err(dev, "failed to get memory.\n");
 740                 return -EINVAL;
 741         }
 742         resources[0] = *res;
 743
 744         res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
 745         if (!res) {
 746                 dev_err(dev, "failed to get irq.\n");
 747                 return -EINVAL;
 748         }
 749         resources[1] = *res;
 750
 751         /* allocate the child platform device */
 752         musb = platform_device_alloc("musb-hdrc",
 753                         (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
 754         if (!musb) {
 755                 dev_err(dev, "failed to allocate musb device\n");
 756                 return -ENOMEM;
 757         }
 758
 759         musb->dev.parent                = dev;
 760         musb->dev.dma_mask              = &musb_dmamask;
 761         musb->dev.coherent_dma_mask     = musb_dmamask;
 762         device_set_of_node_from_dev(&musb->dev, &parent->dev);
 763
 764         glue->musb = musb;
 765
 766         ret = platform_device_add_resources(musb, resources,
 767                         ARRAY_SIZE(resources));
 768         if (ret) {
 769                 dev_err(dev, "failed to add resources\n");
 770                 goto err;
 771         }
 772
 773         config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
 774         if (!config) {
 775                 ret = -ENOMEM;
 776                 goto err;
 777         }
 778         pdata.config = config;
 779         pdata.platform_ops = &dsps_ops;
 780
 781         config->num_eps = get_int_prop(dn, "mentor,num-eps");
 782         config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
 783         config->host_port_deassert_reset_at_resume = 1;
 784         pdata.mode = musb_get_mode(dev);
 785         /* DT keeps this entry in mA, musb expects it as per USB spec */
 786         pdata.power = get_int_prop(dn, "mentor,power") / 2;
 787
 788         ret = of_property_read_u32(dn, "mentor,multipoint", &val);
 789         if (!ret && val)
 790                 config->multipoint = true;
 791
 792         config->maximum_speed = usb_get_maximum_speed(&parent->dev);
 793         switch (config->maximum_speed) {
 794         case USB_SPEED_LOW:
 795         case USB_SPEED_FULL:
 796                 break;
 797         case USB_SPEED_SUPER:
 798                 dev_warn(dev, "ignore incorrect maximum_speed "
 799                                 "(super-speed) setting in dts");
 800                 /* fall through */
 801         default:
 802                 config->maximum_speed = USB_SPEED_HIGH;
 803         }
 804
 805         ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
 806         if (ret) {
 807                 dev_err(dev, "failed to add platform_data\n");
 808                 goto err;
 809         }
 810
 811         ret = platform_device_add(musb);
 812         if (ret) {
 813                 dev_err(dev, "failed to register musb device\n");
 814                 goto err;
 815         }
 816         return 0;
 817
 818 err:
 819         platform_device_put(musb);
 820         return ret;
 821 }
 822
 823 static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
 824 {
 825         struct dsps_glue *glue = priv;
 826         struct musb *musb = platform_get_drvdata(glue->musb);
 827
 828         if (!musb)
 829                 return IRQ_NONE;
 830
 831         dev_dbg(glue->dev, "VBUS interrupt\n");
 832         dsps_mod_timer(glue, 0);
 833
 834         return IRQ_HANDLED;
 835 }
 836
 837 static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
 838                                         struct dsps_glue *glue)
 839 {
 840         int error;
 841
 842         glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
 843         if (glue->vbus_irq == -EPROBE_DEFER)
 844                 return -EPROBE_DEFER;
 845
 846         if (glue->vbus_irq <= 0) {
 847                 glue->vbus_irq = 0;
 848                 return 0;
 849         }
 850
 851         error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
 852                                           NULL, dsps_vbus_threaded_irq,
 853                                           IRQF_ONESHOT,
 854                                           "vbus", glue);
 855         if (error) {
 856                 glue->vbus_irq = 0;
 857                 return error;
 858         }
 859         dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
 860
 861         return 0;
 862 }
 863
 864 static int dsps_probe(struct platform_device *pdev)
 865 {
 866         const struct of_device_id *match;
 867         const struct dsps_musb_wrapper *wrp;
 868         struct dsps_glue *glue;
 869         int ret;
 870
 871         if (!strcmp(pdev->name, "musb-hdrc"))
 872                 return -ENODEV;
 873
 874         match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
 875         if (!match) {
 876                 dev_err(&pdev->dev, "fail to get matching of_match struct\n");
 877                 return -EINVAL;
 878         }
 879         wrp = match->data;
 880
 881         if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
 882                 dsps_ops.read_fifo = dsps_read_fifo32;
 883
 884         /* allocate glue */
 885         glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
 886         if (!glue)
 887                 return -ENOMEM;
 888
 889         glue->dev = &pdev->dev;
 890         glue->wrp = wrp;
 891         glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
 892         if (!glue->usbss_base)
 893                 return -ENXIO;
 894
 895         if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
 896                 ret = dsps_setup_optional_vbus_irq(pdev, glue);
 897                 if (ret)
 898                         goto err_iounmap;
 899         }
 900
 901         platform_set_drvdata(pdev, glue);
 902         pm_runtime_enable(&pdev->dev);
 903         ret = dsps_create_musb_pdev(glue, pdev);
 904         if (ret)
 905                 goto err;
 906
 907         return 0;
 908
 909 err:
 910         pm_runtime_disable(&pdev->dev);
 911 err_iounmap:
 912         iounmap(glue->usbss_base);
 913         return ret;
 914 }
 915
 916 static int dsps_remove(struct platform_device *pdev)
 917 {
 918         struct dsps_glue *glue = platform_get_drvdata(pdev);
 919
 920         platform_device_unregister(glue->musb);
 921
 922         pm_runtime_disable(&pdev->dev);
 923         iounmap(glue->usbss_base);
 924
 925         return 0;
 926 }
 927
 928 static const struct dsps_musb_wrapper am33xx_driver_data = {
 929         .revision               = 0x00,
 930         .control                = 0x14,
 931         .status                 = 0x18,
 932         .epintr_set             = 0x38,
 933         .epintr_clear           = 0x40,
 934         .epintr_status          = 0x30,
 935         .coreintr_set           = 0x3c,
 936         .coreintr_clear         = 0x44,
 937         .coreintr_status        = 0x34,
 938         .phy_utmi               = 0xe0,
 939         .mode                   = 0xe8,
 940         .tx_mode                = 0x70,
 941         .rx_mode                = 0x74,
 942         .reset                  = 0,
 943         .otg_disable            = 21,
 944         .iddig                  = 8,
 945         .iddig_mux              = 7,
 946         .usb_shift              = 0,
 947         .usb_mask               = 0x1ff,
 948         .usb_bitmap             = (0x1ff << 0),
 949         .drvvbus                = 8,
 950         .txep_shift             = 0,
 951         .txep_mask              = 0xffff,
 952         .txep_bitmap            = (0xffff << 0),
 953         .rxep_shift             = 16,
 954         .rxep_mask              = 0xfffe,
 955         .rxep_bitmap            = (0xfffe << 16),
 956         .poll_timeout           = 2000, /* ms */
 957 };
 958
 959 static const struct of_device_id musb_dsps_of_match[] = {
 960         { .compatible = "ti,musb-am33xx",
 961                 .data = &am33xx_driver_data, },
 962         { .compatible = "ti,musb-dm816",
 963                 .data = &am33xx_driver_data, },
 964         {  },
 965 };
 966 MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
 967
 968 #ifdef CONFIG_PM_SLEEP
 969 static int dsps_suspend(struct device *dev)
 970 {
 971         struct dsps_glue *glue = dev_get_drvdata(dev);
 972         const struct dsps_musb_wrapper *wrp = glue->wrp;
 973         struct musb *musb = platform_get_drvdata(glue->musb);
 974         void __iomem *mbase;
 975         int ret;
 976
 977         if (!musb)
 978                 /* This can happen if the musb device is in -EPROBE_DEFER */
 979                 return 0;
 980
 981         ret = pm_runtime_get_sync(dev);
 982         if (ret < 0) {
 983                 pm_runtime_put_noidle(dev);
 984                 return ret;
 985         }
 986
 987         del_timer_sync(&musb->dev_timer);
 988
 989         mbase = musb->ctrl_base;
 990         glue->context.control = musb_readl(mbase, wrp->control);
 991         glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
 992         glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
 993         glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
 994         glue->context.mode = musb_readl(mbase, wrp->mode);
 995         glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
 996         glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
 997
 998         dsps_dma_controller_suspend(glue);
 999
1000         return 0;
1001 }
1002
1003 static int dsps_resume(struct device *dev)
1004 {
1005         struct dsps_glue *glue = dev_get_drvdata(dev);
1006         const struct dsps_musb_wrapper *wrp = glue->wrp;
1007         struct musb *musb = platform_get_drvdata(glue->musb);
1008         void __iomem *mbase;
1009
1010         if (!musb)
1011                 return 0;
1012
1013         dsps_dma_controller_resume(glue);
1014
1015         mbase = musb->ctrl_base;
1016         musb_writel(mbase, wrp->control, glue->context.control);
1017         musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
1018         musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
1019         musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
1020         musb_writel(mbase, wrp->mode, glue->context.mode);
1021         musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
1022         musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
1023         if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
1024             musb->port_mode == MUSB_OTG)
1025                 dsps_mod_timer(glue, -1);
1026
1027         pm_runtime_put(dev);
1028
1029         return 0;
1030 }
1031 #endif
1032
1033 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
1034
1035 static struct platform_driver dsps_usbss_driver = {
1036         .probe          = dsps_probe,
1037         .remove         = dsps_remove,
1038         .driver         = {
1039                 .name   = "musb-dsps",
1040                 .pm     = &dsps_pm_ops,
1041                 .of_match_table = musb_dsps_of_match,
1042         },
1043 };
1044
1045 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
1046 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
1047 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
1048 MODULE_LICENSE("GPL v2");
1049
1050 module_platform_driver(dsps_usbss_driver);