arch/arm/plat-orion/pcie.c

   1 /*
   2  * arch/arm/plat-orion/pcie.c
   3  *
   4  * Marvell Orion SoC PCIe handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/mbus.h>
  14 #include <asm/mach/pci.h>
  15 #include <asm/plat-orion/pcie.h>
  16
  17 /*
  18  * PCIe unit register offsets.
  19  */
  20 #define PCIE_DEV_ID_OFF         0x0000
  21 #define PCIE_CMD_OFF            0x0004
  22 #define PCIE_DEV_REV_OFF        0x0008
  23 #define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
  24 #define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
  25 #define PCIE_HEADER_LOG_4_OFF   0x0128
  26 #define PCIE_BAR_CTRL_OFF(n)    (0x1804 + ((n - 1) * 4))
  27 #define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
  28 #define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
  29 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  30 #define PCIE_WIN5_CTRL_OFF      0x1880
  31 #define PCIE_WIN5_BASE_OFF      0x1884
  32 #define PCIE_WIN5_REMAP_OFF     0x188c
  33 #define PCIE_CONF_ADDR_OFF      0x18f8
  34 #define  PCIE_CONF_ADDR_EN              0x80000000
  35 #define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  36 #define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
  37 #define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
  38 #define  PCIE_CONF_FUNC(f)              (((f) & 0x3) << 8)
  39 #define PCIE_CONF_DATA_OFF      0x18fc
  40 #define PCIE_MASK_OFF           0x1910
  41 #define PCIE_CTRL_OFF           0x1a00
  42 #define PCIE_STAT_OFF           0x1a04
  43 #define  PCIE_STAT_DEV_OFFS             20
  44 #define  PCIE_STAT_DEV_MASK             0x1f
  45 #define  PCIE_STAT_BUS_OFFS             8
  46 #define  PCIE_STAT_BUS_MASK             0xff
  47 #define  PCIE_STAT_LINK_DOWN            1
  48
  49
  50 u32 __init orion_pcie_dev_id(void __iomem *base)
  51 {
  52         return readl(base + PCIE_DEV_ID_OFF) >> 16;
  53 }
  54
  55 u32 __init orion_pcie_rev(void __iomem *base)
  56 {
  57         return readl(base + PCIE_DEV_REV_OFF) & 0xff;
  58 }
  59
  60 int orion_pcie_link_up(void __iomem *base)
  61 {
  62         return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
  63 }
  64
  65 int orion_pcie_get_local_bus_nr(void __iomem *base)
  66 {
  67         u32 stat = readl(base + PCIE_STAT_OFF);
  68
  69         return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
  70 }
  71
  72 void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
  73 {
  74         u32 stat;
  75
  76         stat = readl(base + PCIE_STAT_OFF);
  77         stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
  78         stat |= nr << PCIE_STAT_BUS_OFFS;
  79         writel(stat, base + PCIE_STAT_OFF);
  80 }
  81
  82 /*
  83  * Setup PCIE BARs and Address Decode Wins:
  84  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  85  * WIN[0-3] -> DRAM bank[0-3]
  86  */
  87 static void __init orion_pcie_setup_wins(void __iomem *base,
  88                                          struct mbus_dram_target_info *dram)
  89 {
  90         u32 size;
  91         int i;
  92
  93         /*
  94          * First, disable and clear BARs and windows.
  95          */
  96         for (i = 1; i <= 2; i++) {
  97                 writel(0, base + PCIE_BAR_CTRL_OFF(i));
  98                 writel(0, base + PCIE_BAR_LO_OFF(i));
  99                 writel(0, base + PCIE_BAR_HI_OFF(i));
 100         }
 101
 102         for (i = 0; i < 5; i++) {
 103                 writel(0, base + PCIE_WIN04_CTRL_OFF(i));
 104                 writel(0, base + PCIE_WIN04_BASE_OFF(i));
 105                 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
 106         }
 107
 108         writel(0, base + PCIE_WIN5_CTRL_OFF);
 109         writel(0, base + PCIE_WIN5_BASE_OFF);
 110         writel(0, base + PCIE_WIN5_REMAP_OFF);
 111
 112         /*
 113          * Setup windows for DDR banks.  Count total DDR size on the fly.
 114          */
 115         size = 0;
 116         for (i = 0; i < dram->num_cs; i++) {
 117                 struct mbus_dram_window *cs = dram->cs + i;
 118
 119                 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
 120                 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
 121                 writel(((cs->size - 1) & 0xffff0000) |
 122                         (cs->mbus_attr << 8) |
 123                         (dram->mbus_dram_target_id << 4) | 1,
 124                                 base + PCIE_WIN04_CTRL_OFF(i));
 125
 126                 size += cs->size;
 127         }
 128
 129         /*
 130          * Setup BAR[1] to all DRAM banks.
 131          */
 132         writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
 133         writel(0, base + PCIE_BAR_HI_OFF(1));
 134         writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
 135 }
 136
 137 void __init orion_pcie_setup(void __iomem *base,
 138                              struct mbus_dram_target_info *dram)
 139 {
 140         u16 cmd;
 141         u32 mask;
 142
 143         /*
 144          * Point PCIe unit MBUS decode windows to DRAM space.
 145          */
 146         orion_pcie_setup_wins(base, dram);
 147
 148         /*
 149          * Master + slave enable.
 150          */
 151         cmd = readw(base + PCIE_CMD_OFF);
 152         cmd |= PCI_COMMAND_IO;
 153         cmd |= PCI_COMMAND_MEMORY;
 154         cmd |= PCI_COMMAND_MASTER;
 155         writew(cmd, base + PCIE_CMD_OFF);
 156
 157         /*
 158          * Enable interrupt lines A-D.
 159          */
 160         mask = readl(base + PCIE_MASK_OFF);
 161         mask |= 0x0f000000;
 162         writel(mask, base + PCIE_MASK_OFF);
 163 }
 164
 165 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
 166                        u32 devfn, int where, int size, u32 *val)
 167 {
 168         writel(PCIE_CONF_BUS(bus->number) |
 169                 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
 170                 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
 171                 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
 172                         base + PCIE_CONF_ADDR_OFF);
 173
 174         *val = readl(base + PCIE_CONF_DATA_OFF);
 175
 176         if (size == 1)
 177                 *val = (*val >> (8 * (where & 3))) & 0xff;
 178         else if (size == 2)
 179                 *val = (*val >> (8 * (where & 3))) & 0xffff;
 180
 181         return PCIBIOS_SUCCESSFUL;
 182 }
 183
 184 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
 185                            u32 devfn, int where, int size, u32 *val)
 186 {
 187         writel(PCIE_CONF_BUS(bus->number) |
 188                 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
 189                 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
 190                 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
 191                         base + PCIE_CONF_ADDR_OFF);
 192
 193         *val = readl(base + PCIE_CONF_DATA_OFF);
 194
 195         if (bus->number != orion_pcie_get_local_bus_nr(base) ||
 196             PCI_FUNC(devfn) != 0)
 197                 *val = readl(base + PCIE_HEADER_LOG_4_OFF);
 198
 199         if (size == 1)
 200                 *val = (*val >> (8 * (where & 3))) & 0xff;
 201         else if (size == 2)
 202                 *val = (*val >> (8 * (where & 3))) & 0xffff;
 203
 204         return PCIBIOS_SUCCESSFUL;
 205 }
 206
 207 int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
 208                           u32 devfn, int where, int size, u32 *val)
 209 {
 210         *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
 211                                 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
 212                                 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
 213                                 PCIE_CONF_REG(where)));
 214
 215         if (size == 1)
 216                 *val = (*val >> (8 * (where & 3))) & 0xff;
 217         else if (size == 2)
 218                 *val = (*val >> (8 * (where & 3))) & 0xffff;
 219
 220         return PCIBIOS_SUCCESSFUL;
 221 }
 222
 223 int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
 224                        u32 devfn, int where, int size, u32 val)
 225 {
 226         int ret = PCIBIOS_SUCCESSFUL;
 227
 228         writel(PCIE_CONF_BUS(bus->number) |
 229                 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
 230                 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
 231                 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
 232                         base + PCIE_CONF_ADDR_OFF);
 233
 234         if (size == 4) {
 235                 writel(val, base + PCIE_CONF_DATA_OFF);
 236         } else if (size == 2) {
 237                 writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
 238         } else if (size == 1) {
 239                 writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
 240         } else {
 241                 ret = PCIBIOS_BAD_REGISTER_NUMBER;
 242         }
 243
 244         return ret;
 245 }