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Merge branch 'v6v7' into devel
[linux/fpc-iii.git] / arch / arm / mach-ep93xx / gpio.c
bloba889fa7c3ba19952b80f189727779c1aa35a4acf
1 /*
2 * linux/arch/arm/mach-ep93xx/gpio.c
3 *
4 * Generic EP93xx GPIO handling
5 *
6 * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/seq_file.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/irq.h>
24
25 #include <mach/hardware.h>
26
27 /*************************************************************************
28 * Interrupt handling for EP93xx on-chip GPIOs
29 *************************************************************************/
30 static unsigned char gpio_int_unmasked[3];
31 static unsigned char gpio_int_enabled[3];
32 static unsigned char gpio_int_type1[3];
33 static unsigned char gpio_int_type2[3];
34 static unsigned char gpio_int_debounce[3];
35
36 /* Port ordering is: A B F */
37 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
38 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
39 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
40 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
41 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
42
43 static void ep93xx_gpio_update_int_params(unsigned port)
44 {
45 BUG_ON(port > 2);
46
47 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
48
49 __raw_writeb(gpio_int_type2[port],
50 EP93XX_GPIO_REG(int_type2_register_offset[port]));
51
52 __raw_writeb(gpio_int_type1[port],
53 EP93XX_GPIO_REG(int_type1_register_offset[port]));
54
55 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
56 EP93XX_GPIO_REG(int_en_register_offset[port]));
57 }
58
59 static inline void ep93xx_gpio_int_mask(unsigned line)
60 {
61 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
62 }
63
64 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
65 {
66 int line = irq_to_gpio(irq);
67 int port = line >> 3;
68 int port_mask = 1 << (line & 7);
69
70 if (enable)
71 gpio_int_debounce[port] |= port_mask;
72 else
73 gpio_int_debounce[port] &= ~port_mask;
74
75 __raw_writeb(gpio_int_debounce[port],
76 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
77 }
78
79 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
80 {
81 unsigned char status;
82 int i;
83
84 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
85 for (i = 0; i < 8; i++) {
86 if (status & (1 << i)) {
87 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
88 generic_handle_irq(gpio_irq);
89 }
90 }
91
92 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
93 for (i = 0; i < 8; i++) {
94 if (status & (1 << i)) {
95 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
96 generic_handle_irq(gpio_irq);
97 }
98 }
99 }
100
101 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
102 {
103 /*
104 * map discontiguous hw irq range to continous sw irq range:
105 *
106 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
107 */
108 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
109 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
110
111 generic_handle_irq(gpio_irq);
112 }
113
114 static void ep93xx_gpio_irq_ack(struct irq_data *d)
115 {
116 int line = irq_to_gpio(d->irq);
117 int port = line >> 3;
118 int port_mask = 1 << (line & 7);
119
120 if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
121 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
122 ep93xx_gpio_update_int_params(port);
123 }
124
125 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
126 }
127
128 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
129 {
130 int line = irq_to_gpio(d->irq);
131 int port = line >> 3;
132 int port_mask = 1 << (line & 7);
133
134 if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
135 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
136
137 gpio_int_unmasked[port] &= ~port_mask;
138 ep93xx_gpio_update_int_params(port);
139
140 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
141 }
142
143 static void ep93xx_gpio_irq_mask(struct irq_data *d)
144 {
145 int line = irq_to_gpio(d->irq);
146 int port = line >> 3;
147
148 gpio_int_unmasked[port] &= ~(1 << (line & 7));
149 ep93xx_gpio_update_int_params(port);
150 }
151
152 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
153 {
154 int line = irq_to_gpio(d->irq);
155 int port = line >> 3;
156
157 gpio_int_unmasked[port] |= 1 << (line & 7);
158 ep93xx_gpio_update_int_params(port);
159 }
160
161 /*
162 * gpio_int_type1 controls whether the interrupt is level (0) or
163 * edge (1) triggered, while gpio_int_type2 controls whether it
164 * triggers on low/falling (0) or high/rising (1).
165 */
166 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
167 {
168 struct irq_desc *desc = irq_desc + d->irq;
169 const int gpio = irq_to_gpio(d->irq);
170 const int port = gpio >> 3;
171 const int port_mask = 1 << (gpio & 7);
172
173 gpio_direction_input(gpio);
174
175 switch (type) {
176 case IRQ_TYPE_EDGE_RISING:
177 gpio_int_type1[port] |= port_mask;
178 gpio_int_type2[port] |= port_mask;
179 desc->handle_irq = handle_edge_irq;
180 break;
181 case IRQ_TYPE_EDGE_FALLING:
182 gpio_int_type1[port] |= port_mask;
183 gpio_int_type2[port] &= ~port_mask;
184 desc->handle_irq = handle_edge_irq;
185 break;
186 case IRQ_TYPE_LEVEL_HIGH:
187 gpio_int_type1[port] &= ~port_mask;
188 gpio_int_type2[port] |= port_mask;
189 desc->handle_irq = handle_level_irq;
190 break;
191 case IRQ_TYPE_LEVEL_LOW:
192 gpio_int_type1[port] &= ~port_mask;
193 gpio_int_type2[port] &= ~port_mask;
194 desc->handle_irq = handle_level_irq;
195 break;
196 case IRQ_TYPE_EDGE_BOTH:
197 gpio_int_type1[port] |= port_mask;
198 /* set initial polarity based on current input level */
199 if (gpio_get_value(gpio))
200 gpio_int_type2[port] &= ~port_mask; /* falling */
201 else
202 gpio_int_type2[port] |= port_mask; /* rising */
203 desc->handle_irq = handle_edge_irq;
204 break;
205 default:
206 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
207 return -EINVAL;
208 }
209
210 gpio_int_enabled[port] |= port_mask;
211
212 desc->status &= ~IRQ_TYPE_SENSE_MASK;
213 desc->status |= type & IRQ_TYPE_SENSE_MASK;
214
215 ep93xx_gpio_update_int_params(port);
216
217 return 0;
218 }
219
220 static struct irq_chip ep93xx_gpio_irq_chip = {
221 .name = "GPIO",
222 .irq_ack = ep93xx_gpio_irq_ack,
223 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
224 .irq_mask = ep93xx_gpio_irq_mask,
225 .irq_unmask = ep93xx_gpio_irq_unmask,
226 .irq_set_type = ep93xx_gpio_irq_type,
227 };
228
229 void __init ep93xx_gpio_init_irq(void)
230 {
231 int gpio_irq;
232
233 for (gpio_irq = gpio_to_irq(0);
234 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
235 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
236 set_irq_handler(gpio_irq, handle_level_irq);
237 set_irq_flags(gpio_irq, IRQF_VALID);
238 }
239
240 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
241 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
242 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
243 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
244 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
245 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
246 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
247 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
248 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
249 }
250
251
252 /*************************************************************************
253 * gpiolib interface for EP93xx on-chip GPIOs
254 *************************************************************************/
255 struct ep93xx_gpio_chip {
256 struct gpio_chip chip;
257
258 void __iomem *data_reg;
259 void __iomem *data_dir_reg;
260 };
261
262 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
263
264 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
265 {
266 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
267 unsigned long flags;
268 u8 v;
269
270 local_irq_save(flags);
271 v = __raw_readb(ep93xx_chip->data_dir_reg);
272 v &= ~(1 << offset);
273 __raw_writeb(v, ep93xx_chip->data_dir_reg);
274 local_irq_restore(flags);
275
276 return 0;
277 }
278
279 static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
280 unsigned offset, int val)
281 {
282 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
283 unsigned long flags;
284 int line;
285 u8 v;
286
287 local_irq_save(flags);
288
289 /* Set the value */
290 v = __raw_readb(ep93xx_chip->data_reg);
291 if (val)
292 v |= (1 << offset);
293 else
294 v &= ~(1 << offset);
295 __raw_writeb(v, ep93xx_chip->data_reg);
296
297 /* Drive as an output */
298 line = chip->base + offset;
299 if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
300 /* Ports A/B/F */
301 ep93xx_gpio_int_mask(line);
302 ep93xx_gpio_update_int_params(line >> 3);
303 }
304
305 v = __raw_readb(ep93xx_chip->data_dir_reg);
306 v |= (1 << offset);
307 __raw_writeb(v, ep93xx_chip->data_dir_reg);
308
309 local_irq_restore(flags);
310
311 return 0;
312 }
313
314 static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
315 {
316 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
317
318 return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
319 }
320
321 static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
322 {
323 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
324 unsigned long flags;
325 u8 v;
326
327 local_irq_save(flags);
328 v = __raw_readb(ep93xx_chip->data_reg);
329 if (val)
330 v |= (1 << offset);
331 else
332 v &= ~(1 << offset);
333 __raw_writeb(v, ep93xx_chip->data_reg);
334 local_irq_restore(flags);
335 }
336
337 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
338 unsigned offset, unsigned debounce)
339 {
340 int gpio = chip->base + offset;
341 int irq = gpio_to_irq(gpio);
342
343 if (irq < 0)
344 return -EINVAL;
345
346 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
347
348 return 0;
349 }
350
351 static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
352 {
353 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
354 u8 data_reg, data_dir_reg;
355 int gpio, i;
356
357 data_reg = __raw_readb(ep93xx_chip->data_reg);
358 data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
359
360 gpio = ep93xx_chip->chip.base;
361 for (i = 0; i < chip->ngpio; i++, gpio++) {
362 int is_out = data_dir_reg & (1 << i);
363
364 seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s",
365 chip->label, i, gpio,
366 gpiochip_is_requested(chip, i) ? : "",
367 is_out ? "out" : "in ",
368 (data_reg & (1 << i)) ? "hi" : "lo");
369
370 if (!is_out) {
371 int irq = gpio_to_irq(gpio);
372 struct irq_desc *desc = irq_desc + irq;
373
374 if (irq >= 0 && desc->action) {
375 char *trigger;
376
377 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
378 case IRQ_TYPE_NONE:
379 trigger = "(default)";
380 break;
381 case IRQ_TYPE_EDGE_FALLING:
382 trigger = "edge-falling";
383 break;
384 case IRQ_TYPE_EDGE_RISING:
385 trigger = "edge-rising";
386 break;
387 case IRQ_TYPE_EDGE_BOTH:
388 trigger = "edge-both";
389 break;
390 case IRQ_TYPE_LEVEL_HIGH:
391 trigger = "level-high";
392 break;
393 case IRQ_TYPE_LEVEL_LOW:
394 trigger = "level-low";
395 break;
396 default:
397 trigger = "?trigger?";
398 break;
399 }
400
401 seq_printf(s, " irq-%d %s%s",
402 irq, trigger,
403 (desc->status & IRQ_WAKEUP)
404 ? " wakeup" : "");
405 }
406 }
407
408 seq_printf(s, "\n");
409 }
410 }
411
412 #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
413 { \
414 .chip = { \
415 .label = name, \
416 .direction_input = ep93xx_gpio_direction_input, \
417 .direction_output = ep93xx_gpio_direction_output, \
418 .get = ep93xx_gpio_get, \
419 .set = ep93xx_gpio_set, \
420 .dbg_show = ep93xx_gpio_dbg_show, \
421 .base = base_gpio, \
422 .ngpio = 8, \
423 }, \
424 .data_reg = EP93XX_GPIO_REG(dr), \
425 .data_dir_reg = EP93XX_GPIO_REG(ddr), \
426 }
427
428 static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
429 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
430 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
431 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
432 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
433 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
434 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
435 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
436 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
437 };
438
439 void __init ep93xx_gpio_init(void)
440 {
441 int i;
442
443 /* Set Ports C, D, E, G, and H for GPIO use */
444 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
445 EP93XX_SYSCON_DEVCFG_GONK |
446 EP93XX_SYSCON_DEVCFG_EONIDE |
447 EP93XX_SYSCON_DEVCFG_GONIDE |
448 EP93XX_SYSCON_DEVCFG_HONIDE);
449
450 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
451 struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
452
453 /*
454 * Ports A, B, and F support input debouncing when
455 * used as interrupts.
456 */
457 if (!strcmp(chip->label, "A") ||
458 !strcmp(chip->label, "B") ||
459 !strcmp(chip->label, "F"))
460 chip->set_debounce = ep93xx_gpio_set_debounce;
461
462 gpiochip_add(chip);
463 }
464 }
Linux with added FPC-III support