arch/arm/mach-msm/include/mach/msm_iomap-8x60.h

   1 /*
   2  * Copyright (C) 2007 Google, Inc.
   3  * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
   4  * Author: Brian Swetland <swetland@google.com>
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  *
  16  * The MSM peripherals are spread all over across 768MB of physical
  17  * space, which makes just having a simple IO_ADDRESS macro to slide
  18  * them into the right virtual location rough.  Instead, we will
  19  * provide a master phys->virt mapping for peripherals here.
  20  *
  21  */
  22
  23 #ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
  24 #define __ASM_ARCH_MSM_IOMAP_8X60_H
  25
  26 /* Physical base address and size of peripherals.
  27  * Ordered by the virtual base addresses they will be mapped at.
  28  *
  29  * MSM_VIC_BASE must be an value that can be loaded via a "mov"
  30  * instruction, otherwise entry-macro.S will not compile.
  31  *
  32  * If you add or remove entries here, you'll want to edit the
  33  * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
  34  * changes.
  35  *
  36  */
  37
  38 #define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
  39 #define MSM_QGIC_DIST_PHYS      0x02080000
  40 #define MSM_QGIC_DIST_SIZE      SZ_4K
  41
  42 #define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
  43 #define MSM_QGIC_CPU_PHYS       0x02081000
  44 #define MSM_QGIC_CPU_SIZE       SZ_4K
  45
  46 #define MSM_ACC_BASE            IOMEM(0xF0002000)
  47 #define MSM_ACC_PHYS            0x02001000
  48 #define MSM_ACC_SIZE            SZ_4K
  49
  50 #define MSM_GCC_BASE            IOMEM(0xF0003000)
  51 #define MSM_GCC_PHYS            0x02082000
  52 #define MSM_GCC_SIZE            SZ_4K
  53
  54 #define MSM_TLMM_BASE           IOMEM(0xF0004000)
  55 #define MSM_TLMM_PHYS           0x00800000
  56 #define MSM_TLMM_SIZE           SZ_16K
  57
  58 #define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
  59 #define MSM_SHARED_RAM_SIZE     SZ_1M
  60
  61 #define MSM_TMR_BASE            IOMEM(0xF0200000)
  62 #define MSM_TMR_PHYS            0x02000000
  63 #define MSM_TMR_SIZE            SZ_4K
  64
  65 #define MSM_TMR0_BASE           IOMEM(0xF0201000)
  66 #define MSM_TMR0_PHYS           0x02040000
  67 #define MSM_TMR0_SIZE           SZ_4K
  68
  69 #define MSM_GPT_BASE            (MSM_TMR_BASE + 0x4)
  70 #define MSM_DGT_BASE            (MSM_TMR_BASE + 0x24)
  71
  72 #define MSM_IOMMU_JPEGD_PHYS    0x07300000
  73 #define MSM_IOMMU_JPEGD_SIZE    SZ_1M
  74
  75 #define MSM_IOMMU_VPE_PHYS      0x07400000
  76 #define MSM_IOMMU_VPE_SIZE      SZ_1M
  77
  78 #define MSM_IOMMU_MDP0_PHYS     0x07500000
  79 #define MSM_IOMMU_MDP0_SIZE     SZ_1M
  80
  81 #define MSM_IOMMU_MDP1_PHYS     0x07600000
  82 #define MSM_IOMMU_MDP1_SIZE     SZ_1M
  83
  84 #define MSM_IOMMU_ROT_PHYS      0x07700000
  85 #define MSM_IOMMU_ROT_SIZE      SZ_1M
  86
  87 #define MSM_IOMMU_IJPEG_PHYS    0x07800000
  88 #define MSM_IOMMU_IJPEG_SIZE    SZ_1M
  89
  90 #define MSM_IOMMU_VFE_PHYS      0x07900000
  91 #define MSM_IOMMU_VFE_SIZE      SZ_1M
  92
  93 #define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
  94 #define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
  95
  96 #define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
  97 #define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
  98
  99 #define MSM_IOMMU_GFX3D_PHYS    0x07C00000
 100 #define MSM_IOMMU_GFX3D_SIZE    SZ_1M
 101
 102 #define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
 103 #define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
 104
 105 #define MSM_IOMMU_GFX2D1_PHYS   0x07E00000
 106 #define MSM_IOMMU_GFX2D1_SIZE   SZ_1M
 107
 108 #endif