arch/arm/mach-mx3/mach-mx31ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/clk.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/gpio.h>
  22 #include <linux/i2c.h>
  23 #include <linux/irq.h>
  24
  25 #include <asm/mach-types.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/time.h>
  28 #include <asm/memory.h>
  29 #include <asm/mach/map.h>
  30 #include <mach/common.h>
  31 #include <mach/board-mx31ads.h>
  32 #include <mach/iomux-mx3.h>
  33
  34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
  35 #include <linux/mfd/wm8350/audio.h>
  36 #include <linux/mfd/wm8350/core.h>
  37 #include <linux/mfd/wm8350/pmic.h>
  38 #endif
  39
  40 #include "devices-imx31.h"
  41 #include "devices.h"
  42
  43 /* PBC Board interrupt status register */
  44 #define PBC_INTSTATUS           0x000016
  45
  46 /* PBC Board interrupt current status register */
  47 #define PBC_INTCURR_STATUS      0x000018
  48
  49 /* PBC Interrupt mask register set address */
  50 #define PBC_INTMASK_SET         0x00001A
  51
  52 /* PBC Interrupt mask register clear address */
  53 #define PBC_INTMASK_CLEAR       0x00001C
  54
  55 /* External UART A */
  56 #define PBC_SC16C652_UARTA      0x010000
  57
  58 /* External UART B */
  59 #define PBC_SC16C652_UARTB      0x010010
  60
  61 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
  62 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
  63 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
  64 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
  65
  66 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
  67
  68 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
  69 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
  70
  71 #define MXC_MAX_EXP_IO_LINES    16
  72 /*
  73  * This file contains the board-specific initialization routines.
  74  */
  75
  76 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  77 /*!
  78  * The serial port definition structure.
  79  */
  80 static struct plat_serial8250_port serial_platform_data[] = {
  81         {
  82                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
  83                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
  84                 .irq      = EXPIO_INT_XUART_INTA,
  85                 .uartclk  = 14745600,
  86                 .regshift = 0,
  87                 .iotype   = UPIO_MEM,
  88                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  89         }, {
  90                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
  91                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
  92                 .irq      = EXPIO_INT_XUART_INTB,
  93                 .uartclk  = 14745600,
  94                 .regshift = 0,
  95                 .iotype   = UPIO_MEM,
  96                 .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
  97         },
  98         {},
  99 };
 100
 101 static struct platform_device serial_device = {
 102         .name   = "serial8250",
 103         .id     = 0,
 104         .dev    = {
 105                 .platform_data = serial_platform_data,
 106         },
 107 };
 108
 109 static int __init mxc_init_extuart(void)
 110 {
 111         return platform_device_register(&serial_device);
 112 }
 113 #else
 114 static inline int mxc_init_extuart(void)
 115 {
 116         return 0;
 117 }
 118 #endif
 119
 120 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 121 static const struct imxuart_platform_data uart_pdata __initconst = {
 122         .flags = IMXUART_HAVE_RTSCTS,
 123 };
 124
 125 static unsigned int uart_pins[] = {
 126         MX31_PIN_CTS1__CTS1,
 127         MX31_PIN_RTS1__RTS1,
 128         MX31_PIN_TXD1__TXD1,
 129         MX31_PIN_RXD1__RXD1
 130 };
 131
 132 static inline void mxc_init_imx_uart(void)
 133 {
 134         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
 135         imx31_add_imx_uart0(&uart_pdata);
 136 }
 137 #else /* !SERIAL_IMX */
 138 static inline void mxc_init_imx_uart(void)
 139 {
 140 }
 141 #endif /* !SERIAL_IMX */
 142
 143 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 144 {
 145         u32 imr_val;
 146         u32 int_valid;
 147         u32 expio_irq;
 148
 149         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
 150         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 151
 152         expio_irq = MXC_EXP_IO_BASE;
 153         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
 154                 if ((int_valid & 1) == 0)
 155                         continue;
 156
 157                 generic_handle_irq(expio_irq);
 158         }
 159 }
 160
 161 /*
 162  * Disable an expio pin's interrupt by setting the bit in the imr.
 163  * @param irq           an expio virtual irq number
 164  */
 165 static void expio_mask_irq(struct irq_data *d)
 166 {
 167         u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 168         /* mask the interrupt */
 169         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
 170         __raw_readw(PBC_INTMASK_CLEAR_REG);
 171 }
 172
 173 /*
 174  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 175  * @param irq           an expanded io virtual irq number
 176  */
 177 static void expio_ack_irq(struct irq_data *d)
 178 {
 179         u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 180         /* clear the interrupt status */
 181         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 182 }
 183
 184 /*
 185  * Enable a expio pin's interrupt by clearing the bit in the imr.
 186  * @param irq           a expio virtual irq number
 187  */
 188 static void expio_unmask_irq(struct irq_data *d)
 189 {
 190         u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
 191         /* unmask the interrupt */
 192         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 193 }
 194
 195 static struct irq_chip expio_irq_chip = {
 196         .name = "EXPIO(CPLD)",
 197         .irq_ack = expio_ack_irq,
 198         .irq_mask = expio_mask_irq,
 199         .irq_unmask = expio_unmask_irq,
 200 };
 201
 202 static void __init mx31ads_init_expio(void)
 203 {
 204         int i;
 205
 206         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 207
 208         /*
 209          * Configure INT line as GPIO input
 210          */
 211         mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
 212
 213         /* disable the interrupt and clear the status */
 214         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
 215         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
 216         for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
 217              i++) {
 218                 set_irq_chip(i, &expio_irq_chip);
 219                 set_irq_handler(i, handle_level_irq);
 220                 set_irq_flags(i, IRQF_VALID);
 221         }
 222         set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
 223         set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 224 }
 225
 226 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 227 /* This section defines setup for the Wolfson Microelectronics
 228  * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 229  * regulator definitions may be shared with them, but for now they can
 230  * only be used with this board so would generate warnings about
 231  * unused statics and some of the configuration is specific to this
 232  * module.
 233  */
 234
 235 /* CPU */
 236 static struct regulator_consumer_supply sw1a_consumers[] = {
 237         {
 238                 .supply = "cpu_vcc",
 239         }
 240 };
 241
 242 static struct regulator_init_data sw1a_data = {
 243         .constraints = {
 244                 .name = "SW1A",
 245                 .min_uV = 1275000,
 246                 .max_uV = 1600000,
 247                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 248                                   REGULATOR_CHANGE_MODE,
 249                 .valid_modes_mask = REGULATOR_MODE_NORMAL |
 250                                     REGULATOR_MODE_FAST,
 251                 .state_mem = {
 252                          .uV = 1400000,
 253                          .mode = REGULATOR_MODE_NORMAL,
 254                          .enabled = 1,
 255                  },
 256                 .initial_state = PM_SUSPEND_MEM,
 257                 .always_on = 1,
 258                 .boot_on = 1,
 259         },
 260         .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
 261         .consumer_supplies = sw1a_consumers,
 262 };
 263
 264 /* System IO - High */
 265 static struct regulator_init_data viohi_data = {
 266         .constraints = {
 267                 .name = "VIOHO",
 268                 .min_uV = 2800000,
 269                 .max_uV = 2800000,
 270                 .state_mem = {
 271                          .uV = 2800000,
 272                          .mode = REGULATOR_MODE_NORMAL,
 273                          .enabled = 1,
 274                  },
 275                 .initial_state = PM_SUSPEND_MEM,
 276                 .always_on = 1,
 277                 .boot_on = 1,
 278         },
 279 };
 280
 281 /* System IO - Low */
 282 static struct regulator_init_data violo_data = {
 283         .constraints = {
 284                 .name = "VIOLO",
 285                 .min_uV = 1800000,
 286                 .max_uV = 1800000,
 287                 .state_mem = {
 288                          .uV = 1800000,
 289                          .mode = REGULATOR_MODE_NORMAL,
 290                          .enabled = 1,
 291                  },
 292                 .initial_state = PM_SUSPEND_MEM,
 293                 .always_on = 1,
 294                 .boot_on = 1,
 295         },
 296 };
 297
 298 /* DDR RAM */
 299 static struct regulator_init_data sw2a_data = {
 300         .constraints = {
 301                 .name = "SW2A",
 302                 .min_uV = 1800000,
 303                 .max_uV = 1800000,
 304                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 305                 .state_mem = {
 306                          .uV = 1800000,
 307                          .mode = REGULATOR_MODE_NORMAL,
 308                          .enabled = 1,
 309                  },
 310                 .state_disk = {
 311                          .mode = REGULATOR_MODE_NORMAL,
 312                          .enabled = 0,
 313                  },
 314                 .always_on = 1,
 315                 .boot_on = 1,
 316                 .initial_state = PM_SUSPEND_MEM,
 317         },
 318 };
 319
 320 static struct regulator_init_data ldo1_data = {
 321         .constraints = {
 322                 .name = "VCAM/VMMC1/VMMC2",
 323                 .min_uV = 2800000,
 324                 .max_uV = 2800000,
 325                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 326                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 327                 .apply_uV = 1,
 328         },
 329 };
 330
 331 static struct regulator_consumer_supply ldo2_consumers[] = {
 332         { .supply = "AVDD", .dev_name = "1-001a" },
 333         { .supply = "HPVDD", .dev_name = "1-001a" },
 334 };
 335
 336 /* CODEC and SIM */
 337 static struct regulator_init_data ldo2_data = {
 338         .constraints = {
 339                 .name = "VESIM/VSIM/AVDD",
 340                 .min_uV = 3300000,
 341                 .max_uV = 3300000,
 342                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 343                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 344                 .apply_uV = 1,
 345         },
 346         .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
 347         .consumer_supplies = ldo2_consumers,
 348 };
 349
 350 /* General */
 351 static struct regulator_init_data vdig_data = {
 352         .constraints = {
 353                 .name = "VDIG",
 354                 .min_uV = 1500000,
 355                 .max_uV = 1500000,
 356                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 357                 .apply_uV = 1,
 358                 .always_on = 1,
 359                 .boot_on = 1,
 360         },
 361 };
 362
 363 /* Tranceivers */
 364 static struct regulator_init_data ldo4_data = {
 365         .constraints = {
 366                 .name = "VRF1/CVDD_2.775",
 367                 .min_uV = 2500000,
 368                 .max_uV = 2500000,
 369                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
 370                 .apply_uV = 1,
 371                 .always_on = 1,
 372                 .boot_on = 1,
 373         },
 374 };
 375
 376 static struct wm8350_led_platform_data wm8350_led_data = {
 377         .name            = "wm8350:white",
 378         .default_trigger = "heartbeat",
 379         .max_uA          = 27899,
 380 };
 381
 382 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
 383         .vmid_discharge_msecs = 1000,
 384         .drain_msecs = 30,
 385         .cap_discharge_msecs = 700,
 386         .vmid_charge_msecs = 700,
 387         .vmid_s_curve = WM8350_S_CURVE_SLOW,
 388         .dis_out4 = WM8350_DISCHARGE_SLOW,
 389         .dis_out3 = WM8350_DISCHARGE_SLOW,
 390         .dis_out2 = WM8350_DISCHARGE_SLOW,
 391         .dis_out1 = WM8350_DISCHARGE_SLOW,
 392         .vroi_out4 = WM8350_TIE_OFF_500R,
 393         .vroi_out3 = WM8350_TIE_OFF_500R,
 394         .vroi_out2 = WM8350_TIE_OFF_500R,
 395         .vroi_out1 = WM8350_TIE_OFF_500R,
 396         .vroi_enable = 0,
 397         .codec_current_on = WM8350_CODEC_ISEL_1_0,
 398         .codec_current_standby = WM8350_CODEC_ISEL_0_5,
 399         .codec_current_charge = WM8350_CODEC_ISEL_1_5,
 400 };
 401
 402 static int mx31_wm8350_init(struct wm8350 *wm8350)
 403 {
 404         wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
 405                            WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
 406                            WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
 407                            WM8350_GPIO_DEBOUNCE_ON);
 408
 409         wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
 410                            WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
 411                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 412                            WM8350_GPIO_DEBOUNCE_ON);
 413
 414         wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
 415                            WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
 416                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 417                            WM8350_GPIO_DEBOUNCE_OFF);
 418
 419         wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
 420                            WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
 421                            WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
 422                            WM8350_GPIO_DEBOUNCE_OFF);
 423
 424         wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
 425                            WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
 426                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 427                            WM8350_GPIO_DEBOUNCE_OFF);
 428
 429         wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
 430                            WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 431                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 432                            WM8350_GPIO_DEBOUNCE_OFF);
 433
 434         wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
 435                            WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
 436                            WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
 437                            WM8350_GPIO_DEBOUNCE_OFF);
 438
 439         wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
 440         wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
 441         wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
 442         wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
 443         wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
 444         wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
 445         wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
 446         wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
 447
 448         /* LEDs */
 449         wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
 450                              WM8350_DC5_ERRACT_SHUTDOWN_CONV);
 451         wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
 452                                WM8350_ISINK_FLASH_DISABLE,
 453                                WM8350_ISINK_FLASH_TRIG_BIT,
 454                                WM8350_ISINK_FLASH_DUR_32MS,
 455                                WM8350_ISINK_FLASH_ON_INSTANT,
 456                                WM8350_ISINK_FLASH_OFF_INSTANT,
 457                                WM8350_ISINK_FLASH_MODE_EN);
 458         wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
 459                                WM8350_ISINK_MODE_BOOST,
 460                                WM8350_ISINK_ILIM_NORMAL,
 461                                WM8350_DC5_RMP_20V,
 462                                WM8350_DC5_FBSRC_ISINKA);
 463         wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
 464                             &wm8350_led_data);
 465
 466         wm8350->codec.platform_data = &imx32ads_wm8350_setup;
 467
 468         regulator_has_full_constraints();
 469
 470         return 0;
 471 }
 472
 473 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 474         .init = mx31_wm8350_init,
 475         .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
 476 };
 477 #endif
 478
 479 #if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
 480 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 481 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 482         {
 483                 I2C_BOARD_INFO("wm8350", 0x1a),
 484                 .platform_data = &mx31_wm8350_pdata,
 485                 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 486         },
 487 #endif
 488 };
 489
 490 static void mxc_init_i2c(void)
 491 {
 492         i2c_register_board_info(1, mx31ads_i2c1_devices,
 493                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 494
 495         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
 496         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 497
 498         imx31_add_imx_i2c1(NULL);
 499 }
 500 #else
 501 static void mxc_init_i2c(void)
 502 {
 503 }
 504 #endif
 505
 506 static unsigned int ssi_pins[] = {
 507         MX31_PIN_SFS5__SFS5,
 508         MX31_PIN_SCK5__SCK5,
 509         MX31_PIN_SRXD5__SRXD5,
 510         MX31_PIN_STXD5__STXD5,
 511 };
 512
 513 static void mxc_init_audio(void)
 514 {
 515         imx31_add_imx_ssi(0, NULL);
 516         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 517 }
 518
 519 /*!
 520  * This structure defines static mappings for the i.MX31ADS board.
 521  */
 522 static struct map_desc mx31ads_io_desc[] __initdata = {
 523         {
 524                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
 525                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
 526                 .length         = MX31_CS4_SIZE / 2,
 527                 .type           = MT_DEVICE
 528         },
 529 };
 530
 531 /*!
 532  * Set up static virtual mappings.
 533  */
 534 static void __init mx31ads_map_io(void)
 535 {
 536         mx31_map_io();
 537         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 538 }
 539
 540 static void __init mx31ads_init_irq(void)
 541 {
 542         mx31_init_irq();
 543         mx31ads_init_expio();
 544 }
 545
 546 /*!
 547  * Board specific initialization.
 548  */
 549 static void __init mxc_board_init(void)
 550 {
 551         mxc_init_extuart();
 552         mxc_init_imx_uart();
 553         mxc_init_i2c();
 554         mxc_init_audio();
 555 }
 556
 557 static void __init mx31ads_timer_init(void)
 558 {
 559         mx31_clocks_init(26000000);
 560 }
 561
 562 static struct sys_timer mx31ads_timer = {
 563         .init   = mx31ads_timer_init,
 564 };
 565
 566 /*
 567  * The following uses standard kernel macros defined in arch.h in order to
 568  * initialize __mach_desc_MX31ADS data structure.
 569  */
 570 MACHINE_START(MX31ADS, "Freescale MX31ADS")
 571         /* Maintainer: Freescale Semiconductor, Inc. */
 572         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
 573         .map_io         = mx31ads_map_io,
 574         .init_irq       = mx31ads_init_irq,
 575         .init_machine   = mxc_board_init,
 576         .timer          = &mx31ads_timer,
 577 MACHINE_END