Merge branch 'v6v7' into devel
[linux/fpc-iii.git] / arch / arm / mach-pxa / time.c
blobe7f64d9b4f2d02a084f9208697fc93d84b6b15f8
1 /*
2 * arch/arm/mach-pxa/time.c
4 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/clockchips.h>
19 #include <linux/sched.h>
21 #include <asm/div64.h>
22 #include <asm/mach/irq.h>
23 #include <asm/mach/time.h>
24 #include <asm/sched_clock.h>
25 #include <mach/regs-ost.h>
28 * This is PXA's sched_clock implementation. This has a resolution
29 * of at least 308 ns and a maximum value of 208 days.
31 * The return value is guaranteed to be monotonic in that range as
32 * long as there is always less than 582 seconds between successive
33 * calls to sched_clock() which should always be the case in practice.
35 static DEFINE_CLOCK_DATA(cd);
37 unsigned long long notrace sched_clock(void)
39 u32 cyc = OSCR;
40 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
43 static void notrace pxa_update_sched_clock(void)
45 u32 cyc = OSCR;
46 update_sched_clock(&cd, cyc, (u32)~0);
50 #define MIN_OSCR_DELTA 16
52 static irqreturn_t
53 pxa_ost0_interrupt(int irq, void *dev_id)
55 struct clock_event_device *c = dev_id;
57 /* Disarm the compare/match, signal the event. */
58 OIER &= ~OIER_E0;
59 OSSR = OSSR_M0;
60 c->event_handler(c);
62 return IRQ_HANDLED;
65 static int
66 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
68 unsigned long next, oscr;
70 OIER |= OIER_E0;
71 next = OSCR + delta;
72 OSMR0 = next;
73 oscr = OSCR;
75 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
78 static void
79 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
81 switch (mode) {
82 case CLOCK_EVT_MODE_ONESHOT:
83 OIER &= ~OIER_E0;
84 OSSR = OSSR_M0;
85 break;
87 case CLOCK_EVT_MODE_UNUSED:
88 case CLOCK_EVT_MODE_SHUTDOWN:
89 /* initializing, released, or preparing for suspend */
90 OIER &= ~OIER_E0;
91 OSSR = OSSR_M0;
92 break;
94 case CLOCK_EVT_MODE_RESUME:
95 case CLOCK_EVT_MODE_PERIODIC:
96 break;
100 static struct clock_event_device ckevt_pxa_osmr0 = {
101 .name = "osmr0",
102 .features = CLOCK_EVT_FEAT_ONESHOT,
103 .shift = 32,
104 .rating = 200,
105 .set_next_event = pxa_osmr0_set_next_event,
106 .set_mode = pxa_osmr0_set_mode,
109 static cycle_t pxa_read_oscr(struct clocksource *cs)
111 return OSCR;
114 static struct clocksource cksrc_pxa_oscr0 = {
115 .name = "oscr0",
116 .rating = 200,
117 .read = pxa_read_oscr,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
122 static struct irqaction pxa_ost0_irq = {
123 .name = "ost0",
124 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
125 .handler = pxa_ost0_interrupt,
126 .dev_id = &ckevt_pxa_osmr0,
129 static void __init pxa_timer_init(void)
131 unsigned long clock_tick_rate = get_clock_tick_rate();
133 OIER = 0;
134 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
136 init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
138 ckevt_pxa_osmr0.mult =
139 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
140 ckevt_pxa_osmr0.max_delta_ns =
141 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
142 ckevt_pxa_osmr0.min_delta_ns =
143 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
144 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
146 setup_irq(IRQ_OST0, &pxa_ost0_irq);
148 clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate);
149 clockevents_register_device(&ckevt_pxa_osmr0);
152 #ifdef CONFIG_PM
153 static unsigned long osmr[4], oier, oscr;
155 static void pxa_timer_suspend(void)
157 osmr[0] = OSMR0;
158 osmr[1] = OSMR1;
159 osmr[2] = OSMR2;
160 osmr[3] = OSMR3;
161 oier = OIER;
162 oscr = OSCR;
165 static void pxa_timer_resume(void)
168 * Ensure that we have at least MIN_OSCR_DELTA between match
169 * register 0 and the OSCR, to guarantee that we will receive
170 * the one-shot timer interrupt. We adjust OSMR0 in preference
171 * to OSCR to guarantee that OSCR is monotonically incrementing.
173 if (osmr[0] - oscr < MIN_OSCR_DELTA)
174 osmr[0] += MIN_OSCR_DELTA;
176 OSMR0 = osmr[0];
177 OSMR1 = osmr[1];
178 OSMR2 = osmr[2];
179 OSMR3 = osmr[3];
180 OIER = oier;
181 OSCR = oscr;
183 #else
184 #define pxa_timer_suspend NULL
185 #define pxa_timer_resume NULL
186 #endif
188 struct sys_timer pxa_timer = {
189 .init = pxa_timer_init,
190 .suspend = pxa_timer_suspend,
191 .resume = pxa_timer_resume,