arch/arm/mach-s5pv210/gpiolib.c

   1 /* linux/arch/arm/mach-s5pv210/gpiolib.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - GPIOlib support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/gpio.h>
  17 #include <plat/gpio-core.h>
  18 #include <plat/gpio-cfg.h>
  19 #include <plat/gpio-cfg-helpers.h>
  20 #include <mach/map.h>
  21
  22 static struct s3c_gpio_cfg gpio_cfg = {
  23         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  24         .set_pull       = s3c_gpio_setpull_updown,
  25         .get_pull       = s3c_gpio_getpull_updown,
  26 };
  27
  28 static struct s3c_gpio_cfg gpio_cfg_noint = {
  29         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  30         .set_pull       = s3c_gpio_setpull_updown,
  31         .get_pull       = s3c_gpio_getpull_updown,
  32 };
  33
  34 /* GPIO bank's base address given the index of the bank in the
  35  * list of all gpio banks.
  36  */
  37 #define S5PV210_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
  38
  39 /*
  40  * Following are the gpio banks in v210.
  41  *
  42  * The 'config' member when left to NULL, is initialized to the default
  43  * structure gpio_cfg in the init function below.
  44  *
  45  * The 'base' member is also initialized in the init function below.
  46  * Note: The initialization of 'base' member of s3c_gpio_chip structure
  47  * uses the above macro and depends on the banks being listed in order here.
  48  */
  49 static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
  50         {
  51                 .chip   = {
  52                         .base   = S5PV210_GPA0(0),
  53                         .ngpio  = S5PV210_GPIO_A0_NR,
  54                         .label  = "GPA0",
  55                 },
  56         }, {
  57                 .chip   = {
  58                         .base   = S5PV210_GPA1(0),
  59                         .ngpio  = S5PV210_GPIO_A1_NR,
  60                         .label  = "GPA1",
  61                 },
  62         }, {
  63                 .chip   = {
  64                         .base   = S5PV210_GPB(0),
  65                         .ngpio  = S5PV210_GPIO_B_NR,
  66                         .label  = "GPB",
  67                 },
  68         }, {
  69                 .chip   = {
  70                         .base   = S5PV210_GPC0(0),
  71                         .ngpio  = S5PV210_GPIO_C0_NR,
  72                         .label  = "GPC0",
  73                 },
  74         }, {
  75                 .chip   = {
  76                         .base   = S5PV210_GPC1(0),
  77                         .ngpio  = S5PV210_GPIO_C1_NR,
  78                         .label  = "GPC1",
  79                 },
  80         }, {
  81                 .chip   = {
  82                         .base   = S5PV210_GPD0(0),
  83                         .ngpio  = S5PV210_GPIO_D0_NR,
  84                         .label  = "GPD0",
  85                 },
  86         }, {
  87                 .chip   = {
  88                         .base   = S5PV210_GPD1(0),
  89                         .ngpio  = S5PV210_GPIO_D1_NR,
  90                         .label  = "GPD1",
  91                 },
  92         }, {
  93                 .chip   = {
  94                         .base   = S5PV210_GPE0(0),
  95                         .ngpio  = S5PV210_GPIO_E0_NR,
  96                         .label  = "GPE0",
  97                 },
  98         }, {
  99                 .chip   = {
 100                         .base   = S5PV210_GPE1(0),
 101                         .ngpio  = S5PV210_GPIO_E1_NR,
 102                         .label  = "GPE1",
 103                 },
 104         }, {
 105                 .chip   = {
 106                         .base   = S5PV210_GPF0(0),
 107                         .ngpio  = S5PV210_GPIO_F0_NR,
 108                         .label  = "GPF0",
 109                 },
 110         }, {
 111                 .chip   = {
 112                         .base   = S5PV210_GPF1(0),
 113                         .ngpio  = S5PV210_GPIO_F1_NR,
 114                         .label  = "GPF1",
 115                 },
 116         }, {
 117                 .chip   = {
 118                         .base   = S5PV210_GPF2(0),
 119                         .ngpio  = S5PV210_GPIO_F2_NR,
 120                         .label  = "GPF2",
 121                 },
 122         }, {
 123                 .chip   = {
 124                         .base   = S5PV210_GPF3(0),
 125                         .ngpio  = S5PV210_GPIO_F3_NR,
 126                         .label  = "GPF3",
 127                 },
 128         }, {
 129                 .chip   = {
 130                         .base   = S5PV210_GPG0(0),
 131                         .ngpio  = S5PV210_GPIO_G0_NR,
 132                         .label  = "GPG0",
 133                 },
 134         }, {
 135                 .chip   = {
 136                         .base   = S5PV210_GPG1(0),
 137                         .ngpio  = S5PV210_GPIO_G1_NR,
 138                         .label  = "GPG1",
 139                 },
 140         }, {
 141                 .chip   = {
 142                         .base   = S5PV210_GPG2(0),
 143                         .ngpio  = S5PV210_GPIO_G2_NR,
 144                         .label  = "GPG2",
 145                 },
 146         }, {
 147                 .chip   = {
 148                         .base   = S5PV210_GPG3(0),
 149                         .ngpio  = S5PV210_GPIO_G3_NR,
 150                         .label  = "GPG3",
 151                 },
 152         }, {
 153                 .config = &gpio_cfg_noint,
 154                 .chip   = {
 155                         .base   = S5PV210_GPI(0),
 156                         .ngpio  = S5PV210_GPIO_I_NR,
 157                         .label  = "GPI",
 158                 },
 159         }, {
 160                 .chip   = {
 161                         .base   = S5PV210_GPJ0(0),
 162                         .ngpio  = S5PV210_GPIO_J0_NR,
 163                         .label  = "GPJ0",
 164                 },
 165         }, {
 166                 .chip   = {
 167                         .base   = S5PV210_GPJ1(0),
 168                         .ngpio  = S5PV210_GPIO_J1_NR,
 169                         .label  = "GPJ1",
 170                 },
 171         }, {
 172                 .chip   = {
 173                         .base   = S5PV210_GPJ2(0),
 174                         .ngpio  = S5PV210_GPIO_J2_NR,
 175                         .label  = "GPJ2",
 176                 },
 177         }, {
 178                 .chip   = {
 179                         .base   = S5PV210_GPJ3(0),
 180                         .ngpio  = S5PV210_GPIO_J3_NR,
 181                         .label  = "GPJ3",
 182                 },
 183         }, {
 184                 .chip   = {
 185                         .base   = S5PV210_GPJ4(0),
 186                         .ngpio  = S5PV210_GPIO_J4_NR,
 187                         .label  = "GPJ4",
 188                 },
 189         }, {
 190                 .config = &gpio_cfg_noint,
 191                 .chip   = {
 192                         .base   = S5PV210_MP01(0),
 193                         .ngpio  = S5PV210_GPIO_MP01_NR,
 194                         .label  = "MP01",
 195                 },
 196         }, {
 197                 .config = &gpio_cfg_noint,
 198                 .chip   = {
 199                         .base   = S5PV210_MP02(0),
 200                         .ngpio  = S5PV210_GPIO_MP02_NR,
 201                         .label  = "MP02",
 202                 },
 203         }, {
 204                 .config = &gpio_cfg_noint,
 205                 .chip   = {
 206                         .base   = S5PV210_MP03(0),
 207                         .ngpio  = S5PV210_GPIO_MP03_NR,
 208                         .label  = "MP03",
 209                 },
 210         }, {
 211                 .config = &gpio_cfg_noint,
 212                 .chip   = {
 213                         .base   = S5PV210_MP04(0),
 214                         .ngpio  = S5PV210_GPIO_MP04_NR,
 215                         .label  = "MP04",
 216                 },
 217         }, {
 218                 .config = &gpio_cfg_noint,
 219                 .chip   = {
 220                         .base   = S5PV210_MP05(0),
 221                         .ngpio  = S5PV210_GPIO_MP05_NR,
 222                         .label  = "MP05",
 223                 },
 224         }, {
 225                 .base   = (S5P_VA_GPIO + 0xC00),
 226                 .config = &gpio_cfg_noint,
 227                 .irq_base = IRQ_EINT(0),
 228                 .chip   = {
 229                         .base   = S5PV210_GPH0(0),
 230                         .ngpio  = S5PV210_GPIO_H0_NR,
 231                         .label  = "GPH0",
 232                         .to_irq = samsung_gpiolib_to_irq,
 233                 },
 234         }, {
 235                 .base   = (S5P_VA_GPIO + 0xC20),
 236                 .config = &gpio_cfg_noint,
 237                 .irq_base = IRQ_EINT(8),
 238                 .chip   = {
 239                         .base   = S5PV210_GPH1(0),
 240                         .ngpio  = S5PV210_GPIO_H1_NR,
 241                         .label  = "GPH1",
 242                         .to_irq = samsung_gpiolib_to_irq,
 243                 },
 244         }, {
 245                 .base   = (S5P_VA_GPIO + 0xC40),
 246                 .config = &gpio_cfg_noint,
 247                 .irq_base = IRQ_EINT(16),
 248                 .chip   = {
 249                         .base   = S5PV210_GPH2(0),
 250                         .ngpio  = S5PV210_GPIO_H2_NR,
 251                         .label  = "GPH2",
 252                         .to_irq = samsung_gpiolib_to_irq,
 253                 },
 254         }, {
 255                 .base   = (S5P_VA_GPIO + 0xC60),
 256                 .config = &gpio_cfg_noint,
 257                 .irq_base = IRQ_EINT(24),
 258                 .chip   = {
 259                         .base   = S5PV210_GPH3(0),
 260                         .ngpio  = S5PV210_GPIO_H3_NR,
 261                         .label  = "GPH3",
 262                         .to_irq = samsung_gpiolib_to_irq,
 263                 },
 264         },
 265 };
 266
 267 static __init int s5pv210_gpiolib_init(void)
 268 {
 269         struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
 270         int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
 271         int gpioint_group = 0;
 272         int i = 0;
 273
 274         for (i = 0; i < nr_chips; i++, chip++) {
 275                 if (chip->config == NULL) {
 276                         chip->config = &gpio_cfg;
 277                         chip->group = gpioint_group++;
 278                 }
 279                 if (chip->base == NULL)
 280                         chip->base = S5PV210_BANK_BASE(i);
 281         }
 282
 283         samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
 284
 285         return 0;
 286 }
 287 core_initcall(s5pv210_gpiolib_init);