arch/arm/mach-s5pv310/cpufreq.c

   1 /* linux/arch/arm/mach-s5pv310/cpufreq.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5PV310 - CPU frequency scaling support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/cpufreq.h>
  21
  22 #include <mach/map.h>
  23 #include <mach/regs-clock.h>
  24 #include <mach/regs-mem.h>
  25
  26 #include <plat/clock.h>
  27 #include <plat/pm.h>
  28
  29 static struct clk *cpu_clk;
  30 static struct clk *moutcore;
  31 static struct clk *mout_mpll;
  32 static struct clk *mout_apll;
  33
  34 #ifdef CONFIG_REGULATOR
  35 static struct regulator *arm_regulator;
  36 static struct regulator *int_regulator;
  37 #endif
  38
  39 static struct cpufreq_freqs freqs;
  40 static unsigned int memtype;
  41
  42 enum s5pv310_memory_type {
  43         DDR2 = 4,
  44         LPDDR2,
  45         DDR3,
  46 };
  47
  48 enum cpufreq_level_index {
  49         L0, L1, L2, L3, CPUFREQ_LEVEL_END,
  50 };
  51
  52 static struct cpufreq_frequency_table s5pv310_freq_table[] = {
  53         {L0, 1000*1000},
  54         {L1, 800*1000},
  55         {L2, 400*1000},
  56         {L3, 100*1000},
  57         {0, CPUFREQ_TABLE_END},
  58 };
  59
  60 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
  61         /*
  62          * Clock divider value for following
  63          * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
  64          *              DIVATB, DIVPCLK_DBG, DIVAPLL }
  65          */
  66
  67         /* ARM L0: 1000MHz */
  68         { 0, 3, 7, 3, 3, 0, 1 },
  69
  70         /* ARM L1: 800MHz */
  71         { 0, 3, 7, 3, 3, 0, 1 },
  72
  73         /* ARM L2: 400MHz */
  74         { 0, 1, 3, 1, 3, 0, 1 },
  75
  76         /* ARM L3: 100MHz */
  77         { 0, 0, 1, 0, 3, 1, 1 },
  78 };
  79
  80 static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
  81         /*
  82          * Clock divider value for following
  83          * { DIVCOPY, DIVHPM }
  84          */
  85
  86          /* ARM L0: 1000MHz */
  87         { 3, 0 },
  88
  89         /* ARM L1: 800MHz */
  90         { 3, 0 },
  91
  92         /* ARM L2: 400MHz */
  93         { 3, 0 },
  94
  95         /* ARM L3: 100MHz */
  96         { 3, 0 },
  97 };
  98
  99 static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
 100         /*
 101          * Clock divider value for following
 102          * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
 103          *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
 104          */
 105
 106         /* DMC L0: 400MHz */
 107         { 3, 1, 1, 1, 1, 1, 3, 1 },
 108
 109         /* DMC L1: 400MHz */
 110         { 3, 1, 1, 1, 1, 1, 3, 1 },
 111
 112         /* DMC L2: 266.7MHz */
 113         { 7, 1, 1, 2, 1, 1, 3, 1 },
 114
 115         /* DMC L3: 200MHz */
 116         { 7, 1, 1, 3, 1, 1, 3, 1 },
 117 };
 118
 119 static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
 120         /*
 121          * Clock divider value for following
 122          * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
 123          */
 124
 125         /* ACLK200 L0: 200MHz */
 126         { 3, 7, 4, 5, 1 },
 127
 128         /* ACLK200 L1: 200MHz */
 129         { 3, 7, 4, 5, 1 },
 130
 131         /* ACLK200 L2: 160MHz */
 132         { 4, 7, 5, 7, 1 },
 133
 134         /* ACLK200 L3: 133.3MHz */
 135         { 5, 7, 7, 7, 1 },
 136 };
 137
 138 static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
 139         /*
 140          * Clock divider value for following
 141          * { DIVGDL/R, DIVGPL/R }
 142          */
 143
 144         /* ACLK_GDL/R L0: 200MHz */
 145         { 3, 1 },
 146
 147         /* ACLK_GDL/R L1: 200MHz */
 148         { 3, 1 },
 149
 150         /* ACLK_GDL/R L2: 160MHz */
 151         { 4, 1 },
 152
 153         /* ACLK_GDL/R L3: 133.3MHz */
 154         { 5, 1 },
 155 };
 156
 157 struct cpufreq_voltage_table {
 158         unsigned int    index;          /* any */
 159         unsigned int    arm_volt;       /* uV */
 160         unsigned int    int_volt;
 161 };
 162
 163 static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
 164         {
 165                 .index          = L0,
 166                 .arm_volt       = 1200000,
 167                 .int_volt       = 1100000,
 168         }, {
 169                 .index          = L1,
 170                 .arm_volt       = 1100000,
 171                 .int_volt       = 1100000,
 172         }, {
 173                 .index          = L2,
 174                 .arm_volt       = 1000000,
 175                 .int_volt       = 1000000,
 176         }, {
 177                 .index          = L3,
 178                 .arm_volt       = 900000,
 179                 .int_volt       = 1000000,
 180         },
 181 };
 182
 183 static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
 184         /* APLL FOUT L0: 1000MHz */
 185         ((250 << 16) | (6 << 8) | 1),
 186
 187         /* APLL FOUT L1: 800MHz */
 188         ((200 << 16) | (6 << 8) | 1),
 189
 190         /* APLL FOUT L2 : 400MHz */
 191         ((200 << 16) | (6 << 8) | 2),
 192
 193         /* APLL FOUT L3: 100MHz */
 194         ((200 << 16) | (6 << 8) | 4),
 195 };
 196
 197 int s5pv310_verify_speed(struct cpufreq_policy *policy)
 198 {
 199         return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
 200 }
 201
 202 unsigned int s5pv310_getspeed(unsigned int cpu)
 203 {
 204         return clk_get_rate(cpu_clk) / 1000;
 205 }
 206
 207 void s5pv310_set_clkdiv(unsigned int div_index)
 208 {
 209         unsigned int tmp;
 210
 211         /* Change Divider - CPU0 */
 212
 213         tmp = __raw_readl(S5P_CLKDIV_CPU);
 214
 215         tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
 216                 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
 217                 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
 218                 S5P_CLKDIV_CPU0_APLL_MASK);
 219
 220         tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
 221                 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
 222                 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
 223                 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
 224                 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
 225                 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
 226                 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
 227
 228         __raw_writel(tmp, S5P_CLKDIV_CPU);
 229
 230         do {
 231                 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
 232         } while (tmp & 0x1111111);
 233
 234         /* Change Divider - CPU1 */
 235
 236         tmp = __raw_readl(S5P_CLKDIV_CPU1);
 237
 238         tmp &= ~((0x7 << 4) | 0x7);
 239
 240         tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
 241                 (clkdiv_cpu1[div_index][1] << 0));
 242
 243         __raw_writel(tmp, S5P_CLKDIV_CPU1);
 244
 245         do {
 246                 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
 247         } while (tmp & 0x11);
 248
 249         /* Change Divider - DMC0 */
 250
 251         tmp = __raw_readl(S5P_CLKDIV_DMC0);
 252
 253         tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
 254                 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
 255                 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
 256                 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
 257
 258         tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
 259                 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 260                 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
 261                 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
 262                 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
 263                 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
 264                 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
 265                 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
 266
 267         __raw_writel(tmp, S5P_CLKDIV_DMC0);
 268
 269         do {
 270                 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
 271         } while (tmp & 0x11111111);
 272
 273         /* Change Divider - TOP */
 274
 275         tmp = __raw_readl(S5P_CLKDIV_TOP);
 276
 277         tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
 278                 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
 279                 S5P_CLKDIV_TOP_ONENAND_MASK);
 280
 281         tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
 282                 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
 283                 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
 284                 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
 285                 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
 286
 287         __raw_writel(tmp, S5P_CLKDIV_TOP);
 288
 289         do {
 290                 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
 291         } while (tmp & 0x11111);
 292
 293         /* Change Divider - LEFTBUS */
 294
 295         tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
 296
 297         tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
 298
 299         tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
 300                 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
 301
 302         __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
 303
 304         do {
 305                 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
 306         } while (tmp & 0x11);
 307
 308         /* Change Divider - RIGHTBUS */
 309
 310         tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
 311
 312         tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
 313
 314         tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
 315                 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
 316
 317         __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
 318
 319         do {
 320                 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
 321         } while (tmp & 0x11);
 322 }
 323
 324 static void s5pv310_set_apll(unsigned int index)
 325 {
 326         unsigned int tmp;
 327
 328         /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 329         clk_set_parent(moutcore, mout_mpll);
 330
 331         do {
 332                 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
 333                         >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
 334                 tmp &= 0x7;
 335         } while (tmp != 0x2);
 336
 337         /* 2. Set APLL Lock time */
 338         __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
 339
 340         /* 3. Change PLL PMS values */
 341         tmp = __raw_readl(S5P_APLL_CON0);
 342         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 343         tmp |= s5pv310_apll_pms_table[index];
 344         __raw_writel(tmp, S5P_APLL_CON0);
 345
 346         /* 4. wait_lock_time */
 347         do {
 348                 tmp = __raw_readl(S5P_APLL_CON0);
 349         } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
 350
 351         /* 5. MUX_CORE_SEL = APLL */
 352         clk_set_parent(moutcore, mout_apll);
 353
 354         do {
 355                 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
 356                 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
 357         } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
 358 }
 359
 360 static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
 361 {
 362         unsigned int tmp;
 363
 364         if (old_index > new_index) {
 365                 /* The frequency changing to L0 needs to change apll */
 366                 if (freqs.new == s5pv310_freq_table[L0].frequency) {
 367                         /* 1. Change the system clock divider values */
 368                         s5pv310_set_clkdiv(new_index);
 369
 370                         /* 2. Change the apll m,p,s value */
 371                         s5pv310_set_apll(new_index);
 372                 } else {
 373                         /* 1. Change the system clock divider values */
 374                         s5pv310_set_clkdiv(new_index);
 375
 376                         /* 2. Change just s value in apll m,p,s value */
 377                         tmp = __raw_readl(S5P_APLL_CON0);
 378                         tmp &= ~(0x7 << 0);
 379                         tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
 380                         __raw_writel(tmp, S5P_APLL_CON0);
 381                 }
 382         }
 383
 384         else if (old_index < new_index) {
 385                 /* The frequency changing from L0 needs to change apll */
 386                 if (freqs.old == s5pv310_freq_table[L0].frequency) {
 387                         /* 1. Change the apll m,p,s value */
 388                         s5pv310_set_apll(new_index);
 389
 390                         /* 2. Change the system clock divider values */
 391                         s5pv310_set_clkdiv(new_index);
 392                 } else {
 393                         /* 1. Change just s value in apll m,p,s value */
 394                         tmp = __raw_readl(S5P_APLL_CON0);
 395                         tmp &= ~(0x7 << 0);
 396                         tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
 397                         __raw_writel(tmp, S5P_APLL_CON0);
 398
 399                         /* 2. Change the system clock divider values */
 400                         s5pv310_set_clkdiv(new_index);
 401                 }
 402         }
 403 }
 404
 405 static int s5pv310_target(struct cpufreq_policy *policy,
 406                           unsigned int target_freq,
 407                           unsigned int relation)
 408 {
 409         unsigned int index, old_index;
 410         unsigned int arm_volt, int_volt;
 411
 412         freqs.old = s5pv310_getspeed(policy->cpu);
 413
 414         if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
 415                                            freqs.old, relation, &old_index))
 416                 return -EINVAL;
 417
 418         if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
 419                                            target_freq, relation, &index))
 420                 return -EINVAL;
 421
 422         freqs.new = s5pv310_freq_table[index].frequency;
 423         freqs.cpu = policy->cpu;
 424
 425         if (freqs.new == freqs.old)
 426                 return 0;
 427
 428         /* get the voltage value */
 429         arm_volt = s5pv310_volt_table[index].arm_volt;
 430         int_volt = s5pv310_volt_table[index].int_volt;
 431
 432         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 433
 434         /* control regulator */
 435         if (freqs.new > freqs.old) {
 436                 /* Voltage up */
 437 #ifdef CONFIG_REGULATOR
 438                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
 439                 regulator_set_voltage(int_regulator, int_volt, int_volt);
 440 #endif
 441         }
 442
 443         /* Clock Configuration Procedure */
 444         s5pv310_set_frequency(old_index, index);
 445
 446         /* control regulator */
 447         if (freqs.new < freqs.old) {
 448                 /* Voltage down */
 449 #ifdef CONFIG_REGULATOR
 450                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
 451                 regulator_set_voltage(int_regulator, int_volt, int_volt);
 452 #endif
 453         }
 454
 455         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 456
 457         return 0;
 458 }
 459
 460 #ifdef CONFIG_PM
 461 static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
 462                                    pm_message_t pmsg)
 463 {
 464         return 0;
 465 }
 466
 467 static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
 468 {
 469         return 0;
 470 }
 471 #endif
 472
 473 static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
 474 {
 475         policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
 476
 477         cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
 478
 479         /* set the transition latency value */
 480         policy->cpuinfo.transition_latency = 100000;
 481
 482         /*
 483          * S5PV310 multi-core processors has 2 cores
 484          * that the frequency cannot be set independently.
 485          * Each cpu is bound to the same speed.
 486          * So the affected cpu is all of the cpus.
 487          */
 488         cpumask_setall(policy->cpus);
 489
 490         return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
 491 }
 492
 493 static struct cpufreq_driver s5pv310_driver = {
 494         .flags          = CPUFREQ_STICKY,
 495         .verify         = s5pv310_verify_speed,
 496         .target         = s5pv310_target,
 497         .get            = s5pv310_getspeed,
 498         .init           = s5pv310_cpufreq_cpu_init,
 499         .name           = "s5pv310_cpufreq",
 500 #ifdef CONFIG_PM
 501         .suspend        = s5pv310_cpufreq_suspend,
 502         .resume         = s5pv310_cpufreq_resume,
 503 #endif
 504 };
 505
 506 static int __init s5pv310_cpufreq_init(void)
 507 {
 508         cpu_clk = clk_get(NULL, "armclk");
 509         if (IS_ERR(cpu_clk))
 510                 return PTR_ERR(cpu_clk);
 511
 512         moutcore = clk_get(NULL, "moutcore");
 513         if (IS_ERR(moutcore))
 514                 goto out;
 515
 516         mout_mpll = clk_get(NULL, "mout_mpll");
 517         if (IS_ERR(mout_mpll))
 518                 goto out;
 519
 520         mout_apll = clk_get(NULL, "mout_apll");
 521         if (IS_ERR(mout_apll))
 522                 goto out;
 523
 524 #ifdef CONFIG_REGULATOR
 525         arm_regulator = regulator_get(NULL, "vdd_arm");
 526         if (IS_ERR(arm_regulator)) {
 527                 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
 528                 goto out;
 529         }
 530
 531         int_regulator = regulator_get(NULL, "vdd_int");
 532         if (IS_ERR(int_regulator)) {
 533                 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
 534                 goto out;
 535         }
 536 #endif
 537
 538         /*
 539          * Check DRAM type.
 540          * Because DVFS level is different according to DRAM type.
 541          */
 542         memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
 543         memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
 544         memtype &= S5P_DMC0_MEMTYPE_MASK;
 545
 546         if ((memtype < DDR2) && (memtype > DDR3)) {
 547                 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
 548                 goto out;
 549         } else {
 550                 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
 551         }
 552
 553         return cpufreq_register_driver(&s5pv310_driver);
 554
 555 out:
 556         if (!IS_ERR(cpu_clk))
 557                 clk_put(cpu_clk);
 558
 559         if (!IS_ERR(moutcore))
 560                 clk_put(moutcore);
 561
 562         if (!IS_ERR(mout_mpll))
 563                 clk_put(mout_mpll);
 564
 565         if (!IS_ERR(mout_apll))
 566                 clk_put(mout_apll);
 567
 568 #ifdef CONFIG_REGULATOR
 569         if (!IS_ERR(arm_regulator))
 570                 regulator_put(arm_regulator);
 571
 572         if (!IS_ERR(int_regulator))
 573                 regulator_put(int_regulator);
 574 #endif
 575
 576         printk(KERN_ERR "%s: failed initialization\n", __func__);
 577
 578         return -EINVAL;
 579 }
 580 late_initcall(s5pv310_cpufreq_init);