| blob | b810deb552a993a0a40785c410438fe9d36c5f6a |
1 /*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22 #define REGS_UARTDBG_PHYS 0x80070000
23 #define REGS_UARTDBG_SIZE 0x2000
25 #define HW_UARTDBGDR 0x00000000
26 #define BP_UARTDBGDR_UNAVAILABLE 16
27 #define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28 #define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30 #define BP_UARTDBGDR_RESERVED 12
31 #define BM_UARTDBGDR_RESERVED 0x0000F000
32 #define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34 #define BM_UARTDBGDR_OE 0x00000800
35 #define BM_UARTDBGDR_BE 0x00000400
36 #define BM_UARTDBGDR_PE 0x00000200
37 #define BM_UARTDBGDR_FE 0x00000100
38 #define BP_UARTDBGDR_DATA 0
39 #define BM_UARTDBGDR_DATA 0x000000FF
40 #define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42 #define HW_UARTDBGRSR_ECR 0x00000004
43 #define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44 #define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45 #define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47 #define BP_UARTDBGRSR_ECR_EC 4
48 #define BM_UARTDBGRSR_ECR_EC 0x000000F0
49 #define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51 #define BM_UARTDBGRSR_ECR_OE 0x00000008
52 #define BM_UARTDBGRSR_ECR_BE 0x00000004
53 #define BM_UARTDBGRSR_ECR_PE 0x00000002
54 #define BM_UARTDBGRSR_ECR_FE 0x00000001
55 #define HW_UARTDBGFR 0x00000018
56 #define BP_UARTDBGFR_UNAVAILABLE 16
57 #define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58 #define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60 #define BP_UARTDBGFR_RESERVED 9
61 #define BM_UARTDBGFR_RESERVED 0x0000FE00
62 #define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64 #define BM_UARTDBGFR_RI 0x00000100
65 #define BM_UARTDBGFR_TXFE 0x00000080
66 #define BM_UARTDBGFR_RXFF 0x00000040
67 #define BM_UARTDBGFR_TXFF 0x00000020
68 #define BM_UARTDBGFR_RXFE 0x00000010
69 #define BM_UARTDBGFR_BUSY 0x00000008
70 #define BM_UARTDBGFR_DCD 0x00000004
71 #define BM_UARTDBGFR_DSR 0x00000002
72 #define BM_UARTDBGFR_CTS 0x00000001
73 #define HW_UARTDBGILPR 0x00000020
74 #define BP_UARTDBGILPR_UNAVAILABLE 8
75 #define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76 #define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78 #define BP_UARTDBGILPR_ILPDVSR 0
79 #define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80 #define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82 #define HW_UARTDBGIBRD 0x00000024
83 #define BP_UARTDBGIBRD_UNAVAILABLE 16
84 #define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85 #define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87 #define BP_UARTDBGIBRD_BAUD_DIVINT 0
88 #define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89 #define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91 #define HW_UARTDBGFBRD 0x00000028
92 #define BP_UARTDBGFBRD_UNAVAILABLE 8
93 #define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94 #define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96 #define BP_UARTDBGFBRD_RESERVED 6
97 #define BM_UARTDBGFBRD_RESERVED 0x000000C0
98 #define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100 #define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101 #define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102 #define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104 #define HW_UARTDBGLCR_H 0x0000002c
105 #define BP_UARTDBGLCR_H_UNAVAILABLE 16
106 #define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107 #define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109 #define BP_UARTDBGLCR_H_RESERVED 8
110 #define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111 #define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113 #define BM_UARTDBGLCR_H_SPS 0x00000080
114 #define BP_UARTDBGLCR_H_WLEN 5
115 #define BM_UARTDBGLCR_H_WLEN 0x00000060
116 #define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118 #define BM_UARTDBGLCR_H_FEN 0x00000010
119 #define BM_UARTDBGLCR_H_STP2 0x00000008
120 #define BM_UARTDBGLCR_H_EPS 0x00000004
121 #define BM_UARTDBGLCR_H_PEN 0x00000002
122 #define BM_UARTDBGLCR_H_BRK 0x00000001
123 #define HW_UARTDBGCR 0x00000030
124 #define BP_UARTDBGCR_UNAVAILABLE 16
125 #define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126 #define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128 #define BM_UARTDBGCR_CTSEN 0x00008000
129 #define BM_UARTDBGCR_RTSEN 0x00004000
130 #define BM_UARTDBGCR_OUT2 0x00002000
131 #define BM_UARTDBGCR_OUT1 0x00001000
132 #define BM_UARTDBGCR_RTS 0x00000800
133 #define BM_UARTDBGCR_DTR 0x00000400
134 #define BM_UARTDBGCR_RXE 0x00000200
135 #define BM_UARTDBGCR_TXE 0x00000100
136 #define BM_UARTDBGCR_LBE 0x00000080
137 #define BP_UARTDBGCR_RESERVED 3
138 #define BM_UARTDBGCR_RESERVED 0x00000078
139 #define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141 #define BM_UARTDBGCR_SIRLP 0x00000004
142 #define BM_UARTDBGCR_SIREN 0x00000002
143 #define BM_UARTDBGCR_UARTEN 0x00000001
144 #define HW_UARTDBGIFLS 0x00000034
145 #define BP_UARTDBGIFLS_UNAVAILABLE 16
146 #define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147 #define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149 #define BP_UARTDBGIFLS_RESERVED 6
150 #define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151 #define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153 #define BP_UARTDBGIFLS_RXIFLSEL 3
154 #define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155 #define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157 #define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158 #define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159 #define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160 #define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161 #define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162 #define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163 #define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164 #define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165 #define BP_UARTDBGIFLS_TXIFLSEL 0
166 #define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167 #define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169 #define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170 #define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171 #define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172 #define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173 #define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174 #define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175 #define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176 #define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177 #define HW_UARTDBGIMSC 0x00000038
178 #define BP_UARTDBGIMSC_UNAVAILABLE 16
179 #define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180 #define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182 #define BP_UARTDBGIMSC_RESERVED 11
183 #define BM_UARTDBGIMSC_RESERVED 0x0000F800
184 #define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186 #define BM_UARTDBGIMSC_OEIM 0x00000400
187 #define BM_UARTDBGIMSC_BEIM 0x00000200
188 #define BM_UARTDBGIMSC_PEIM 0x00000100
189 #define BM_UARTDBGIMSC_FEIM 0x00000080
190 #define BM_UARTDBGIMSC_RTIM 0x00000040
191 #define BM_UARTDBGIMSC_TXIM 0x00000020
192 #define BM_UARTDBGIMSC_RXIM 0x00000010
193 #define BM_UARTDBGIMSC_DSRMIM 0x00000008
194 #define BM_UARTDBGIMSC_DCDMIM 0x00000004
195 #define BM_UARTDBGIMSC_CTSMIM 0x00000002
196 #define BM_UARTDBGIMSC_RIMIM 0x00000001
197 #define HW_UARTDBGRIS 0x0000003c
198 #define BP_UARTDBGRIS_UNAVAILABLE 16
199 #define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200 #define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202 #define BP_UARTDBGRIS_RESERVED 11
203 #define BM_UARTDBGRIS_RESERVED 0x0000F800
204 #define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206 #define BM_UARTDBGRIS_OERIS 0x00000400
207 #define BM_UARTDBGRIS_BERIS 0x00000200
208 #define BM_UARTDBGRIS_PERIS 0x00000100
209 #define BM_UARTDBGRIS_FERIS 0x00000080
210 #define BM_UARTDBGRIS_RTRIS 0x00000040
211 #define BM_UARTDBGRIS_TXRIS 0x00000020
212 #define BM_UARTDBGRIS_RXRIS 0x00000010
213 #define BM_UARTDBGRIS_DSRRMIS 0x00000008
214 #define BM_UARTDBGRIS_DCDRMIS 0x00000004
215 #define BM_UARTDBGRIS_CTSRMIS 0x00000002
216 #define BM_UARTDBGRIS_RIRMIS 0x00000001
217 #define HW_UARTDBGMIS 0x00000040
218 #define BP_UARTDBGMIS_UNAVAILABLE 16
219 #define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220 #define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222 #define BP_UARTDBGMIS_RESERVED 11
223 #define BM_UARTDBGMIS_RESERVED 0x0000F800
224 #define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226 #define BM_UARTDBGMIS_OEMIS 0x00000400
227 #define BM_UARTDBGMIS_BEMIS 0x00000200
228 #define BM_UARTDBGMIS_PEMIS 0x00000100
229 #define BM_UARTDBGMIS_FEMIS 0x00000080
230 #define BM_UARTDBGMIS_RTMIS 0x00000040
231 #define BM_UARTDBGMIS_TXMIS 0x00000020
232 #define BM_UARTDBGMIS_RXMIS 0x00000010
233 #define BM_UARTDBGMIS_DSRMMIS 0x00000008
234 #define BM_UARTDBGMIS_DCDMMIS 0x00000004
235 #define BM_UARTDBGMIS_CTSMMIS 0x00000002
236 #define BM_UARTDBGMIS_RIMMIS 0x00000001
237 #define HW_UARTDBGICR 0x00000044
238 #define BP_UARTDBGICR_UNAVAILABLE 16
239 #define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240 #define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242 #define BP_UARTDBGICR_RESERVED 11
243 #define BM_UARTDBGICR_RESERVED 0x0000F800
244 #define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246 #define BM_UARTDBGICR_OEIC 0x00000400
247 #define BM_UARTDBGICR_BEIC 0x00000200
248 #define BM_UARTDBGICR_PEIC 0x00000100
249 #define BM_UARTDBGICR_FEIC 0x00000080
250 #define BM_UARTDBGICR_RTIC 0x00000040
251 #define BM_UARTDBGICR_TXIC 0x00000020
252 #define BM_UARTDBGICR_RXIC 0x00000010
253 #define BM_UARTDBGICR_DSRMIC 0x00000008
254 #define BM_UARTDBGICR_DCDMIC 0x00000004
255 #define BM_UARTDBGICR_CTSMIC 0x00000002
256 #define BM_UARTDBGICR_RIMIC 0x00000001
257 #define HW_UARTDBGDMACR 0x00000048
258 #define BP_UARTDBGDMACR_UNAVAILABLE 16
259 #define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260 #define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262 #define BP_UARTDBGDMACR_RESERVED 3
263 #define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264 #define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266 #define BM_UARTDBGDMACR_DMAONERR 0x00000004
267 #define BM_UARTDBGDMACR_TXDMAE 0x00000002
268 #define BM_UARTDBGDMACR_RXDMAE 0x00000001