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Merge branch 'v6v7' into devel
[linux/fpc-iii.git] / arch / arm / mach-tegra / pcie.c
blob53f5fa37014a34eeeaaf98350b29ee2c2384d5e9
1 /*
2 * arch/arm/mach-tegra/pci.c
3 *
4 * PCIe host controller driver for TEGRA(2) SOCs
5 *
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
8 *
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 *
12 * Bits taken from arch/arm/mach-dove/pcie.c
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35
36 #include <asm/sizes.h>
37 #include <asm/mach/pci.h>
38
39 #include <mach/pinmux.h>
40 #include <mach/iomap.h>
41 #include <mach/clk.h>
42
43 /* register definitions */
44 #define AFI_OFFSET 0x3800
45 #define PADS_OFFSET 0x3000
46 #define RP0_OFFSET 0x0000
47 #define RP1_OFFSET 0x1000
48
49 #define AFI_AXI_BAR0_SZ 0x00
50 #define AFI_AXI_BAR1_SZ 0x04
51 #define AFI_AXI_BAR2_SZ 0x08
52 #define AFI_AXI_BAR3_SZ 0x0c
53 #define AFI_AXI_BAR4_SZ 0x10
54 #define AFI_AXI_BAR5_SZ 0x14
55
56 #define AFI_AXI_BAR0_START 0x18
57 #define AFI_AXI_BAR1_START 0x1c
58 #define AFI_AXI_BAR2_START 0x20
59 #define AFI_AXI_BAR3_START 0x24
60 #define AFI_AXI_BAR4_START 0x28
61 #define AFI_AXI_BAR5_START 0x2c
62
63 #define AFI_FPCI_BAR0 0x30
64 #define AFI_FPCI_BAR1 0x34
65 #define AFI_FPCI_BAR2 0x38
66 #define AFI_FPCI_BAR3 0x3c
67 #define AFI_FPCI_BAR4 0x40
68 #define AFI_FPCI_BAR5 0x44
69
70 #define AFI_CACHE_BAR0_SZ 0x48
71 #define AFI_CACHE_BAR0_ST 0x4c
72 #define AFI_CACHE_BAR1_SZ 0x50
73 #define AFI_CACHE_BAR1_ST 0x54
74
75 #define AFI_MSI_BAR_SZ 0x60
76 #define AFI_MSI_FPCI_BAR_ST 0x64
77 #define AFI_MSI_AXI_BAR_ST 0x68
78
79 #define AFI_CONFIGURATION 0xac
80 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
81
82 #define AFI_FPCI_ERROR_MASKS 0xb0
83
84 #define AFI_INTR_MASK 0xb4
85 #define AFI_INTR_MASK_INT_MASK (1 << 0)
86 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
87
88 #define AFI_INTR_CODE 0xb8
89 #define AFI_INTR_CODE_MASK 0xf
90 #define AFI_INTR_MASTER_ABORT 4
91 #define AFI_INTR_LEGACY 6
92
93 #define AFI_INTR_SIGNATURE 0xbc
94 #define AFI_SM_INTR_ENABLE 0xc4
95
96 #define AFI_AFI_INTR_ENABLE 0xc8
97 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
98 #define AFI_INTR_EN_INI_DECERR (1 << 1)
99 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
100 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
101 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
102 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
103 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
104 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
105
106 #define AFI_PCIE_CONFIG 0x0f8
107 #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
108 #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
109 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
110 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
112
113 #define AFI_FUSE 0x104
114 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
115
116 #define AFI_PEX0_CTRL 0x110
117 #define AFI_PEX1_CTRL 0x118
118 #define AFI_PEX_CTRL_RST (1 << 0)
119 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
120
121 #define RP_VEND_XP 0x00000F00
122 #define RP_VEND_XP_DL_UP (1 << 30)
123
124 #define RP_LINK_CONTROL_STATUS 0x00000090
125 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
126
127 #define PADS_CTL_SEL 0x0000009C
128
129 #define PADS_CTL 0x000000A0
130 #define PADS_CTL_IDDQ_1L (1 << 0)
131 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
132 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
133
134 #define PADS_PLL_CTL 0x000000B8
135 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
136 #define PADS_PLL_CTL_LOCKDET (1 << 8)
137 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
138 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
139 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
140 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
141 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
142 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
143 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
144
145 /* PMC access is required for PCIE xclk (un)clamping */
146 #define PMC_SCRATCH42 0x144
147 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
148
149 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
150
151 #define pmc_writel(value, reg) \
152 __raw_writel(value, (u32)reg_pmc_base + (reg))
153 #define pmc_readl(reg) \
154 __raw_readl((u32)reg_pmc_base + (reg))
155
156 /*
157 * Tegra2 defines 1GB in the AXI address map for PCIe.
158 *
159 * That address space is split into different regions, with sizes and
160 * offsets as follows:
161 *
162 * 0x80000000 - 0x80003fff - PCI controller registers
163 * 0x80004000 - 0x80103fff - PCI configuration space
164 * 0x80104000 - 0x80203fff - PCI extended configuration space
165 * 0x80203fff - 0x803fffff - unused
166 * 0x80400000 - 0x8040ffff - downstream IO
167 * 0x80410000 - 0x8fffffff - unused
168 * 0x90000000 - 0x9fffffff - non-prefetchable memory
169 * 0xa0000000 - 0xbfffffff - prefetchable memory
170 */
171 #define TEGRA_PCIE_BASE 0x80000000
172
173 #define PCIE_REGS_SZ SZ_16K
174 #define PCIE_CFG_OFF PCIE_REGS_SZ
175 #define PCIE_CFG_SZ SZ_1M
176 #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
177 #define PCIE_EXT_CFG_SZ SZ_1M
178 #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
179
180 #define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
181 #define MMIO_SIZE SZ_64K
182 #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
183 #define MEM_SIZE_0 SZ_128M
184 #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
185 #define MEM_SIZE_1 SZ_128M
186 #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
187 #define PREFETCH_MEM_SIZE_0 SZ_128M
188 #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
189 #define PREFETCH_MEM_SIZE_1 SZ_128M
190
191 #define PCIE_CONF_BUS(b) ((b) << 16)
192 #define PCIE_CONF_DEV(d) ((d) << 11)
193 #define PCIE_CONF_FUNC(f) ((f) << 8)
194 #define PCIE_CONF_REG(r) \
195 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
196
197 struct tegra_pcie_port {
198 int index;
199 u8 root_bus_nr;
200 void __iomem *base;
201
202 bool link_up;
203
204 char io_space_name[16];
205 char mem_space_name[16];
206 char prefetch_space_name[20];
207 struct resource res[3];
208 };
209
210 struct tegra_pcie_info {
211 struct tegra_pcie_port port[2];
212 int num_ports;
213
214 void __iomem *regs;
215 struct resource res_mmio;
216
217 struct clk *pex_clk;
218 struct clk *afi_clk;
219 struct clk *pcie_xclk;
220 struct clk *pll_e;
221 };
222
223 static struct tegra_pcie_info tegra_pcie = {
224 .res_mmio = {
225 .name = "PCI IO",
226 .start = MMIO_BASE,
227 .end = MMIO_BASE + MMIO_SIZE - 1,
228 .flags = IORESOURCE_MEM,
229 },
230 };
231
232 void __iomem *tegra_pcie_io_base;
233 EXPORT_SYMBOL(tegra_pcie_io_base);
234
235 static inline void afi_writel(u32 value, unsigned long offset)
236 {
237 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
238 }
239
240 static inline u32 afi_readl(unsigned long offset)
241 {
242 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
243 }
244
245 static inline void pads_writel(u32 value, unsigned long offset)
246 {
247 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
248 }
249
250 static inline u32 pads_readl(unsigned long offset)
251 {
252 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
253 }
254
255 static struct tegra_pcie_port *bus_to_port(int bus)
256 {
257 int i;
258
259 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
260 int rbus = tegra_pcie.port[i].root_bus_nr;
261 if (rbus != -1 && rbus == bus)
262 break;
263 }
264
265 return i >= 0 ? tegra_pcie.port + i : NULL;
266 }
267
268 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
269 int where, int size, u32 *val)
270 {
271 struct tegra_pcie_port *pp = bus_to_port(bus->number);
272 void __iomem *addr;
273
274 if (pp) {
275 if (devfn != 0) {
276 *val = 0xffffffff;
277 return PCIBIOS_DEVICE_NOT_FOUND;
278 }
279
280 addr = pp->base + (where & ~0x3);
281 } else {
282 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
283 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
284 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
285 PCIE_CONF_REG(where));
286 }
287
288 *val = readl(addr);
289
290 if (size == 1)
291 *val = (*val >> (8 * (where & 3))) & 0xff;
292 else if (size == 2)
293 *val = (*val >> (8 * (where & 3))) & 0xffff;
294
295 return PCIBIOS_SUCCESSFUL;
296 }
297
298 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
299 int where, int size, u32 val)
300 {
301 struct tegra_pcie_port *pp = bus_to_port(bus->number);
302 void __iomem *addr;
303
304 u32 mask;
305 u32 tmp;
306
307 if (pp) {
308 if (devfn != 0)
309 return PCIBIOS_DEVICE_NOT_FOUND;
310
311 addr = pp->base + (where & ~0x3);
312 } else {
313 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
314 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
315 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
316 PCIE_CONF_REG(where));
317 }
318
319 if (size == 4) {
320 writel(val, addr);
321 return PCIBIOS_SUCCESSFUL;
322 }
323
324 if (size == 2)
325 mask = ~(0xffff << ((where & 0x3) * 8));
326 else if (size == 1)
327 mask = ~(0xff << ((where & 0x3) * 8));
328 else
329 return PCIBIOS_BAD_REGISTER_NUMBER;
330
331 tmp = readl(addr) & mask;
332 tmp |= val << ((where & 0x3) * 8);
333 writel(tmp, addr);
334
335 return PCIBIOS_SUCCESSFUL;
336 }
337
338 static struct pci_ops tegra_pcie_ops = {
339 .read = tegra_pcie_read_conf,
340 .write = tegra_pcie_write_conf,
341 };
342
343 static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
344 {
345 u16 reg;
346
347 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
348 pci_read_config_word(dev, PCI_COMMAND, &reg);
349 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
350 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
351 pci_write_config_word(dev, PCI_COMMAND, reg);
352 }
353 }
354 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
355
356 /* Tegra PCIE root complex wrongly reports device class */
357 static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
358 {
359 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
360 }
361 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
362 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
363
364 /* Tegra PCIE requires relaxed ordering */
365 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
366 {
367 u16 val16;
368 int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
369
370 if (pos <= 0) {
371 dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
372 return;
373 }
374
375 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
376 val16 |= PCI_EXP_DEVCTL_RELAX_EN;
377 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
378 }
379 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
380
381 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
382 {
383 struct tegra_pcie_port *pp;
384
385 if (nr >= tegra_pcie.num_ports)
386 return 0;
387
388 pp = tegra_pcie.port + nr;
389 pp->root_bus_nr = sys->busnr;
390
391 /*
392 * IORESOURCE_IO
393 */
394 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
395 "PCIe %d I/O", pp->index);
396 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
397 pp->res[0].name = pp->io_space_name;
398 if (pp->index == 0) {
399 pp->res[0].start = PCIBIOS_MIN_IO;
400 pp->res[0].end = pp->res[0].start + SZ_32K - 1;
401 } else {
402 pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
403 pp->res[0].end = IO_SPACE_LIMIT;
404 }
405 pp->res[0].flags = IORESOURCE_IO;
406 if (request_resource(&ioport_resource, &pp->res[0]))
407 panic("Request PCIe IO resource failed\n");
408 sys->resource[0] = &pp->res[0];
409
410 /*
411 * IORESOURCE_MEM
412 */
413 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
414 "PCIe %d MEM", pp->index);
415 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
416 pp->res[1].name = pp->mem_space_name;
417 if (pp->index == 0) {
418 pp->res[1].start = MEM_BASE_0;
419 pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
420 } else {
421 pp->res[1].start = MEM_BASE_1;
422 pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
423 }
424 pp->res[1].flags = IORESOURCE_MEM;
425 if (request_resource(&iomem_resource, &pp->res[1]))
426 panic("Request PCIe Memory resource failed\n");
427 sys->resource[1] = &pp->res[1];
428
429 /*
430 * IORESOURCE_MEM | IORESOURCE_PREFETCH
431 */
432 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
433 "PCIe %d PREFETCH MEM", pp->index);
434 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
435 pp->res[2].name = pp->prefetch_space_name;
436 if (pp->index == 0) {
437 pp->res[2].start = PREFETCH_MEM_BASE_0;
438 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
439 } else {
440 pp->res[2].start = PREFETCH_MEM_BASE_1;
441 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
442 }
443 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
444 if (request_resource(&iomem_resource, &pp->res[2]))
445 panic("Request PCIe Prefetch Memory resource failed\n");
446 sys->resource[2] = &pp->res[2];
447
448 return 1;
449 }
450
451 static int tegra_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
452 {
453 return INT_PCIE_INTR;
454 }
455
456 static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
457 struct pci_sys_data *sys)
458 {
459 struct tegra_pcie_port *pp;
460
461 if (nr >= tegra_pcie.num_ports)
462 return 0;
463
464 pp = tegra_pcie.port + nr;
465 pp->root_bus_nr = sys->busnr;
466
467 return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys);
468 }
469
470 static struct hw_pci tegra_pcie_hw __initdata = {
471 .nr_controllers = 2,
472 .setup = tegra_pcie_setup,
473 .scan = tegra_pcie_scan_bus,
474 .swizzle = pci_std_swizzle,
475 .map_irq = tegra_pcie_map_irq,
476 };
477
478
479 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
480 {
481 const char *err_msg[] = {
482 "Unknown",
483 "AXI slave error",
484 "AXI decode error",
485 "Target abort",
486 "Master abort",
487 "Invalid write",
488 "Response decoding error",
489 "AXI response decoding error",
490 "Transcation timeout",
491 };
492
493 u32 code, signature;
494
495 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
496 signature = afi_readl(AFI_INTR_SIGNATURE);
497 afi_writel(0, AFI_INTR_CODE);
498
499 if (code == AFI_INTR_LEGACY)
500 return IRQ_NONE;
501
502 if (code >= ARRAY_SIZE(err_msg))
503 code = 0;
504
505 /*
506 * do not pollute kernel log with master abort reports since they
507 * happen a lot during enumeration
508 */
509 if (code == AFI_INTR_MASTER_ABORT)
510 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
511 else
512 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
513
514 return IRQ_HANDLED;
515 }
516
517 static void tegra_pcie_setup_translations(void)
518 {
519 u32 fpci_bar;
520 u32 size;
521 u32 axi_address;
522
523 /* Bar 0: config Bar */
524 fpci_bar = ((u32)0xfdff << 16);
525 size = PCIE_CFG_SZ;
526 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
527 afi_writel(axi_address, AFI_AXI_BAR0_START);
528 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
529 afi_writel(fpci_bar, AFI_FPCI_BAR0);
530
531 /* Bar 1: extended config Bar */
532 fpci_bar = ((u32)0xfe1 << 20);
533 size = PCIE_EXT_CFG_SZ;
534 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
535 afi_writel(axi_address, AFI_AXI_BAR1_START);
536 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
537 afi_writel(fpci_bar, AFI_FPCI_BAR1);
538
539 /* Bar 2: downstream IO bar */
540 fpci_bar = ((__u32)0xfdfc << 16);
541 size = MMIO_SIZE;
542 axi_address = MMIO_BASE;
543 afi_writel(axi_address, AFI_AXI_BAR2_START);
544 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
545 afi_writel(fpci_bar, AFI_FPCI_BAR2);
546
547 /* Bar 3: prefetchable memory BAR */
548 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
549 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
550 axi_address = PREFETCH_MEM_BASE_0;
551 afi_writel(axi_address, AFI_AXI_BAR3_START);
552 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
553 afi_writel(fpci_bar, AFI_FPCI_BAR3);
554
555 /* Bar 4: non prefetchable memory BAR */
556 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
557 size = MEM_SIZE_0 + MEM_SIZE_1;
558 axi_address = MEM_BASE_0;
559 afi_writel(axi_address, AFI_AXI_BAR4_START);
560 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
561 afi_writel(fpci_bar, AFI_FPCI_BAR4);
562
563 /* Bar 5: NULL out the remaining BAR as it is not used */
564 fpci_bar = 0;
565 size = 0;
566 axi_address = 0;
567 afi_writel(axi_address, AFI_AXI_BAR5_START);
568 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
569 afi_writel(fpci_bar, AFI_FPCI_BAR5);
570
571 /* map all upstream transactions as uncached */
572 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
573 afi_writel(0, AFI_CACHE_BAR0_SZ);
574 afi_writel(0, AFI_CACHE_BAR1_ST);
575 afi_writel(0, AFI_CACHE_BAR1_SZ);
576
577 /* No MSI */
578 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
579 afi_writel(0, AFI_MSI_BAR_SZ);
580 afi_writel(0, AFI_MSI_AXI_BAR_ST);
581 afi_writel(0, AFI_MSI_BAR_SZ);
582 }
583
584 static void tegra_pcie_enable_controller(void)
585 {
586 u32 val, reg;
587 int i;
588
589 /* Enable slot clock and pulse the reset signals */
590 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
591 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
592 afi_writel(val, reg);
593 val &= ~AFI_PEX_CTRL_RST;
594 afi_writel(val, reg);
595
596 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
597 afi_writel(val, reg);
598 }
599
600 /* Enable dual controller and both ports */
601 val = afi_readl(AFI_PCIE_CONFIG);
602 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
603 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
604 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
605 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
606 afi_writel(val, AFI_PCIE_CONFIG);
607
608 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
609 afi_writel(val, AFI_FUSE);
610
611 /* Initialze internal PHY, enable up to 16 PCIE lanes */
612 pads_writel(0x0, PADS_CTL_SEL);
613
614 /* override IDDQ to 1 on all 4 lanes */
615 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
616 pads_writel(val, PADS_CTL);
617
618 /*
619 * set up PHY PLL inputs select PLLE output as refclock,
620 * set TX ref sel to div10 (not div5)
621 */
622 val = pads_readl(PADS_PLL_CTL);
623 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
624 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
625 pads_writel(val, PADS_PLL_CTL);
626
627 /* take PLL out of reset */
628 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
629 pads_writel(val, PADS_PLL_CTL);
630
631 /*
632 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
633 * This doesn't exist in the documentation
634 */
635 pads_writel(0xfa5cfa5c, 0xc8);
636
637 /* Wait for the PLL to lock */
638 do {
639 val = pads_readl(PADS_PLL_CTL);
640 } while (!(val & PADS_PLL_CTL_LOCKDET));
641
642 /* turn off IDDQ override */
643 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
644 pads_writel(val, PADS_CTL);
645
646 /* enable TX/RX data */
647 val = pads_readl(PADS_CTL);
648 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
649 pads_writel(val, PADS_CTL);
650
651 /* Take the PCIe interface module out of reset */
652 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
653
654 /* Finally enable PCIe */
655 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
656 afi_writel(val, AFI_CONFIGURATION);
657
658 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
659 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
660 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
661 afi_writel(val, AFI_AFI_INTR_ENABLE);
662 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
663
664 /* FIXME: No MSI for now, only INT */
665 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
666
667 /* Disable all execptions */
668 afi_writel(0, AFI_FPCI_ERROR_MASKS);
669
670 return;
671 }
672
673 static void tegra_pcie_xclk_clamp(bool clamp)
674 {
675 u32 reg;
676
677 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
678
679 if (clamp)
680 reg |= PMC_SCRATCH42_PCX_CLAMP;
681
682 pmc_writel(reg, PMC_SCRATCH42);
683 }
684
685 static int tegra_pcie_power_on(void)
686 {
687 tegra_pcie_xclk_clamp(true);
688 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
689 tegra_pcie_xclk_clamp(false);
690
691 clk_enable(tegra_pcie.afi_clk);
692 clk_enable(tegra_pcie.pex_clk);
693 return clk_enable(tegra_pcie.pll_e);
694 }
695
696 static void tegra_pcie_power_off(void)
697 {
698 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
699 tegra_periph_reset_assert(tegra_pcie.afi_clk);
700 tegra_periph_reset_assert(tegra_pcie.pex_clk);
701
702 tegra_pcie_xclk_clamp(true);
703 }
704
705 static int tegra_pcie_clocks_get(void)
706 {
707 int err;
708
709 tegra_pcie.pex_clk = clk_get(NULL, "pex");
710 if (IS_ERR(tegra_pcie.pex_clk))
711 return PTR_ERR(tegra_pcie.pex_clk);
712
713 tegra_pcie.afi_clk = clk_get(NULL, "afi");
714 if (IS_ERR(tegra_pcie.afi_clk)) {
715 err = PTR_ERR(tegra_pcie.afi_clk);
716 goto err_afi_clk;
717 }
718
719 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
720 if (IS_ERR(tegra_pcie.pcie_xclk)) {
721 err = PTR_ERR(tegra_pcie.pcie_xclk);
722 goto err_pcie_xclk;
723 }
724
725 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
726 if (IS_ERR(tegra_pcie.pll_e)) {
727 err = PTR_ERR(tegra_pcie.pll_e);
728 goto err_pll_e;
729 }
730
731 return 0;
732
733 err_pll_e:
734 clk_put(tegra_pcie.pcie_xclk);
735 err_pcie_xclk:
736 clk_put(tegra_pcie.afi_clk);
737 err_afi_clk:
738 clk_put(tegra_pcie.pex_clk);
739
740 return err;
741 }
742
743 static void tegra_pcie_clocks_put(void)
744 {
745 clk_put(tegra_pcie.pll_e);
746 clk_put(tegra_pcie.pcie_xclk);
747 clk_put(tegra_pcie.afi_clk);
748 clk_put(tegra_pcie.pex_clk);
749 }
750
751 static int __init tegra_pcie_get_resources(void)
752 {
753 struct resource *res_mmio = &tegra_pcie.res_mmio;
754 int err;
755
756 err = tegra_pcie_clocks_get();
757 if (err) {
758 pr_err("PCIE: failed to get clocks: %d\n", err);
759 return err;
760 }
761
762 err = tegra_pcie_power_on();
763 if (err) {
764 pr_err("PCIE: failed to power up: %d\n", err);
765 goto err_pwr_on;
766 }
767
768 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
769 if (tegra_pcie.regs == NULL) {
770 pr_err("PCIE: Failed to map PCI/AFI registers\n");
771 err = -ENOMEM;
772 goto err_map_reg;
773 }
774
775 err = request_resource(&iomem_resource, res_mmio);
776 if (err) {
777 pr_err("PCIE: Failed to request resources: %d\n", err);
778 goto err_req_io;
779 }
780
781 tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
782 resource_size(res_mmio));
783 if (tegra_pcie_io_base == NULL) {
784 pr_err("PCIE: Failed to map IO\n");
785 err = -ENOMEM;
786 goto err_map_io;
787 }
788
789 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
790 IRQF_SHARED, "PCIE", &tegra_pcie);
791 if (err) {
792 pr_err("PCIE: Failed to register IRQ: %d\n", err);
793 goto err_irq;
794 }
795 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
796
797 return 0;
798
799 err_irq:
800 iounmap(tegra_pcie_io_base);
801 err_map_io:
802 release_resource(&tegra_pcie.res_mmio);
803 err_req_io:
804 iounmap(tegra_pcie.regs);
805 err_map_reg:
806 tegra_pcie_power_off();
807 err_pwr_on:
808 tegra_pcie_clocks_put();
809
810 return err;
811 }
812
813 /*
814 * FIXME: If there are no PCIe cards attached, then calling this function
815 * can result in the increase of the bootup time as there are big timeout
816 * loops.
817 */
818 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
819 static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
820 u32 reset_reg)
821 {
822 u32 reg;
823 int retries = 3;
824 int timeout;
825
826 do {
827 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
828 while (timeout) {
829 reg = readl(pp->base + RP_VEND_XP);
830
831 if (reg & RP_VEND_XP_DL_UP)
832 break;
833
834 mdelay(1);
835 timeout--;
836 }
837
838 if (!timeout) {
839 pr_err("PCIE: port %d: link down, retrying\n", idx);
840 goto retry;
841 }
842
843 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
844 while (timeout) {
845 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
846
847 if (reg & 0x20000000)
848 return true;
849
850 mdelay(1);
851 timeout--;
852 }
853
854 retry:
855 /* Pulse the PEX reset */
856 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
857 afi_writel(reg, reset_reg);
858 mdelay(1);
859 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
860 afi_writel(reg, reset_reg);
861
862 retries--;
863 } while (retries);
864
865 return false;
866 }
867
868 static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
869 {
870 struct tegra_pcie_port *pp;
871
872 pp = tegra_pcie.port + tegra_pcie.num_ports;
873
874 pp->index = -1;
875 pp->base = tegra_pcie.regs + offset;
876 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
877
878 if (!pp->link_up) {
879 pp->base = NULL;
880 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
881 return;
882 }
883
884 tegra_pcie.num_ports++;
885 pp->index = index;
886 pp->root_bus_nr = -1;
887 memset(pp->res, 0, sizeof(pp->res));
888 }
889
890 int __init tegra_pcie_init(bool init_port0, bool init_port1)
891 {
892 int err;
893
894 if (!(init_port0 || init_port1))
895 return -ENODEV;
896
897 err = tegra_pcie_get_resources();
898 if (err)
899 return err;
900
901 tegra_pcie_enable_controller();
902
903 /* setup the AFI address translations */
904 tegra_pcie_setup_translations();
905
906 if (init_port0)
907 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
908
909 if (init_port1)
910 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
911
912 pci_common_init(&tegra_pcie_hw);
913
914 return 0;
915 }
Linux with added FPC-III support