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Merge branch 'v6v7' into devel
[linux/fpc-iii.git] / arch / arm / plat-mxc / gpio.c
blobd17b3c996b840df35e326c7bb840854b9c5ee7b5
1 /*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <mach/hardware.h>
28 #include <asm-generic/bug.h>
29
30 static struct mxc_gpio_port *mxc_gpio_ports;
31 static int gpio_table_size;
32
33 #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
34
35 #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
36 #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
37 #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
38 #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
39 #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
40 #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
41 #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43 #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44 #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45 #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46 #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47 #define GPIO_INT_NONE 0x4
48
49 /* Note: This driver assumes 32 GPIOs are handled in one register */
50
51 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
52 {
53 __raw_writel(1 << index, port->base + GPIO_ISR);
54 }
55
56 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
57 int enable)
58 {
59 u32 l;
60
61 l = __raw_readl(port->base + GPIO_IMR);
62 l = (l & (~(1 << index))) | (!!enable << index);
63 __raw_writel(l, port->base + GPIO_IMR);
64 }
65
66 static void gpio_ack_irq(struct irq_data *d)
67 {
68 u32 gpio = irq_to_gpio(d->irq);
69 _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
70 }
71
72 static void gpio_mask_irq(struct irq_data *d)
73 {
74 u32 gpio = irq_to_gpio(d->irq);
75 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
76 }
77
78 static void gpio_unmask_irq(struct irq_data *d)
79 {
80 u32 gpio = irq_to_gpio(d->irq);
81 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
82 }
83
84 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
85
86 static int gpio_set_irq_type(struct irq_data *d, u32 type)
87 {
88 u32 gpio = irq_to_gpio(d->irq);
89 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
90 u32 bit, val;
91 int edge;
92 void __iomem *reg = port->base;
93
94 port->both_edges &= ~(1 << (gpio & 31));
95 switch (type) {
96 case IRQ_TYPE_EDGE_RISING:
97 edge = GPIO_INT_RISE_EDGE;
98 break;
99 case IRQ_TYPE_EDGE_FALLING:
100 edge = GPIO_INT_FALL_EDGE;
101 break;
102 case IRQ_TYPE_EDGE_BOTH:
103 val = mxc_gpio_get(&port->chip, gpio & 31);
104 if (val) {
105 edge = GPIO_INT_LOW_LEV;
106 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
107 } else {
108 edge = GPIO_INT_HIGH_LEV;
109 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
110 }
111 port->both_edges |= 1 << (gpio & 31);
112 break;
113 case IRQ_TYPE_LEVEL_LOW:
114 edge = GPIO_INT_LOW_LEV;
115 break;
116 case IRQ_TYPE_LEVEL_HIGH:
117 edge = GPIO_INT_HIGH_LEV;
118 break;
119 default:
120 return -EINVAL;
121 }
122
123 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
124 bit = gpio & 0xf;
125 val = __raw_readl(reg) & ~(0x3 << (bit << 1));
126 __raw_writel(val | (edge << (bit << 1)), reg);
127 _clear_gpio_irqstatus(port, gpio & 0x1f);
128
129 return 0;
130 }
131
132 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
133 {
134 void __iomem *reg = port->base;
135 u32 bit, val;
136 int edge;
137
138 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
139 bit = gpio & 0xf;
140 val = __raw_readl(reg);
141 edge = (val >> (bit << 1)) & 3;
142 val &= ~(0x3 << (bit << 1));
143 if (edge == GPIO_INT_HIGH_LEV) {
144 edge = GPIO_INT_LOW_LEV;
145 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
146 } else if (edge == GPIO_INT_LOW_LEV) {
147 edge = GPIO_INT_HIGH_LEV;
148 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
149 } else {
150 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
151 gpio, edge);
152 return;
153 }
154 __raw_writel(val | (edge << (bit << 1)), reg);
155 }
156
157 /* handle 32 interrupts in one status register */
158 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
159 {
160 u32 gpio_irq_no_base = port->virtual_irq_start;
161
162 while (irq_stat != 0) {
163 int irqoffset = fls(irq_stat) - 1;
164
165 if (port->both_edges & (1 << irqoffset))
166 mxc_flip_edge(port, irqoffset);
167
168 generic_handle_irq(gpio_irq_no_base + irqoffset);
169
170 irq_stat &= ~(1 << irqoffset);
171 }
172 }
173
174 /* MX1 and MX3 has one interrupt *per* gpio port */
175 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176 {
177 u32 irq_stat;
178 struct mxc_gpio_port *port = get_irq_data(irq);
179
180 irq_stat = __raw_readl(port->base + GPIO_ISR) &
181 __raw_readl(port->base + GPIO_IMR);
182
183 mxc_gpio_irq_handler(port, irq_stat);
184 }
185
186 /* MX2 has one interrupt *for all* gpio ports */
187 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
188 {
189 int i;
190 u32 irq_msk, irq_stat;
191 struct mxc_gpio_port *port = get_irq_data(irq);
192
193 /* walk through all interrupt status registers */
194 for (i = 0; i < gpio_table_size; i++) {
195 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
196 if (!irq_msk)
197 continue;
198
199 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
200 if (irq_stat)
201 mxc_gpio_irq_handler(&port[i], irq_stat);
202 }
203 }
204
205 /*
206 * Set interrupt number "irq" in the GPIO as a wake-up source.
207 * While system is running, all registered GPIO interrupts need to have
208 * wake-up enabled. When system is suspended, only selected GPIO interrupts
209 * need to have wake-up enabled.
210 * @param irq interrupt source number
211 * @param enable enable as wake-up if equal to non-zero
212 * @return This function returns 0 on success.
213 */
214 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
215 {
216 u32 gpio = irq_to_gpio(d->irq);
217 u32 gpio_idx = gpio & 0x1F;
218 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
219
220 if (enable) {
221 if (port->irq_high && (gpio_idx >= 16))
222 enable_irq_wake(port->irq_high);
223 else
224 enable_irq_wake(port->irq);
225 } else {
226 if (port->irq_high && (gpio_idx >= 16))
227 disable_irq_wake(port->irq_high);
228 else
229 disable_irq_wake(port->irq);
230 }
231
232 return 0;
233 }
234
235 static struct irq_chip gpio_irq_chip = {
236 .irq_ack = gpio_ack_irq,
237 .irq_mask = gpio_mask_irq,
238 .irq_unmask = gpio_unmask_irq,
239 .irq_set_type = gpio_set_irq_type,
240 .irq_set_wake = gpio_set_wake_irq,
241 };
242
243 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
244 int dir)
245 {
246 struct mxc_gpio_port *port =
247 container_of(chip, struct mxc_gpio_port, chip);
248 u32 l;
249 unsigned long flags;
250
251 spin_lock_irqsave(&port->lock, flags);
252 l = __raw_readl(port->base + GPIO_GDIR);
253 if (dir)
254 l |= 1 << offset;
255 else
256 l &= ~(1 << offset);
257 __raw_writel(l, port->base + GPIO_GDIR);
258 spin_unlock_irqrestore(&port->lock, flags);
259 }
260
261 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
262 {
263 struct mxc_gpio_port *port =
264 container_of(chip, struct mxc_gpio_port, chip);
265 void __iomem *reg = port->base + GPIO_DR;
266 u32 l;
267 unsigned long flags;
268
269 spin_lock_irqsave(&port->lock, flags);
270 l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
271 __raw_writel(l, reg);
272 spin_unlock_irqrestore(&port->lock, flags);
273 }
274
275 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
276 {
277 struct mxc_gpio_port *port =
278 container_of(chip, struct mxc_gpio_port, chip);
279
280 return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
281 }
282
283 static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
284 {
285 _set_gpio_direction(chip, offset, 0);
286 return 0;
287 }
288
289 static int mxc_gpio_direction_output(struct gpio_chip *chip,
290 unsigned offset, int value)
291 {
292 mxc_gpio_set(chip, offset, value);
293 _set_gpio_direction(chip, offset, 1);
294 return 0;
295 }
296
297 int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
298 {
299 int i, j;
300
301 /* save for local usage */
302 mxc_gpio_ports = port;
303 gpio_table_size = cnt;
304
305 printk(KERN_INFO "MXC GPIO hardware\n");
306
307 for (i = 0; i < cnt; i++) {
308 /* disable the interrupt and clear the status */
309 __raw_writel(0, port[i].base + GPIO_IMR);
310 __raw_writel(~0, port[i].base + GPIO_ISR);
311 for (j = port[i].virtual_irq_start;
312 j < port[i].virtual_irq_start + 32; j++) {
313 set_irq_chip(j, &gpio_irq_chip);
314 set_irq_handler(j, handle_level_irq);
315 set_irq_flags(j, IRQF_VALID);
316 }
317
318 /* register gpio chip */
319 port[i].chip.direction_input = mxc_gpio_direction_input;
320 port[i].chip.direction_output = mxc_gpio_direction_output;
321 port[i].chip.get = mxc_gpio_get;
322 port[i].chip.set = mxc_gpio_set;
323 port[i].chip.base = i * 32;
324 port[i].chip.ngpio = 32;
325
326 spin_lock_init(&port[i].lock);
327
328 /* its a serious configuration bug when it fails */
329 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
330
331 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
332 /* setup one handler for each entry */
333 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
334 set_irq_data(port[i].irq, &port[i]);
335 if (port[i].irq_high) {
336 /* setup handler for GPIO 16 to 31 */
337 set_irq_chained_handler(port[i].irq_high,
338 mx3_gpio_irq_handler);
339 set_irq_data(port[i].irq_high, &port[i]);
340 }
341 }
342 }
343
344 if (cpu_is_mx2()) {
345 /* setup one handler for all GPIO interrupts */
346 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
347 set_irq_data(port[0].irq, port);
348 }
349
350 return 0;
351 }
352
353 #define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
354 { \
355 .chip.label = "gpio-" #_id, \
356 .irq = _irq, \
357 .irq_high = _irq_high, \
358 .base = soc ## _IO_ADDRESS( \
359 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
360 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
361 }
362
363 #define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
364 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
365 #define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
366 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
367
368 #define DEFINE_REGISTER_FUNCTION(prefix) \
369 int __init prefix ## _register_gpios(void) \
370 { \
371 return mxc_gpio_init(prefix ## _gpio_ports, \
372 ARRAY_SIZE(prefix ## _gpio_ports)); \
373 }
374
375 #if defined(CONFIG_SOC_IMX1)
376 static struct mxc_gpio_port imx1_gpio_ports[] = {
377 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
378 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
379 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
380 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
381 };
382
383 DEFINE_REGISTER_FUNCTION(imx1)
384
385 #endif /* if defined(CONFIG_SOC_IMX1) */
386
387 #if defined(CONFIG_SOC_IMX21)
388 static struct mxc_gpio_port imx21_gpio_ports[] = {
389 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
390 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
391 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
392 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
393 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
394 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
395 };
396
397 DEFINE_REGISTER_FUNCTION(imx21)
398
399 #endif /* if defined(CONFIG_SOC_IMX21) */
400
401 #if defined(CONFIG_SOC_IMX25)
402 static struct mxc_gpio_port imx25_gpio_ports[] = {
403 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
404 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
405 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
406 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
407 };
408
409 DEFINE_REGISTER_FUNCTION(imx25)
410
411 #endif /* if defined(CONFIG_SOC_IMX25) */
412
413 #if defined(CONFIG_SOC_IMX27)
414 static struct mxc_gpio_port imx27_gpio_ports[] = {
415 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
416 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
417 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
418 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
419 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
420 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
421 };
422
423 DEFINE_REGISTER_FUNCTION(imx27)
424
425 #endif /* if defined(CONFIG_SOC_IMX27) */
426
427 #if defined(CONFIG_SOC_IMX31)
428 static struct mxc_gpio_port imx31_gpio_ports[] = {
429 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
430 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
431 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
432 };
433
434 DEFINE_REGISTER_FUNCTION(imx31)
435
436 #endif /* if defined(CONFIG_SOC_IMX31) */
437
438 #if defined(CONFIG_SOC_IMX35)
439 static struct mxc_gpio_port imx35_gpio_ports[] = {
440 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
441 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
442 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
443 };
444
445 DEFINE_REGISTER_FUNCTION(imx35)
446
447 #endif /* if defined(CONFIG_SOC_IMX35) */
448
449 #if defined(CONFIG_SOC_IMX50)
450 static struct mxc_gpio_port imx50_gpio_ports[] = {
451 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
452 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
453 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
454 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
455 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
456 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
457 };
458
459 DEFINE_REGISTER_FUNCTION(imx50)
460
461 #endif /* if defined(CONFIG_SOC_IMX50) */
Linux with added FPC-III support