| blob | 087cd7ac8d5228264e68c347b17011aa8363bbd1 |
1 #ifndef __MACH_MX25_H__
2 #define __MACH_MX25_H__
4 #define MX25_AIPS1_BASE_ADDR 0x43f00000
5 #define MX25_AIPS1_SIZE SZ_1M
6 #define MX25_AIPS2_BASE_ADDR 0x53f00000
7 #define MX25_AIPS2_SIZE SZ_1M
8 #define MX25_AVIC_BASE_ADDR 0x68000000
9 #define MX25_AVIC_SIZE SZ_1M
11 #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
12 #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
13 #define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
14 #define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
15 #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
16 #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
17 #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
19 #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20 #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21 #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22 #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23 #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24 #define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25 #define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26 #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27 #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
28 #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29 #define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
31 #define MX25_UART1_BASE_ADDR 0x43f90000
32 #define MX25_UART2_BASE_ADDR 0x43f94000
33 #define MX25_AUDMUX_BASE_ADDR 0x43fb0000
34 #define MX25_UART3_BASE_ADDR 0x5000c000
35 #define MX25_UART4_BASE_ADDR 0x50008000
36 #define MX25_UART5_BASE_ADDR 0x5002c000
38 #define MX25_CSPI3_BASE_ADDR 0x50004000
39 #define MX25_CSPI2_BASE_ADDR 0x50010000
40 #define MX25_FEC_BASE_ADDR 0x50038000
41 #define MX25_SSI2_BASE_ADDR 0x50014000
42 #define MX25_SSI1_BASE_ADDR 0x50034000
43 #define MX25_NFC_BASE_ADDR 0xbb000000
44 #define MX25_DRYICE_BASE_ADDR 0x53ffc000
45 #define MX25_ESDHC1_BASE_ADDR 0x53fb4000
46 #define MX25_ESDHC2_BASE_ADDR 0x53fb8000
47 #define MX25_LCDC_BASE_ADDR 0x53fbc000
48 #define MX25_KPP_BASE_ADDR 0x43fa8000
49 #define MX25_SDMA_BASE_ADDR 0x53fd4000
50 #define MX25_USB_BASE_ADDR 0x53ff4000
51 #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
52 /*
53 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
54 * for the host controller. Early documentation drafts specified 0x400 and
55 * Freescale internal sources confirm only the latter value to work.
56 */
57 #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
58 #define MX25_CSI_BASE_ADDR 0x53ff8000
60 #define MX25_IO_P2V(x) IMX_IO_P2V(x)
61 #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63 #define MX25_INT_CSPI3 0
64 #define MX25_INT_I2C1 3
65 #define MX25_INT_I2C2 4
66 #define MX25_INT_UART4 5
67 #define MX25_INT_ESDHC2 8
68 #define MX25_INT_ESDHC1 9
69 #define MX25_INT_I2C3 10
70 #define MX25_INT_SSI2 11
71 #define MX25_INT_SSI1 12
72 #define MX25_INT_CSPI2 13
73 #define MX25_INT_CSPI1 14
74 #define MX25_INT_GPIO3 16
75 #define MX25_INT_CSI 17
76 #define MX25_INT_UART3 18
77 #define MX25_INT_GPIO4 23
78 #define MX25_INT_KPP 24
79 #define MX25_INT_DRYICE 25
80 #define MX25_INT_PWM1 26
81 #define MX25_INT_UART2 32
82 #define MX25_INT_NFC 33
83 #define MX25_INT_SDMA 34
84 #define MX25_INT_USB_HS 35
85 #define MX25_INT_PWM2 36
86 #define MX25_INT_USB_OTG 37
87 #define MX25_INT_LCDC 39
88 #define MX25_INT_UART5 40
89 #define MX25_INT_PWM3 41
90 #define MX25_INT_PWM4 42
91 #define MX25_INT_CAN1 43
92 #define MX25_INT_CAN2 44
93 #define MX25_INT_UART1 45
94 #define MX25_INT_GPIO2 51
95 #define MX25_INT_GPIO1 52
96 #define MX25_INT_FEC 57
98 #define MX25_DMA_REQ_SSI2_RX1 22
99 #define MX25_DMA_REQ_SSI2_TX1 23
100 #define MX25_DMA_REQ_SSI2_RX0 24
101 #define MX25_DMA_REQ_SSI2_TX0 25
102 #define MX25_DMA_REQ_SSI1_RX1 26
103 #define MX25_DMA_REQ_SSI1_TX1 27
104 #define MX25_DMA_REQ_SSI1_RX0 28
105 #define MX25_DMA_REQ_SSI1_TX0 29