arch/arm/plat-s3c24xx/clock.c

   1 /* linux/arch/arm/plat-s3c24xx/clock.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C24XX Core clock control support
   7  *
   8  * Based on, and code from linux/arch/arm/mach-versatile/clock.c
   9  **
  10  **  Copyright (C) 2004 ARM Limited.
  11  **  Written by Deep Blue Solutions Limited.
  12  *
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/clk.h>
  32 #include <linux/io.h>
  33
  34 #include <mach/hardware.h>
  35 #include <asm/irq.h>
  36
  37 #include <mach/regs-clock.h>
  38 #include <mach/regs-gpio.h>
  39
  40 #include <plat/cpu-freq.h>
  41
  42 #include <plat/clock.h>
  43 #include <plat/cpu.h>
  44 #include <plat/pll.h>
  45
  46 /* initialise all the clocks */
  47
  48 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
  49                                            unsigned long hclk,
  50                                            unsigned long pclk)
  51 {
  52         clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
  53                                         clk_xtal.rate);
  54
  55         clk_mpll.rate = fclk;
  56         clk_h.rate = hclk;
  57         clk_p.rate = pclk;
  58         clk_f.rate = fclk;
  59 }