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Merge branch 'v6v7' into devel
[linux/fpc-iii.git] / drivers / media / video / cx231xx / cx231xx-avcore.c
blobc53e97295a0d1d460d5117641e332c1ff109494a
1 /*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
32 #include <linux/mm.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
35
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
39
40 #include "cx231xx.h"
41 #include "cx231xx-dif.h"
42
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
47 [I2S audio] |
48 |
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
51 |
52 |-> Cx25840 --> Video
53 [Video]
54
55 *******************************************************************************/
56 /******************************************************************************
57 * VERVE REGISTER *
58 * *
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61 {
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
63 saddr, 1, data, 1);
64 }
65
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
67 {
68 int status;
69 u32 temp = 0;
70
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
72 saddr, 1, &temp, 1);
73 *data = (u8) temp;
74 return status;
75 }
76 void initGPIO(struct cx231xx *dev)
77 {
78 u32 _gpio_direction = 0;
79 u32 value = 0;
80 u8 val = 0;
81
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
85
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
91
92 cx231xx_capture_start(dev, 1, 2);
93
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
96
97 }
98 void uninitGPIO(struct cx231xx *dev)
99 {
100 u8 value[4] = { 0, 0, 0, 0 };
101
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
105 0x68, value, 4);
106 }
107
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
113 {
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
115 saddr, 2, data, 1);
116 }
117
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
119 {
120 int status;
121 u32 temp = 0;
122
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
124 saddr, 2, &temp, 1);
125 *data = (u8) temp;
126 return status;
127 }
128
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
130 {
131 int status = 0;
132 u8 temp = 0;
133 u8 afe_power_status = 0;
134 int i = 0;
135
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
139 if (status < 0)
140 return status;
141
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
143 if (status < 0)
144 return status;
145
146 temp = (u8) ((ref_count & 0x300) >> 8);
147 temp |= 0x40;
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
149 if (status < 0)
150 return status;
151
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
153 if (status < 0)
154 return status;
155
156 /* enable pll */
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
159 if (status < 0) {
160 cx231xx_info(
161 ": Init Super Block failed in send cmd\n");
162 break;
163 }
164
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
167 if (status < 0) {
168 cx231xx_info(
169 ": Init Super Block failed in receive cmd\n");
170 break;
171 }
172 i++;
173 if (i == 10) {
174 cx231xx_info(
175 ": Init Super Block force break in loop !!!!\n");
176 status = -1;
177 break;
178 }
179 }
180
181 if (status < 0)
182 return status;
183
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
186 if (status < 0)
187 return status;
188
189 msleep(5);
190
191 /* exit tuning */
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
193
194 return status;
195 }
196
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
198 {
199 int status = 0;
200
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
205
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
208
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
213
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
218 msleep(5);
219
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
224
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
229
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
237
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
242
243 return status;
244 }
245
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
247 {
248 u8 c_value = 0;
249 int status = 0;
250
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
254
255 return status;
256 }
257
258 /*
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
262
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
266 */
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
268 {
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
272 int status = 0;
273 u8 value = 0;
274
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= ~INPUT_SEL_MASK;
278 value |= (ch1_setting - 1) << 4;
279 value &= 0xff;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
281 }
282
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= ~INPUT_SEL_MASK;
286 value |= (ch2_setting - 1) << 4;
287 value &= 0xff;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
289 }
290
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= ~INPUT_SEL_MASK;
296 value |= (ch3_setting - 1) << 4;
297 value &= 0xff;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
299 }
300
301 return status;
302 }
303
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
305 {
306 int status = 0;
307
308 /*
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
311 */
312
313 switch (mode) {
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
316 break;
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
319 break;
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
322 break;
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
325 break;
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
328 break;
329 }
330
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
335
336 dev->afe_mode = mode;
337
338 return status;
339 }
340
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
342 enum AV_MODE avmode)
343 {
344 u8 afe_power_status = 0;
345 int status = 0;
346
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
358 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
359 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
360 FLD_PWRDN_ENABLE_PLL)) {
361 status = afe_write_byte(dev, SUP_BLK_PWRDN,
362 FLD_PWRDN_TUNING_BIAS |
363 FLD_PWRDN_ENABLE_PLL);
364 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
365 &afe_power_status);
366 if (status < 0)
367 break;
368 }
369
370 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
371 0x00);
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
373 0x00);
374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
375 0x00);
376 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
377 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
378 0x70);
379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
380 0x70);
381 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
382 0x70);
383
384 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
385 &afe_power_status);
386 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
387 FLD_PWRDN_PD_BIAS |
388 FLD_PWRDN_PD_TUNECK;
389 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
390 afe_power_status);
391 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
392 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
393 FLD_PWRDN_ENABLE_PLL)) {
394 status = afe_write_byte(dev, SUP_BLK_PWRDN,
395 FLD_PWRDN_TUNING_BIAS |
396 FLD_PWRDN_ENABLE_PLL);
397 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
398 &afe_power_status);
399 if (status < 0)
400 break;
401 }
402
403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
404 0x00);
405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
406 0x00);
407 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
408 0x00);
409 } else {
410 cx231xx_info("Invalid AV mode input\n");
411 status = -1;
412 }
413 break;
414 default:
415 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
416 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
417 FLD_PWRDN_ENABLE_PLL)) {
418 status = afe_write_byte(dev, SUP_BLK_PWRDN,
419 FLD_PWRDN_TUNING_BIAS |
420 FLD_PWRDN_ENABLE_PLL);
421 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
422 &afe_power_status);
423 if (status < 0)
424 break;
425 }
426
427 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
428 0x40);
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
430 0x40);
431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
432 0x00);
433 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
434 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
435 0x70);
436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
437 0x70);
438 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
439 0x70);
440
441 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
442 &afe_power_status);
443 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
444 FLD_PWRDN_PD_BIAS |
445 FLD_PWRDN_PD_TUNECK;
446 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
447 afe_power_status);
448 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
449 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
450 FLD_PWRDN_ENABLE_PLL)) {
451 status = afe_write_byte(dev, SUP_BLK_PWRDN,
452 FLD_PWRDN_TUNING_BIAS |
453 FLD_PWRDN_ENABLE_PLL);
454 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
455 &afe_power_status);
456 if (status < 0)
457 break;
458 }
459
460 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
461 0x00);
462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
463 0x00);
464 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
465 0x40);
466 } else {
467 cx231xx_info("Invalid AV mode input\n");
468 status = -1;
469 }
470 } /* switch */
471
472 return status;
473 }
474
475 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
476 {
477 u8 input_mode = 0;
478 u8 ntf_mode = 0;
479 int status = 0;
480
481 dev->video_input = video_input;
482
483 if (video_input == CX231XX_VMUX_TELEVISION) {
484 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
485 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
486 &ntf_mode);
487 } else {
488 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
489 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
490 &ntf_mode);
491 }
492
493 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
494
495 switch (input_mode) {
496 case SINGLE_ENDED:
497 dev->afe_ref_count = 0x23C;
498 break;
499 case LOW_IF:
500 dev->afe_ref_count = 0x24C;
501 break;
502 case EU_IF:
503 dev->afe_ref_count = 0x258;
504 break;
505 case US_IF:
506 dev->afe_ref_count = 0x260;
507 break;
508 default:
509 break;
510 }
511
512 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
513
514 return status;
515 }
516
517 /******************************************************************************
518 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
519 ******************************************************************************/
520 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
521 {
522 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
523 saddr, 2, data, 1);
524 }
525
526 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
527 {
528 int status;
529 u32 temp = 0;
530
531 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
532 saddr, 2, &temp, 1);
533 *data = (u8) temp;
534 return status;
535 }
536
537 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
538 {
539 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
540 saddr, 2, data, 4);
541 }
542
543 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
544 {
545 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
546 saddr, 2, data, 4);
547 }
548 int cx231xx_check_fw(struct cx231xx *dev)
549 {
550 u8 temp = 0;
551 int status = 0;
552 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
553 if (status < 0)
554 return status;
555 else
556 return temp;
557
558 }
559
560 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
561 {
562 int status = 0;
563
564 switch (INPUT(input)->type) {
565 case CX231XX_VMUX_COMPOSITE1:
566 case CX231XX_VMUX_SVIDEO:
567 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
568 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
569 /* External AV */
570 status = cx231xx_set_power_mode(dev,
571 POLARIS_AVMODE_ENXTERNAL_AV);
572 if (status < 0) {
573 cx231xx_errdev("%s: set_power_mode : Failed to"
574 " set Power - errCode [%d]!\n",
575 __func__, status);
576 return status;
577 }
578 }
579 status = cx231xx_set_decoder_video_input(dev,
580 INPUT(input)->type,
581 INPUT(input)->vmux);
582 break;
583 case CX231XX_VMUX_TELEVISION:
584 case CX231XX_VMUX_CABLE:
585 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
586 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
587 /* Tuner */
588 status = cx231xx_set_power_mode(dev,
589 POLARIS_AVMODE_ANALOGT_TV);
590 if (status < 0) {
591 cx231xx_errdev("%s: set_power_mode:Failed"
592 " to set Power - errCode [%d]!\n",
593 __func__, status);
594 return status;
595 }
596 }
597 if (dev->tuner_type == TUNER_NXP_TDA18271)
598 status = cx231xx_set_decoder_video_input(dev,
599 CX231XX_VMUX_TELEVISION,
600 INPUT(input)->vmux);
601 else
602 status = cx231xx_set_decoder_video_input(dev,
603 CX231XX_VMUX_COMPOSITE1,
604 INPUT(input)->vmux);
605
606 break;
607 default:
608 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
609 __func__, INPUT(input)->type);
610 break;
611 }
612
613 /* save the selection */
614 dev->video_input = input;
615
616 return status;
617 }
618
619 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
620 u8 pin_type, u8 input)
621 {
622 int status = 0;
623 u32 value = 0;
624
625 if (pin_type != dev->video_input) {
626 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
627 if (status < 0) {
628 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
629 "AFE input mux - errCode [%d]!\n",
630 __func__, status);
631 return status;
632 }
633 }
634
635 /* call afe block to set video inputs */
636 status = cx231xx_afe_set_input_mux(dev, input);
637 if (status < 0) {
638 cx231xx_errdev("%s: set_input_mux :Failed to set"
639 " AFE input mux - errCode [%d]!\n",
640 __func__, status);
641 return status;
642 }
643
644 switch (pin_type) {
645 case CX231XX_VMUX_COMPOSITE1:
646 status = vid_blk_read_word(dev, AFE_CTRL, &value);
647 value |= (0 << 13) | (1 << 4);
648 value &= ~(1 << 5);
649
650 /* set [24:23] [22:15] to 0 */
651 value &= (~(0x1ff8000));
652 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
653 value |= 0x1000000;
654 status = vid_blk_write_word(dev, AFE_CTRL, value);
655
656 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
657 value |= (1 << 7);
658 status = vid_blk_write_word(dev, OUT_CTRL1, value);
659
660 /* Set output mode */
661 status = cx231xx_read_modify_write_i2c_dword(dev,
662 VID_BLK_I2C_ADDRESS,
663 OUT_CTRL1,
664 FLD_OUT_MODE,
665 dev->board.output_mode);
666
667 /* Tell DIF object to go to baseband mode */
668 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
669 if (status < 0) {
670 cx231xx_errdev("%s: cx231xx_dif set to By pass"
671 " mode- errCode [%d]!\n",
672 __func__, status);
673 return status;
674 }
675
676 /* Read the DFE_CTRL1 register */
677 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
678
679 /* enable the VBI_GATE_EN */
680 value |= FLD_VBI_GATE_EN;
681
682 /* Enable the auto-VGA enable */
683 value |= FLD_VGA_AUTO_EN;
684
685 /* Write it back */
686 status = vid_blk_write_word(dev, DFE_CTRL1, value);
687
688 /* Disable auto config of registers */
689 status = cx231xx_read_modify_write_i2c_dword(dev,
690 VID_BLK_I2C_ADDRESS,
691 MODE_CTRL, FLD_ACFG_DIS,
692 cx231xx_set_field(FLD_ACFG_DIS, 1));
693
694 /* Set CVBS input mode */
695 status = cx231xx_read_modify_write_i2c_dword(dev,
696 VID_BLK_I2C_ADDRESS,
697 MODE_CTRL, FLD_INPUT_MODE,
698 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
699 break;
700 case CX231XX_VMUX_SVIDEO:
701 /* Disable the use of DIF */
702
703 status = vid_blk_read_word(dev, AFE_CTRL, &value);
704
705 /* set [24:23] [22:15] to 0 */
706 value &= (~(0x1ff8000));
707 /* set FUNC_MODE[24:23] = 2
708 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
709 value |= 0x1000010;
710 status = vid_blk_write_word(dev, AFE_CTRL, value);
711
712 /* Tell DIF object to go to baseband mode */
713 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
714 if (status < 0) {
715 cx231xx_errdev("%s: cx231xx_dif set to By pass"
716 " mode- errCode [%d]!\n",
717 __func__, status);
718 return status;
719 }
720
721 /* Read the DFE_CTRL1 register */
722 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
723
724 /* enable the VBI_GATE_EN */
725 value |= FLD_VBI_GATE_EN;
726
727 /* Enable the auto-VGA enable */
728 value |= FLD_VGA_AUTO_EN;
729
730 /* Write it back */
731 status = vid_blk_write_word(dev, DFE_CTRL1, value);
732
733 /* Disable auto config of registers */
734 status = cx231xx_read_modify_write_i2c_dword(dev,
735 VID_BLK_I2C_ADDRESS,
736 MODE_CTRL, FLD_ACFG_DIS,
737 cx231xx_set_field(FLD_ACFG_DIS, 1));
738
739 /* Set YC input mode */
740 status = cx231xx_read_modify_write_i2c_dword(dev,
741 VID_BLK_I2C_ADDRESS,
742 MODE_CTRL,
743 FLD_INPUT_MODE,
744 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
745
746 /* Chroma to ADC2 */
747 status = vid_blk_read_word(dev, AFE_CTRL, &value);
748 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
749
750 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
751 This sets them to use video
752 rather than audio. Only one of the two will be in use. */
753 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
754
755 status = vid_blk_write_word(dev, AFE_CTRL, value);
756
757 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
758 break;
759 case CX231XX_VMUX_TELEVISION:
760 case CX231XX_VMUX_CABLE:
761 default:
762 switch (dev->model) {
763 case CX231XX_BOARD_CNXT_CARRAERA:
764 case CX231XX_BOARD_CNXT_RDE_250:
765 case CX231XX_BOARD_CNXT_SHELBY:
766 case CX231XX_BOARD_CNXT_RDU_250:
767 /* Disable the use of DIF */
768
769 status = vid_blk_read_word(dev, AFE_CTRL, &value);
770 value |= (0 << 13) | (1 << 4);
771 value &= ~(1 << 5);
772
773 /* set [24:23] [22:15] to 0 */
774 value &= (~(0x1FF8000));
775 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
776 value |= 0x1000000;
777 status = vid_blk_write_word(dev, AFE_CTRL, value);
778
779 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
780 value |= (1 << 7);
781 status = vid_blk_write_word(dev, OUT_CTRL1, value);
782
783 /* Set output mode */
784 status = cx231xx_read_modify_write_i2c_dword(dev,
785 VID_BLK_I2C_ADDRESS,
786 OUT_CTRL1, FLD_OUT_MODE,
787 dev->board.output_mode);
788
789 /* Tell DIF object to go to baseband mode */
790 status = cx231xx_dif_set_standard(dev,
791 DIF_USE_BASEBAND);
792 if (status < 0) {
793 cx231xx_errdev("%s: cx231xx_dif set to By pass"
794 " mode- errCode [%d]!\n",
795 __func__, status);
796 return status;
797 }
798
799 /* Read the DFE_CTRL1 register */
800 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
801
802 /* enable the VBI_GATE_EN */
803 value |= FLD_VBI_GATE_EN;
804
805 /* Enable the auto-VGA enable */
806 value |= FLD_VGA_AUTO_EN;
807
808 /* Write it back */
809 status = vid_blk_write_word(dev, DFE_CTRL1, value);
810
811 /* Disable auto config of registers */
812 status = cx231xx_read_modify_write_i2c_dword(dev,
813 VID_BLK_I2C_ADDRESS,
814 MODE_CTRL, FLD_ACFG_DIS,
815 cx231xx_set_field(FLD_ACFG_DIS, 1));
816
817 /* Set CVBS input mode */
818 status = cx231xx_read_modify_write_i2c_dword(dev,
819 VID_BLK_I2C_ADDRESS,
820 MODE_CTRL, FLD_INPUT_MODE,
821 cx231xx_set_field(FLD_INPUT_MODE,
822 INPUT_MODE_CVBS_0));
823 break;
824 default:
825 /* Enable the DIF for the tuner */
826
827 /* Reinitialize the DIF */
828 status = cx231xx_dif_set_standard(dev, dev->norm);
829 if (status < 0) {
830 cx231xx_errdev("%s: cx231xx_dif set to By pass"
831 " mode- errCode [%d]!\n",
832 __func__, status);
833 return status;
834 }
835
836 /* Make sure bypass is cleared */
837 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
838
839 /* Clear the bypass bit */
840 value &= ~FLD_DIF_DIF_BYPASS;
841
842 /* Enable the use of the DIF block */
843 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
844
845 /* Read the DFE_CTRL1 register */
846 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
847
848 /* Disable the VBI_GATE_EN */
849 value &= ~FLD_VBI_GATE_EN;
850
851 /* Enable the auto-VGA enable, AGC, and
852 set the skip count to 2 */
853 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
854
855 /* Write it back */
856 status = vid_blk_write_word(dev, DFE_CTRL1, value);
857
858 /* Wait until AGC locks up */
859 msleep(1);
860
861 /* Disable the auto-VGA enable AGC */
862 value &= ~(FLD_VGA_AUTO_EN);
863
864 /* Write it back */
865 status = vid_blk_write_word(dev, DFE_CTRL1, value);
866
867 /* Enable Polaris B0 AGC output */
868 status = vid_blk_read_word(dev, PIN_CTRL, &value);
869 value |= (FLD_OEF_AGC_RF) |
870 (FLD_OEF_AGC_IFVGA) |
871 (FLD_OEF_AGC_IF);
872 status = vid_blk_write_word(dev, PIN_CTRL, value);
873
874 /* Set output mode */
875 status = cx231xx_read_modify_write_i2c_dword(dev,
876 VID_BLK_I2C_ADDRESS,
877 OUT_CTRL1, FLD_OUT_MODE,
878 dev->board.output_mode);
879
880 /* Disable auto config of registers */
881 status = cx231xx_read_modify_write_i2c_dword(dev,
882 VID_BLK_I2C_ADDRESS,
883 MODE_CTRL, FLD_ACFG_DIS,
884 cx231xx_set_field(FLD_ACFG_DIS, 1));
885
886 /* Set CVBS input mode */
887 status = cx231xx_read_modify_write_i2c_dword(dev,
888 VID_BLK_I2C_ADDRESS,
889 MODE_CTRL, FLD_INPUT_MODE,
890 cx231xx_set_field(FLD_INPUT_MODE,
891 INPUT_MODE_CVBS_0));
892
893 /* Set some bits in AFE_CTRL so that channel 2 or 3
894 * is ready to receive audio */
895 /* Clear clamp for channels 2 and 3 (bit 16-17) */
896 /* Clear droop comp (bit 19-20) */
897 /* Set VGA_SEL (for audio control) (bit 7-8) */
898 status = vid_blk_read_word(dev, AFE_CTRL, &value);
899
900 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
901 value &= (~(FLD_FUNC_MODE));
902 value |= 0x800000;
903
904 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
905
906 status = vid_blk_write_word(dev, AFE_CTRL, value);
907
908 if (dev->tuner_type == TUNER_NXP_TDA18271) {
909 status = vid_blk_read_word(dev, PIN_CTRL,
910 &value);
911 status = vid_blk_write_word(dev, PIN_CTRL,
912 (value & 0xFFFFFFEF));
913 }
914
915 break;
916
917 }
918 break;
919 }
920
921 /* Set raw VBI mode */
922 status = cx231xx_read_modify_write_i2c_dword(dev,
923 VID_BLK_I2C_ADDRESS,
924 OUT_CTRL1, FLD_VBIHACTRAW_EN,
925 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
926
927 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
928 if (value & 0x02) {
929 value |= (1 << 19);
930 status = vid_blk_write_word(dev, OUT_CTRL1, value);
931 }
932
933 return status;
934 }
935
936 void cx231xx_enable656(struct cx231xx *dev)
937 {
938 u8 temp = 0;
939 int status;
940 /*enable TS1 data[0:7] as output to export 656*/
941
942 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
943
944 /*enable TS1 clock as output to export 656*/
945
946 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
947 temp = temp|0x04;
948
949 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
950
951 }
952 EXPORT_SYMBOL_GPL(cx231xx_enable656);
953
954 void cx231xx_disable656(struct cx231xx *dev)
955 {
956 u8 temp = 0;
957 int status;
958
959
960 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
961
962 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
963 temp = temp&0xFB;
964
965 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
966 }
967 EXPORT_SYMBOL_GPL(cx231xx_disable656);
968
969 /*
970 * Handle any video-mode specific overrides that are different
971 * on a per video standards basis after touching the MODE_CTRL
972 * register which resets many values for autodetect
973 */
974 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
975 {
976 int status = 0;
977
978 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
979 (unsigned int)dev->norm);
980
981 /* Change the DFE_CTRL3 bp_percent to fix flagging */
982 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
983
984 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
985 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
986
987 /* Move the close caption lines out of active video,
988 adjust the active video start point */
989 status = cx231xx_read_modify_write_i2c_dword(dev,
990 VID_BLK_I2C_ADDRESS,
991 VERT_TIM_CTRL,
992 FLD_VBLANK_CNT, 0x18);
993 status = cx231xx_read_modify_write_i2c_dword(dev,
994 VID_BLK_I2C_ADDRESS,
995 VERT_TIM_CTRL,
996 FLD_VACTIVE_CNT,
997 0x1E7000);
998 status = cx231xx_read_modify_write_i2c_dword(dev,
999 VID_BLK_I2C_ADDRESS,
1000 VERT_TIM_CTRL,
1001 FLD_V656BLANK_CNT,
1002 0x1C000000);
1003
1004 status = cx231xx_read_modify_write_i2c_dword(dev,
1005 VID_BLK_I2C_ADDRESS,
1006 HORIZ_TIM_CTRL,
1007 FLD_HBLANK_CNT,
1008 cx231xx_set_field
1009 (FLD_HBLANK_CNT, 0x79));
1010
1011 } else if (dev->norm & V4L2_STD_SECAM) {
1012 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1013 status = cx231xx_read_modify_write_i2c_dword(dev,
1014 VID_BLK_I2C_ADDRESS,
1015 VERT_TIM_CTRL,
1016 FLD_VBLANK_CNT, 0x20);
1017 status = cx231xx_read_modify_write_i2c_dword(dev,
1018 VID_BLK_I2C_ADDRESS,
1019 VERT_TIM_CTRL,
1020 FLD_VACTIVE_CNT,
1021 cx231xx_set_field
1022 (FLD_VACTIVE_CNT,
1023 0x244));
1024 status = cx231xx_read_modify_write_i2c_dword(dev,
1025 VID_BLK_I2C_ADDRESS,
1026 VERT_TIM_CTRL,
1027 FLD_V656BLANK_CNT,
1028 cx231xx_set_field
1029 (FLD_V656BLANK_CNT,
1030 0x24));
1031 /* Adjust the active video horizontal start point */
1032 status = cx231xx_read_modify_write_i2c_dword(dev,
1033 VID_BLK_I2C_ADDRESS,
1034 HORIZ_TIM_CTRL,
1035 FLD_HBLANK_CNT,
1036 cx231xx_set_field
1037 (FLD_HBLANK_CNT, 0x85));
1038 } else {
1039 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1040 status = cx231xx_read_modify_write_i2c_dword(dev,
1041 VID_BLK_I2C_ADDRESS,
1042 VERT_TIM_CTRL,
1043 FLD_VBLANK_CNT, 0x20);
1044 status = cx231xx_read_modify_write_i2c_dword(dev,
1045 VID_BLK_I2C_ADDRESS,
1046 VERT_TIM_CTRL,
1047 FLD_VACTIVE_CNT,
1048 cx231xx_set_field
1049 (FLD_VACTIVE_CNT,
1050 0x244));
1051 status = cx231xx_read_modify_write_i2c_dword(dev,
1052 VID_BLK_I2C_ADDRESS,
1053 VERT_TIM_CTRL,
1054 FLD_V656BLANK_CNT,
1055 cx231xx_set_field
1056 (FLD_V656BLANK_CNT,
1057 0x24));
1058 /* Adjust the active video horizontal start point */
1059 status = cx231xx_read_modify_write_i2c_dword(dev,
1060 VID_BLK_I2C_ADDRESS,
1061 HORIZ_TIM_CTRL,
1062 FLD_HBLANK_CNT,
1063 cx231xx_set_field
1064 (FLD_HBLANK_CNT, 0x85));
1065
1066 }
1067
1068 return status;
1069 }
1070
1071 int cx231xx_unmute_audio(struct cx231xx *dev)
1072 {
1073 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1074 }
1075 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1076
1077 int stopAudioFirmware(struct cx231xx *dev)
1078 {
1079 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1080 }
1081
1082 int restartAudioFirmware(struct cx231xx *dev)
1083 {
1084 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1085 }
1086
1087 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1088 {
1089 int status = 0;
1090 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1091
1092 switch (INPUT(input)->amux) {
1093 case CX231XX_AMUX_VIDEO:
1094 ainput = AUDIO_INPUT_TUNER_TV;
1095 break;
1096 case CX231XX_AMUX_LINE_IN:
1097 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1098 ainput = AUDIO_INPUT_LINE;
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 status = cx231xx_set_audio_decoder_input(dev, ainput);
1105
1106 return status;
1107 }
1108
1109 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1110 enum AUDIO_INPUT audio_input)
1111 {
1112 u32 dwval;
1113 int status;
1114 u8 gen_ctrl;
1115 u32 value = 0;
1116
1117 /* Put it in soft reset */
1118 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1119 gen_ctrl |= 1;
1120 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1121
1122 switch (audio_input) {
1123 case AUDIO_INPUT_LINE:
1124 /* setup AUD_IO control from Merlin paralle output */
1125 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1126 AUD_CHAN_SRC_PARALLEL);
1127 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1128
1129 /* setup input to Merlin, SRC2 connect to AC97
1130 bypass upsample-by-2, slave mode, sony mode, left justify
1131 adr 091c, dat 01000000 */
1132 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1133
1134 status = vid_blk_write_word(dev, AC97_CTL,
1135 (dwval | FLD_AC97_UP2X_BYPASS));
1136
1137 /* select the parallel1 and SRC3 */
1138 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1139 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1140 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1141 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1142
1143 /* unmute all, AC97 in, independence mode
1144 adr 08d0, data 0x00063073 */
1145 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1146 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1147
1148 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1149 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1150 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1151 (dwval | FLD_PATH1_AVC_THRESHOLD));
1152
1153 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1154 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1155 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1156 (dwval | FLD_PATH1_SC_THRESHOLD));
1157 break;
1158
1159 case AUDIO_INPUT_TUNER_TV:
1160 default:
1161 status = stopAudioFirmware(dev);
1162 /* Setup SRC sources and clocks */
1163 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1164 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1165 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1166 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1167 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1168 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1169 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1170 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1171 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1172 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1173 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1174 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1175 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1176 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1177
1178 /* Setup the AUD_IO control */
1179 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1180 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1181 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1182 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1183 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1184 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1185
1186 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1187
1188 /* setAudioStandard(_audio_standard); */
1189 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1190
1191 status = restartAudioFirmware(dev);
1192
1193 switch (dev->board.tuner_type) {
1194 case TUNER_XC5000:
1195 /* SIF passthrough at 28.6363 MHz sample rate */
1196 status = cx231xx_read_modify_write_i2c_dword(dev,
1197 VID_BLK_I2C_ADDRESS,
1198 CHIP_CTRL,
1199 FLD_SIF_EN,
1200 cx231xx_set_field(FLD_SIF_EN, 1));
1201 break;
1202 case TUNER_NXP_TDA18271:
1203 /* Normal mode: SIF passthrough at 14.32 MHz */
1204 status = cx231xx_read_modify_write_i2c_dword(dev,
1205 VID_BLK_I2C_ADDRESS,
1206 CHIP_CTRL,
1207 FLD_SIF_EN,
1208 cx231xx_set_field(FLD_SIF_EN, 0));
1209 break;
1210 default:
1211 /* This is just a casual suggestion to people adding
1212 new boards in case they use a tuner type we don't
1213 currently know about */
1214 printk(KERN_INFO "Unknown tuner type configuring SIF");
1215 break;
1216 }
1217 break;
1218
1219 case AUDIO_INPUT_TUNER_FM:
1220 /* use SIF for FM radio
1221 setupFM();
1222 setAudioStandard(_audio_standard);
1223 */
1224 break;
1225
1226 case AUDIO_INPUT_MUTE:
1227 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1228 break;
1229 }
1230
1231 /* Take it out of soft reset */
1232 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1233 gen_ctrl &= ~1;
1234 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1235
1236 return status;
1237 }
1238
1239 /******************************************************************************
1240 * C H I P Specific C O N T R O L functions *
1241 ******************************************************************************/
1242 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1243 {
1244 u32 value;
1245 int status = 0;
1246
1247 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1248 value |= (~dev->board.ctl_pin_status_mask);
1249 status = vid_blk_write_word(dev, PIN_CTRL, value);
1250
1251 return status;
1252 }
1253
1254 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1255 u8 analog_or_digital)
1256 {
1257 int status = 0;
1258
1259 /* first set the direction to output */
1260 status = cx231xx_set_gpio_direction(dev,
1261 dev->board.
1262 agc_analog_digital_select_gpio, 1);
1263
1264 /* 0 - demod ; 1 - Analog mode */
1265 status = cx231xx_set_gpio_value(dev,
1266 dev->board.agc_analog_digital_select_gpio,
1267 analog_or_digital);
1268
1269 return status;
1270 }
1271
1272 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1273 {
1274 u8 value[4] = { 0, 0, 0, 0 };
1275 int status = 0;
1276 bool current_is_port_3;
1277
1278 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1279 PWR_CTL_EN, value, 4);
1280 if (status < 0)
1281 return status;
1282
1283 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1284
1285 /* Just return, if already using the right port */
1286 if (current_is_port_3 == is_port_3)
1287 return 0;
1288
1289 if (is_port_3)
1290 value[0] |= I2C_DEMOD_EN;
1291 else
1292 value[0] &= ~I2C_DEMOD_EN;
1293
1294 cx231xx_info("Changing the i2c master port to %d\n",
1295 is_port_3 ? 3 : 1);
1296
1297 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1298 PWR_CTL_EN, value, 4);
1299
1300 return status;
1301
1302 }
1303 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1304
1305 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1306 {
1307 /*
1308 u8 status = 0;
1309 u32 value = 0;
1310
1311 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1312 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1313 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1314
1315 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1316 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1317 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1318 */
1319 }
1320
1321 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1322 {
1323 u8 status = 0;
1324 u32 value = 0;
1325 u16 i = 0;
1326
1327 value = 0x45005390;
1328 status = vid_blk_write_word(dev, 0x104, value);
1329
1330 for (i = 0x100; i < 0x140; i++) {
1331 status = vid_blk_read_word(dev, i, &value);
1332 cx231xx_info("reg0x%x=0x%x\n", i, value);
1333 i = i+3;
1334 }
1335
1336 for (i = 0x300; i < 0x400; i++) {
1337 status = vid_blk_read_word(dev, i, &value);
1338 cx231xx_info("reg0x%x=0x%x\n", i, value);
1339 i = i+3;
1340 }
1341
1342 for (i = 0x400; i < 0x440; i++) {
1343 status = vid_blk_read_word(dev, i, &value);
1344 cx231xx_info("reg0x%x=0x%x\n", i, value);
1345 i = i+3;
1346 }
1347
1348 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1349 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1350 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1351 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1352 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1353 }
1354
1355 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1356 {
1357 u8 value[4] = { 0, 0, 0, 0 };
1358 int status = 0;
1359 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1360
1361 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1362 value, 4);
1363 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1364 value[1], value[2], value[3]);
1365 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1366 value, 4);
1367 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1368 value[1], value[2], value[3]);
1369 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1370 value, 4);
1371 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1372 value[1], value[2], value[3]);
1373 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1374 value, 4);
1375 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1376 value[1], value[2], value[3]);
1377
1378 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1379 value, 4);
1380 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1381 value[1], value[2], value[3]);
1382 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1383 value, 4);
1384 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1385 value[1], value[2], value[3]);
1386 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1387 value, 4);
1388 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1389 value[1], value[2], value[3]);
1390 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1391 value, 4);
1392 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1393 value[1], value[2], value[3]);
1394
1395 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1396 value, 4);
1397 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1398 value[1], value[2], value[3]);
1399 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1400 value, 4);
1401 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1402 value[1], value[2], value[3]);
1403 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1404 value, 4);
1405 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1406 value[1], value[2], value[3]);
1407 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1408 value, 4);
1409 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1410 value[1], value[2], value[3]);
1411
1412 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1413 value, 4);
1414 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1415 value[1], value[2], value[3]);
1416 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1417 value, 4);
1418 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1419 value[1], value[2], value[3]);
1420 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1421 value, 4);
1422 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1423 value[1], value[2], value[3]);
1424 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1425 value, 4);
1426 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1427 value[1], value[2], value[3]);
1428
1429 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1430 value, 4);
1431 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1432 value[1], value[2], value[3]);
1433 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1434 value, 4);
1435 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1436 value[1], value[2], value[3]);
1437
1438
1439 }
1440
1441 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1442
1443 {
1444 u8 status = 0;
1445 u8 value = 0;
1446
1447
1448
1449 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1450 value = (value & 0xFE)|0x01;
1451 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1452
1453 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1454 value = (value & 0xFE)|0x00;
1455 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1456
1457
1458 /*
1459 config colibri to lo-if mode
1460
1461 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1462 the diff IF input by half,
1463
1464 for low-if agc defect
1465 */
1466
1467 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1468 value = (value & 0xFC)|0x00;
1469 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1470
1471 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1472 value = (value & 0xF9)|0x02;
1473 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1474
1475 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1476 value = (value & 0xFB)|0x04;
1477 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1478
1479 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1480 value = (value & 0xFC)|0x03;
1481 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1482
1483 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1484 value = (value & 0xFB)|0x04;
1485 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1486
1487 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1488 value = (value & 0xF8)|0x06;
1489 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1490
1491 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1492 value = (value & 0x8F)|0x40;
1493 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1494
1495 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1496 value = (value & 0xDF)|0x20;
1497 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1498 }
1499
1500 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1501 u8 spectral_invert, u32 mode)
1502 {
1503 u32 colibri_carrier_offset = 0;
1504 u8 status = 0;
1505 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1506 u32 standard = 0;
1507 u8 value[4] = { 0, 0, 0, 0 };
1508
1509 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1510 value[0] = (u8) 0x6F;
1511 value[1] = (u8) 0x6F;
1512 value[2] = (u8) 0x6F;
1513 value[3] = (u8) 0x6F;
1514 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1515 PWR_CTL_EN, value, 4);
1516
1517 /*Set colibri for low IF*/
1518 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1519
1520 /* Set C2HH for low IF operation.*/
1521 standard = dev->norm;
1522 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1523 func_mode, standard);
1524
1525 /* Get colibri offsets.*/
1526 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1527 standard);
1528
1529 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1530 colibri_carrier_offset, standard);
1531
1532 /* Set the band Pass filter for DIF*/
1533 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1534 spectral_invert, mode);
1535 }
1536
1537 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1538 {
1539 u32 colibri_carrier_offset = 0;
1540
1541 if (mode == TUNER_MODE_FM_RADIO) {
1542 colibri_carrier_offset = 1100000;
1543 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
1544 colibri_carrier_offset = 4832000; /*4.83MHz */
1545 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1546 colibri_carrier_offset = 2700000; /*2.70MHz */
1547 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1548 | V4L2_STD_SECAM)) {
1549 colibri_carrier_offset = 2100000; /*2.10MHz */
1550 }
1551
1552 return colibri_carrier_offset;
1553 }
1554
1555 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1556 u8 spectral_invert, u32 mode)
1557 {
1558 unsigned long pll_freq_word;
1559 int status = 0;
1560 u32 dif_misc_ctrl_value = 0;
1561 u64 pll_freq_u64 = 0;
1562 u32 i = 0;
1563
1564 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1565 if_freq, spectral_invert, mode);
1566
1567
1568 if (mode == TUNER_MODE_FM_RADIO) {
1569 pll_freq_word = 0x905A1CAC;
1570 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1571
1572 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1573 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1574 pll_freq_word = if_freq;
1575 pll_freq_u64 = (u64)pll_freq_word << 28L;
1576 do_div(pll_freq_u64, 50000000);
1577 pll_freq_word = (u32)pll_freq_u64;
1578 /*pll_freq_word = 0x3463497;*/
1579 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1580
1581 if (spectral_invert) {
1582 if_freq -= 400000;
1583 /* Enable Spectral Invert*/
1584 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1585 &dif_misc_ctrl_value);
1586 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1587 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1588 dif_misc_ctrl_value);
1589 } else {
1590 if_freq += 400000;
1591 /* Disable Spectral Invert*/
1592 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1593 &dif_misc_ctrl_value);
1594 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1595 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1596 dif_misc_ctrl_value);
1597 }
1598
1599 if_freq = (if_freq/100000)*100000;
1600
1601 if (if_freq < 3000000)
1602 if_freq = 3000000;
1603
1604 if (if_freq > 16000000)
1605 if_freq = 16000000;
1606 }
1607
1608 cx231xx_info("Enter IF=%zd\n",
1609 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1610 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1611 if (Dif_set_array[i].if_freq == if_freq) {
1612 status = vid_blk_write_word(dev,
1613 Dif_set_array[i].register_address, Dif_set_array[i].value);
1614 }
1615 }
1616 }
1617
1618 /******************************************************************************
1619 * D I F - B L O C K C O N T R O L functions *
1620 ******************************************************************************/
1621 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1622 u32 function_mode, u32 standard)
1623 {
1624 int status = 0;
1625
1626
1627 if (mode == V4L2_TUNER_RADIO) {
1628 /* C2HH */
1629 /* lo if big signal */
1630 status = cx231xx_reg_mask_write(dev,
1631 VID_BLK_I2C_ADDRESS, 32,
1632 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1633 /* FUNC_MODE = DIF */
1634 status = cx231xx_reg_mask_write(dev,
1635 VID_BLK_I2C_ADDRESS, 32,
1636 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1637 /* IF_MODE */
1638 status = cx231xx_reg_mask_write(dev,
1639 VID_BLK_I2C_ADDRESS, 32,
1640 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1641 /* no inv */
1642 status = cx231xx_reg_mask_write(dev,
1643 VID_BLK_I2C_ADDRESS, 32,
1644 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1645 } else if (standard != DIF_USE_BASEBAND) {
1646 if (standard & V4L2_STD_MN) {
1647 /* lo if big signal */
1648 status = cx231xx_reg_mask_write(dev,
1649 VID_BLK_I2C_ADDRESS, 32,
1650 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1651 /* FUNC_MODE = DIF */
1652 status = cx231xx_reg_mask_write(dev,
1653 VID_BLK_I2C_ADDRESS, 32,
1654 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1655 function_mode);
1656 /* IF_MODE */
1657 status = cx231xx_reg_mask_write(dev,
1658 VID_BLK_I2C_ADDRESS, 32,
1659 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1660 /* no inv */
1661 status = cx231xx_reg_mask_write(dev,
1662 VID_BLK_I2C_ADDRESS, 32,
1663 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1664 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1665 status = cx231xx_reg_mask_write(dev,
1666 VID_BLK_I2C_ADDRESS, 32,
1667 AUD_IO_CTRL, 0, 31, 0x00000003);
1668 } else if ((standard == V4L2_STD_PAL_I) |
1669 (standard & V4L2_STD_PAL_D) |
1670 (standard & V4L2_STD_SECAM)) {
1671 /* C2HH setup */
1672 /* lo if big signal */
1673 status = cx231xx_reg_mask_write(dev,
1674 VID_BLK_I2C_ADDRESS, 32,
1675 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1676 /* FUNC_MODE = DIF */
1677 status = cx231xx_reg_mask_write(dev,
1678 VID_BLK_I2C_ADDRESS, 32,
1679 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1680 function_mode);
1681 /* IF_MODE */
1682 status = cx231xx_reg_mask_write(dev,
1683 VID_BLK_I2C_ADDRESS, 32,
1684 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1685 /* no inv */
1686 status = cx231xx_reg_mask_write(dev,
1687 VID_BLK_I2C_ADDRESS, 32,
1688 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1689 } else {
1690 /* default PAL BG */
1691 /* C2HH setup */
1692 /* lo if big signal */
1693 status = cx231xx_reg_mask_write(dev,
1694 VID_BLK_I2C_ADDRESS, 32,
1695 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1696 /* FUNC_MODE = DIF */
1697 status = cx231xx_reg_mask_write(dev,
1698 VID_BLK_I2C_ADDRESS, 32,
1699 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1700 function_mode);
1701 /* IF_MODE */
1702 status = cx231xx_reg_mask_write(dev,
1703 VID_BLK_I2C_ADDRESS, 32,
1704 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1705 /* no inv */
1706 status = cx231xx_reg_mask_write(dev,
1707 VID_BLK_I2C_ADDRESS, 32,
1708 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1709 }
1710 }
1711
1712 return status;
1713 }
1714
1715 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1716 {
1717 int status = 0;
1718 u32 dif_misc_ctrl_value = 0;
1719 u32 func_mode = 0;
1720
1721 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1722
1723 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1724 if (standard != DIF_USE_BASEBAND)
1725 dev->norm = standard;
1726
1727 switch (dev->model) {
1728 case CX231XX_BOARD_CNXT_CARRAERA:
1729 case CX231XX_BOARD_CNXT_RDE_250:
1730 case CX231XX_BOARD_CNXT_SHELBY:
1731 case CX231XX_BOARD_CNXT_RDU_250:
1732 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1733 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1734 func_mode = 0x03;
1735 break;
1736 case CX231XX_BOARD_CNXT_RDE_253S:
1737 case CX231XX_BOARD_CNXT_RDU_253S:
1738 func_mode = 0x01;
1739 break;
1740 default:
1741 func_mode = 0x01;
1742 }
1743
1744 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1745 func_mode, standard);
1746
1747 if (standard == DIF_USE_BASEBAND) { /* base band */
1748 /* There is a different SRC_PHASE_INC value
1749 for baseband vs. DIF */
1750 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1751 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1752 &dif_misc_ctrl_value);
1753 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1754 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1755 dif_misc_ctrl_value);
1756 } else if (standard & V4L2_STD_PAL_D) {
1757 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1758 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1760 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1762 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1764 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1766 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1772 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1774 DIF_AGC_IF_INT_CURRENT, 0, 31,
1775 0x26001700);
1776 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1777 DIF_AGC_RF_CURRENT, 0, 31,
1778 0x00002660);
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 DIF_VIDEO_AGC_CTRL, 0, 31,
1781 0x72500800);
1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1783 DIF_VID_AUD_OVERRIDE, 0, 31,
1784 0x27000100);
1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1786 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1788 DIF_COMP_FLT_CTRL, 0, 31,
1789 0x00000000);
1790 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1791 DIF_SRC_PHASE_INC, 0, 31,
1792 0x1befbf06);
1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1794 DIF_SRC_GAIN_CONTROL, 0, 31,
1795 0x000035e8);
1796 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1797 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1798 /* Save the Spec Inversion value */
1799 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1800 dif_misc_ctrl_value |= 0x3a023F11;
1801 } else if (standard & V4L2_STD_PAL_I) {
1802 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1803 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1807 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1809 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1811 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1817 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819 DIF_AGC_IF_INT_CURRENT, 0, 31,
1820 0x26001700);
1821 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1822 DIF_AGC_RF_CURRENT, 0, 31,
1823 0x00002660);
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 DIF_VIDEO_AGC_CTRL, 0, 31,
1826 0x72500800);
1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1828 DIF_VID_AUD_OVERRIDE, 0, 31,
1829 0x27000100);
1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1831 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1833 DIF_COMP_FLT_CTRL, 0, 31,
1834 0x00000000);
1835 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1836 DIF_SRC_PHASE_INC, 0, 31,
1837 0x1befbf06);
1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1839 DIF_SRC_GAIN_CONTROL, 0, 31,
1840 0x000035e8);
1841 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1842 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1843 /* Save the Spec Inversion value */
1844 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1845 dif_misc_ctrl_value |= 0x3a033F11;
1846 } else if (standard & V4L2_STD_PAL_M) {
1847 /* improved Low Frequency Phase Noise */
1848 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1849 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1850 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1851 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1852 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1853 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1854 0x26001700);
1855 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1856 0x00002660);
1857 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1858 0x72500800);
1859 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1860 0x27000100);
1861 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1862 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1863 0x009f50c1);
1864 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1865 0x1befbf06);
1866 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1867 0x000035e8);
1868 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1869 0x00000000);
1870 /* Save the Spec Inversion value */
1871 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1872 dif_misc_ctrl_value |= 0x3A0A3F10;
1873 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1874 /* improved Low Frequency Phase Noise */
1875 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1876 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1877 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1878 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1879 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1880 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1881 0x26001700);
1882 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1883 0x00002660);
1884 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1885 0x72500800);
1886 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1887 0x27000100);
1888 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1889 0x012c405d);
1890 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1891 0x009f50c1);
1892 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1893 0x1befbf06);
1894 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1895 0x000035e8);
1896 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1897 0x00000000);
1898 /* Save the Spec Inversion value */
1899 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1900 dif_misc_ctrl_value = 0x3A093F10;
1901 } else if (standard &
1902 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1903 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1904
1905 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1906 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1908 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1910 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1912 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1914 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1916 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1920 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1922 DIF_AGC_IF_INT_CURRENT, 0, 31,
1923 0x26001700);
1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1925 DIF_AGC_RF_CURRENT, 0, 31,
1926 0x00002660);
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 DIF_VID_AUD_OVERRIDE, 0, 31,
1929 0x27000100);
1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1931 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1933 DIF_COMP_FLT_CTRL, 0, 31,
1934 0x00000000);
1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936 DIF_SRC_PHASE_INC, 0, 31,
1937 0x1befbf06);
1938 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1939 DIF_SRC_GAIN_CONTROL, 0, 31,
1940 0x000035e8);
1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1942 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944 DIF_VIDEO_AGC_CTRL, 0, 31,
1945 0xf4000000);
1946
1947 /* Save the Spec Inversion value */
1948 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1949 dif_misc_ctrl_value |= 0x3a023F11;
1950 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1951 /* Is it SECAM_L1? */
1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1953 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1957 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1959 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1963 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1967 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1969 DIF_AGC_IF_INT_CURRENT, 0, 31,
1970 0x26001700);
1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1972 DIF_AGC_RF_CURRENT, 0, 31,
1973 0x00002660);
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 DIF_VID_AUD_OVERRIDE, 0, 31,
1976 0x27000100);
1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1978 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1980 DIF_COMP_FLT_CTRL, 0, 31,
1981 0x00000000);
1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983 DIF_SRC_PHASE_INC, 0, 31,
1984 0x1befbf06);
1985 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1986 DIF_SRC_GAIN_CONTROL, 0, 31,
1987 0x000035e8);
1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1989 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991 DIF_VIDEO_AGC_CTRL, 0, 31,
1992 0xf2560000);
1993
1994 /* Save the Spec Inversion value */
1995 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1996 dif_misc_ctrl_value |= 0x3a023F11;
1997
1998 } else if (standard & V4L2_STD_NTSC_M) {
1999 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2000 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2001
2002 /* For NTSC the centre frequency of video coming out of
2003 sidewinder is around 7.1MHz or 3.6MHz depending on the
2004 spectral inversion. so for a non spectrally inverted channel
2005 the pll freq word is 0x03420c49
2006 */
2007
2008 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2009 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2010 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2011 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2012 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2013 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2014 0x26001700);
2015 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2016 0x00002660);
2017 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2018 0x04000800);
2019 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2020 0x27000100);
2021 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2022
2023 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2024 0x009f50c1);
2025 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2026 0x1befbf06);
2027 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2028 0x000035e8);
2029
2030 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2031 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2032 0xC2262600);
2033 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2034
2035 /* Save the Spec Inversion value */
2036 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2037 dif_misc_ctrl_value |= 0x3a003F10;
2038 } else {
2039 /* default PAL BG */
2040 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2041 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2043 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2045 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2047 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2049 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2051 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2055 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2057 DIF_AGC_IF_INT_CURRENT, 0, 31,
2058 0x26001700);
2059 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2060 DIF_AGC_RF_CURRENT, 0, 31,
2061 0x00002660);
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 DIF_VIDEO_AGC_CTRL, 0, 31,
2064 0x72500800);
2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2066 DIF_VID_AUD_OVERRIDE, 0, 31,
2067 0x27000100);
2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2069 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2071 DIF_COMP_FLT_CTRL, 0, 31,
2072 0x00A653A8);
2073 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2074 DIF_SRC_PHASE_INC, 0, 31,
2075 0x1befbf06);
2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2077 DIF_SRC_GAIN_CONTROL, 0, 31,
2078 0x000035e8);
2079 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2080 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2081 /* Save the Spec Inversion value */
2082 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2083 dif_misc_ctrl_value |= 0x3a013F11;
2084 }
2085
2086 /* The AGC values should be the same for all standards,
2087 AUD_SRC_SEL[19] should always be disabled */
2088 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2089
2090 /* It is still possible to get Set Standard calls even when we
2091 are in FM mode.
2092 This is done to override the value for FM. */
2093 if (dev->active_mode == V4L2_TUNER_RADIO)
2094 dif_misc_ctrl_value = 0x7a080000;
2095
2096 /* Write the calculated value for misc ontrol register */
2097 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2098
2099 return status;
2100 }
2101
2102 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2103 {
2104 int status = 0;
2105 u32 dwval;
2106
2107 /* Set the RF and IF k_agc values to 3 */
2108 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2109 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2110 dwval |= 0x33000000;
2111
2112 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2113
2114 return status;
2115 }
2116
2117 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2118 {
2119 int status = 0;
2120 u32 dwval;
2121 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2122 dev->tuner_type);
2123 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2124 * SECAM L/B/D standards */
2125 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2126 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2127
2128 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2129 V4L2_STD_SECAM_D)) {
2130 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2131 dwval &= ~FLD_DIF_IF_REF;
2132 dwval |= 0x88000300;
2133 } else
2134 dwval |= 0x88000000;
2135 } else {
2136 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2137 dwval &= ~FLD_DIF_IF_REF;
2138 dwval |= 0xCC000300;
2139 } else
2140 dwval |= 0x44000000;
2141 }
2142
2143 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2144
2145 return status;
2146 }
2147
2148 /******************************************************************************
2149 * I 2 S - B L O C K C O N T R O L functions *
2150 ******************************************************************************/
2151 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2152 {
2153 int status = 0;
2154 u32 value;
2155
2156 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2157 CH_PWR_CTRL1, 1, &value, 1);
2158 /* enables clock to delta-sigma and decimation filter */
2159 value |= 0x80;
2160 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2161 CH_PWR_CTRL1, 1, value, 1);
2162 /* power up all channel */
2163 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2164 CH_PWR_CTRL2, 1, 0x00, 1);
2165
2166 return status;
2167 }
2168
2169 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2170 enum AV_MODE avmode)
2171 {
2172 int status = 0;
2173 u32 value = 0;
2174
2175 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2176 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2177 CH_PWR_CTRL2, 1, &value, 1);
2178 value |= 0xfe;
2179 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2180 CH_PWR_CTRL2, 1, value, 1);
2181 } else {
2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2183 CH_PWR_CTRL2, 1, 0x00, 1);
2184 }
2185
2186 return status;
2187 }
2188
2189 /* set i2s_blk for audio input types */
2190 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2191 {
2192 int status = 0;
2193
2194 switch (audio_input) {
2195 case CX231XX_AMUX_LINE_IN:
2196 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2197 CH_PWR_CTRL2, 1, 0x00, 1);
2198 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2199 CH_PWR_CTRL1, 1, 0x80, 1);
2200 break;
2201 case CX231XX_AMUX_VIDEO:
2202 default:
2203 break;
2204 }
2205
2206 dev->ctl_ainput = audio_input;
2207
2208 return status;
2209 }
2210
2211 /******************************************************************************
2212 * P O W E R C O N T R O L functions *
2213 ******************************************************************************/
2214 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2215 {
2216 u8 value[4] = { 0, 0, 0, 0 };
2217 u32 tmp = 0;
2218 int status = 0;
2219
2220 if (dev->power_mode != mode)
2221 dev->power_mode = mode;
2222 else {
2223 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2224 mode);
2225 return 0;
2226 }
2227
2228 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2229 4);
2230 if (status < 0)
2231 return status;
2232
2233 tmp = *((u32 *) value);
2234
2235 switch (mode) {
2236 case POLARIS_AVMODE_ENXTERNAL_AV:
2237
2238 tmp &= (~PWR_MODE_MASK);
2239
2240 tmp |= PWR_AV_EN;
2241 value[0] = (u8) tmp;
2242 value[1] = (u8) (tmp >> 8);
2243 value[2] = (u8) (tmp >> 16);
2244 value[3] = (u8) (tmp >> 24);
2245 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2246 PWR_CTL_EN, value, 4);
2247 msleep(PWR_SLEEP_INTERVAL);
2248
2249 tmp |= PWR_ISO_EN;
2250 value[0] = (u8) tmp;
2251 value[1] = (u8) (tmp >> 8);
2252 value[2] = (u8) (tmp >> 16);
2253 value[3] = (u8) (tmp >> 24);
2254 status =
2255 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2256 value, 4);
2257 msleep(PWR_SLEEP_INTERVAL);
2258
2259 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2260 value[0] = (u8) tmp;
2261 value[1] = (u8) (tmp >> 8);
2262 value[2] = (u8) (tmp >> 16);
2263 value[3] = (u8) (tmp >> 24);
2264 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2265 PWR_CTL_EN, value, 4);
2266
2267 /* reset state of xceive tuner */
2268 dev->xc_fw_load_done = 0;
2269 break;
2270
2271 case POLARIS_AVMODE_ANALOGT_TV:
2272
2273 tmp |= PWR_DEMOD_EN;
2274 tmp |= (I2C_DEMOD_EN);
2275 value[0] = (u8) tmp;
2276 value[1] = (u8) (tmp >> 8);
2277 value[2] = (u8) (tmp >> 16);
2278 value[3] = (u8) (tmp >> 24);
2279 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2280 PWR_CTL_EN, value, 4);
2281 msleep(PWR_SLEEP_INTERVAL);
2282
2283 if (!(tmp & PWR_TUNER_EN)) {
2284 tmp |= (PWR_TUNER_EN);
2285 value[0] = (u8) tmp;
2286 value[1] = (u8) (tmp >> 8);
2287 value[2] = (u8) (tmp >> 16);
2288 value[3] = (u8) (tmp >> 24);
2289 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2290 PWR_CTL_EN, value, 4);
2291 msleep(PWR_SLEEP_INTERVAL);
2292 }
2293
2294 if (!(tmp & PWR_AV_EN)) {
2295 tmp |= PWR_AV_EN;
2296 value[0] = (u8) tmp;
2297 value[1] = (u8) (tmp >> 8);
2298 value[2] = (u8) (tmp >> 16);
2299 value[3] = (u8) (tmp >> 24);
2300 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2301 PWR_CTL_EN, value, 4);
2302 msleep(PWR_SLEEP_INTERVAL);
2303 }
2304 if (!(tmp & PWR_ISO_EN)) {
2305 tmp |= PWR_ISO_EN;
2306 value[0] = (u8) tmp;
2307 value[1] = (u8) (tmp >> 8);
2308 value[2] = (u8) (tmp >> 16);
2309 value[3] = (u8) (tmp >> 24);
2310 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2311 PWR_CTL_EN, value, 4);
2312 msleep(PWR_SLEEP_INTERVAL);
2313 }
2314
2315 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2316 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2317 value[0] = (u8) tmp;
2318 value[1] = (u8) (tmp >> 8);
2319 value[2] = (u8) (tmp >> 16);
2320 value[3] = (u8) (tmp >> 24);
2321 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2322 PWR_CTL_EN, value, 4);
2323 msleep(PWR_SLEEP_INTERVAL);
2324 }
2325
2326 if (dev->board.tuner_type != TUNER_ABSENT) {
2327 /* Enable tuner */
2328 cx231xx_enable_i2c_port_3(dev, true);
2329
2330 /* reset the Tuner */
2331 if (dev->board.tuner_gpio)
2332 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2333
2334 if (dev->cx231xx_reset_analog_tuner)
2335 dev->cx231xx_reset_analog_tuner(dev);
2336 }
2337
2338 break;
2339
2340 case POLARIS_AVMODE_DIGITAL:
2341 if (!(tmp & PWR_TUNER_EN)) {
2342 tmp |= (PWR_TUNER_EN);
2343 value[0] = (u8) tmp;
2344 value[1] = (u8) (tmp >> 8);
2345 value[2] = (u8) (tmp >> 16);
2346 value[3] = (u8) (tmp >> 24);
2347 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2348 PWR_CTL_EN, value, 4);
2349 msleep(PWR_SLEEP_INTERVAL);
2350 }
2351 if (!(tmp & PWR_AV_EN)) {
2352 tmp |= PWR_AV_EN;
2353 value[0] = (u8) tmp;
2354 value[1] = (u8) (tmp >> 8);
2355 value[2] = (u8) (tmp >> 16);
2356 value[3] = (u8) (tmp >> 24);
2357 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2358 PWR_CTL_EN, value, 4);
2359 msleep(PWR_SLEEP_INTERVAL);
2360 }
2361 if (!(tmp & PWR_ISO_EN)) {
2362 tmp |= PWR_ISO_EN;
2363 value[0] = (u8) tmp;
2364 value[1] = (u8) (tmp >> 8);
2365 value[2] = (u8) (tmp >> 16);
2366 value[3] = (u8) (tmp >> 24);
2367 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2368 PWR_CTL_EN, value, 4);
2369 msleep(PWR_SLEEP_INTERVAL);
2370 }
2371
2372 tmp &= (~PWR_AV_MODE);
2373 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2374 value[0] = (u8) tmp;
2375 value[1] = (u8) (tmp >> 8);
2376 value[2] = (u8) (tmp >> 16);
2377 value[3] = (u8) (tmp >> 24);
2378 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2379 PWR_CTL_EN, value, 4);
2380 msleep(PWR_SLEEP_INTERVAL);
2381
2382 if (!(tmp & PWR_DEMOD_EN)) {
2383 tmp |= PWR_DEMOD_EN;
2384 value[0] = (u8) tmp;
2385 value[1] = (u8) (tmp >> 8);
2386 value[2] = (u8) (tmp >> 16);
2387 value[3] = (u8) (tmp >> 24);
2388 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2389 PWR_CTL_EN, value, 4);
2390 msleep(PWR_SLEEP_INTERVAL);
2391 }
2392
2393 if (dev->board.tuner_type != TUNER_ABSENT) {
2394 /*
2395 * Enable tuner
2396 * Hauppauge Exeter seems to need to do something different!
2397 */
2398 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)
2399 cx231xx_enable_i2c_port_3(dev, false);
2400 else
2401 cx231xx_enable_i2c_port_3(dev, true);
2402
2403 /* reset the Tuner */
2404 if (dev->board.tuner_gpio)
2405 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2406
2407 if (dev->cx231xx_reset_analog_tuner)
2408 dev->cx231xx_reset_analog_tuner(dev);
2409 }
2410 break;
2411
2412 default:
2413 break;
2414 }
2415
2416 msleep(PWR_SLEEP_INTERVAL);
2417
2418 /* For power saving, only enable Pwr_resetout_n
2419 when digital TV is selected. */
2420 if (mode == POLARIS_AVMODE_DIGITAL) {
2421 tmp |= PWR_RESETOUT_EN;
2422 value[0] = (u8) tmp;
2423 value[1] = (u8) (tmp >> 8);
2424 value[2] = (u8) (tmp >> 16);
2425 value[3] = (u8) (tmp >> 24);
2426 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2427 PWR_CTL_EN, value, 4);
2428 msleep(PWR_SLEEP_INTERVAL);
2429 }
2430
2431 /* update power control for afe */
2432 status = cx231xx_afe_update_power_control(dev, mode);
2433
2434 /* update power control for i2s_blk */
2435 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2436
2437 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2438 4);
2439
2440 return status;
2441 }
2442
2443 int cx231xx_power_suspend(struct cx231xx *dev)
2444 {
2445 u8 value[4] = { 0, 0, 0, 0 };
2446 u32 tmp = 0;
2447 int status = 0;
2448
2449 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2450 value, 4);
2451 if (status > 0)
2452 return status;
2453
2454 tmp = *((u32 *) value);
2455 tmp &= (~PWR_MODE_MASK);
2456
2457 value[0] = (u8) tmp;
2458 value[1] = (u8) (tmp >> 8);
2459 value[2] = (u8) (tmp >> 16);
2460 value[3] = (u8) (tmp >> 24);
2461 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2462 value, 4);
2463
2464 return status;
2465 }
2466
2467 /******************************************************************************
2468 * S T R E A M C O N T R O L functions *
2469 ******************************************************************************/
2470 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2471 {
2472 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2473 u32 tmp = 0;
2474 int status = 0;
2475
2476 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2477 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2478 value, 4);
2479 if (status < 0)
2480 return status;
2481
2482 tmp = *((u32 *) value);
2483 tmp |= ep_mask;
2484 value[0] = (u8) tmp;
2485 value[1] = (u8) (tmp >> 8);
2486 value[2] = (u8) (tmp >> 16);
2487 value[3] = (u8) (tmp >> 24);
2488
2489 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2490 value, 4);
2491
2492 return status;
2493 }
2494
2495 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2496 {
2497 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2498 u32 tmp = 0;
2499 int status = 0;
2500
2501 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2502 status =
2503 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2504 if (status < 0)
2505 return status;
2506
2507 tmp = *((u32 *) value);
2508 tmp &= (~ep_mask);
2509 value[0] = (u8) tmp;
2510 value[1] = (u8) (tmp >> 8);
2511 value[2] = (u8) (tmp >> 16);
2512 value[3] = (u8) (tmp >> 24);
2513
2514 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2515 value, 4);
2516
2517 return status;
2518 }
2519
2520 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2521 {
2522 int status = 0;
2523 u32 value = 0;
2524 u8 val[4] = { 0, 0, 0, 0 };
2525
2526 if (dev->udev->speed == USB_SPEED_HIGH) {
2527 switch (media_type) {
2528 case 81: /* audio */
2529 cx231xx_info("%s: Audio enter HANC\n", __func__);
2530 status =
2531 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2532 break;
2533
2534 case 2: /* vbi */
2535 cx231xx_info("%s: set vanc registers\n", __func__);
2536 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2537 break;
2538
2539 case 3: /* sliced cc */
2540 cx231xx_info("%s: set hanc registers\n", __func__);
2541 status =
2542 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2543 break;
2544
2545 case 0: /* video */
2546 cx231xx_info("%s: set video registers\n", __func__);
2547 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2548 break;
2549
2550 case 4: /* ts1 */
2551 cx231xx_info("%s: set ts1 registers", __func__);
2552
2553 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2554 cx231xx_info(" MPEG\n");
2555 value &= 0xFFFFFFFC;
2556 value |= 0x3;
2557
2558 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2559
2560 val[0] = 0x04;
2561 val[1] = 0xA3;
2562 val[2] = 0x3B;
2563 val[3] = 0x00;
2564 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2565 TS1_CFG_REG, val, 4);
2566
2567 val[0] = 0x00;
2568 val[1] = 0x08;
2569 val[2] = 0x00;
2570 val[3] = 0x08;
2571 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2572 TS1_LENGTH_REG, val, 4);
2573
2574 } else {
2575 cx231xx_info(" BDA\n");
2576 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2577 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2578 }
2579 break;
2580
2581 case 6: /* ts1 parallel mode */
2582 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2583 __func__);
2584 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2585 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2586 break;
2587 }
2588 } else {
2589 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2590 }
2591
2592 return status;
2593 }
2594
2595 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2596 {
2597 int rc = -1;
2598 u32 ep_mask = -1;
2599 struct pcb_config *pcb_config;
2600
2601 /* get EP for media type */
2602 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2603
2604 if (pcb_config->config_num == 1) {
2605 switch (media_type) {
2606 case 0: /* Video */
2607 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2608 break;
2609 case 1: /* Audio */
2610 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2611 break;
2612 case 2: /* Vbi */
2613 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2614 break;
2615 case 3: /* Sliced_cc */
2616 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2617 break;
2618 case 4: /* ts1 */
2619 case 6: /* ts1 parallel mode */
2620 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2621 break;
2622 case 5: /* ts2 */
2623 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2624 break;
2625 }
2626
2627 } else if (pcb_config->config_num > 1) {
2628 switch (media_type) {
2629 case 0: /* Video */
2630 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2631 break;
2632 case 1: /* Audio */
2633 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2634 break;
2635 case 2: /* Vbi */
2636 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2637 break;
2638 case 3: /* Sliced_cc */
2639 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2640 break;
2641 case 4: /* ts1 */
2642 case 6: /* ts1 parallel mode */
2643 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2644 break;
2645 case 5: /* ts2 */
2646 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2647 break;
2648 }
2649
2650 }
2651
2652 if (start) {
2653 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2654
2655 if (rc < 0)
2656 return rc;
2657
2658 /* enable video capture */
2659 if (ep_mask > 0)
2660 rc = cx231xx_start_stream(dev, ep_mask);
2661 } else {
2662 /* disable video capture */
2663 if (ep_mask > 0)
2664 rc = cx231xx_stop_stream(dev, ep_mask);
2665 }
2666
2667 if (dev->mode == CX231XX_ANALOG_MODE)
2668 ;/* do any in Analog mode */
2669 else
2670 ;/* do any in digital mode */
2671
2672 return rc;
2673 }
2674 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2675
2676 /*****************************************************************************
2677 * G P I O B I T control functions *
2678 ******************************************************************************/
2679 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2680 {
2681 int status = 0;
2682
2683 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2684
2685 return status;
2686 }
2687
2688 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2689 {
2690 int status = 0;
2691
2692 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2693
2694 return status;
2695 }
2696
2697 /*
2698 * cx231xx_set_gpio_direction
2699 * Sets the direction of the GPIO pin to input or output
2700 *
2701 * Parameters :
2702 * pin_number : The GPIO Pin number to program the direction for
2703 * from 0 to 31
2704 * pin_value : The Direction of the GPIO Pin under reference.
2705 * 0 = Input direction
2706 * 1 = Output direction
2707 */
2708 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2709 int pin_number, int pin_value)
2710 {
2711 int status = 0;
2712 u32 value = 0;
2713
2714 /* Check for valid pin_number - if 32 , bail out */
2715 if (pin_number >= 32)
2716 return -EINVAL;
2717
2718 /* input */
2719 if (pin_value == 0)
2720 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2721 else
2722 value = dev->gpio_dir | (1 << pin_number);
2723
2724 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2725
2726 /* cache the value for future */
2727 dev->gpio_dir = value;
2728
2729 return status;
2730 }
2731
2732 /*
2733 * cx231xx_set_gpio_value
2734 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2735 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2736 *
2737 * Parameters :
2738 * pin_number : The GPIO Pin number to program the direction for
2739 * pin_value : The value of the GPIO Pin under reference.
2740 * 0 = set it to 0
2741 * 1 = set it to 1
2742 */
2743 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2744 {
2745 int status = 0;
2746 u32 value = 0;
2747
2748 /* Check for valid pin_number - if 0xFF , bail out */
2749 if (pin_number >= 32)
2750 return -EINVAL;
2751
2752 /* first do a sanity check - if the Pin is not output, make it output */
2753 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2754 /* It was in input mode */
2755 value = dev->gpio_dir | (1 << pin_number);
2756 dev->gpio_dir = value;
2757 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2758 (u8 *) &dev->gpio_val);
2759 value = 0;
2760 }
2761
2762 if (pin_value == 0)
2763 value = dev->gpio_val & (~(1 << pin_number));
2764 else
2765 value = dev->gpio_val | (1 << pin_number);
2766
2767 /* store the value */
2768 dev->gpio_val = value;
2769
2770 /* toggle bit0 of GP_IO */
2771 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2772
2773 return status;
2774 }
2775
2776 /*****************************************************************************
2777 * G P I O I2C related functions *
2778 ******************************************************************************/
2779 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2780 {
2781 int status = 0;
2782
2783 /* set SCL to output 1 ; set SDA to output 1 */
2784 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2785 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2786 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2787 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2788
2789 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2790 if (status < 0)
2791 return -EINVAL;
2792
2793 /* set SCL to output 1; set SDA to output 0 */
2794 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2795 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2796
2797 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2798 if (status < 0)
2799 return -EINVAL;
2800
2801 /* set SCL to output 0; set SDA to output 0 */
2802 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2803 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2804
2805 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2806 if (status < 0)
2807 return -EINVAL;
2808
2809 return status;
2810 }
2811
2812 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2813 {
2814 int status = 0;
2815
2816 /* set SCL to output 0; set SDA to output 0 */
2817 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2818 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2819
2820 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2821 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2822
2823 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2824 if (status < 0)
2825 return -EINVAL;
2826
2827 /* set SCL to output 1; set SDA to output 0 */
2828 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2829 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2830
2831 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2832 if (status < 0)
2833 return -EINVAL;
2834
2835 /* set SCL to input ,release SCL cable control
2836 set SDA to input ,release SDA cable control */
2837 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2838 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2839
2840 status =
2841 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2842 if (status < 0)
2843 return -EINVAL;
2844
2845 return status;
2846 }
2847
2848 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2849 {
2850 int status = 0;
2851 u8 i;
2852
2853 /* set SCL to output ; set SDA to output */
2854 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2855 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2856
2857 for (i = 0; i < 8; i++) {
2858 if (((data << i) & 0x80) == 0) {
2859 /* set SCL to output 0; set SDA to output 0 */
2860 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2861 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2862 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2863 (u8 *)&dev->gpio_val);
2864
2865 /* set SCL to output 1; set SDA to output 0 */
2866 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2867 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2868 (u8 *)&dev->gpio_val);
2869
2870 /* set SCL to output 0; set SDA to output 0 */
2871 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2872 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2873 (u8 *)&dev->gpio_val);
2874 } else {
2875 /* set SCL to output 0; set SDA to output 1 */
2876 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2877 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2878 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2879 (u8 *)&dev->gpio_val);
2880
2881 /* set SCL to output 1; set SDA to output 1 */
2882 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2883 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2884 (u8 *)&dev->gpio_val);
2885
2886 /* set SCL to output 0; set SDA to output 1 */
2887 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2888 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2889 (u8 *)&dev->gpio_val);
2890 }
2891 }
2892 return status;
2893 }
2894
2895 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2896 {
2897 u8 value = 0;
2898 int status = 0;
2899 u32 gpio_logic_value = 0;
2900 u8 i;
2901
2902 /* read byte */
2903 for (i = 0; i < 8; i++) { /* send write I2c addr */
2904
2905 /* set SCL to output 0; set SDA to input */
2906 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2907 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2908 (u8 *)&dev->gpio_val);
2909
2910 /* set SCL to output 1; set SDA to input */
2911 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2912 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2913 (u8 *)&dev->gpio_val);
2914
2915 /* get SDA data bit */
2916 gpio_logic_value = dev->gpio_val;
2917 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2918 (u8 *)&dev->gpio_val);
2919 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2920 value |= (1 << (8 - i - 1));
2921
2922 dev->gpio_val = gpio_logic_value;
2923 }
2924
2925 /* set SCL to output 0,finish the read latest SCL signal.
2926 !!!set SDA to input, never to modify SDA direction at
2927 the same times */
2928 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2929 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2930
2931 /* store the value */
2932 *buf = value & 0xff;
2933
2934 return status;
2935 }
2936
2937 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2938 {
2939 int status = 0;
2940 u32 gpio_logic_value = 0;
2941 int nCnt = 10;
2942 int nInit = nCnt;
2943
2944 /* clock stretch; set SCL to input; set SDA to input;
2945 get SCL value till SCL = 1 */
2946 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2947 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2948
2949 gpio_logic_value = dev->gpio_val;
2950 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2951
2952 do {
2953 msleep(2);
2954 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2955 (u8 *)&dev->gpio_val);
2956 nCnt--;
2957 } while (((dev->gpio_val &
2958 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2959 (nCnt > 0));
2960
2961 if (nCnt == 0)
2962 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2963 nInit * 10);
2964
2965 /*
2966 * readAck
2967 * through clock stretch, slave has given a SCL signal,
2968 * so the SDA data can be directly read.
2969 */
2970 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2971
2972 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2973 dev->gpio_val = gpio_logic_value;
2974 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2975 status = 0;
2976 } else {
2977 dev->gpio_val = gpio_logic_value;
2978 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2979 }
2980
2981 /* read SDA end, set the SCL to output 0, after this operation,
2982 SDA direction can be changed. */
2983 dev->gpio_val = gpio_logic_value;
2984 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2985 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2986 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2987
2988 return status;
2989 }
2990
2991 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2992 {
2993 int status = 0;
2994
2995 /* set SDA to ouput */
2996 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2998
2999 /* set SCL = 0 (output); set SDA = 0 (output) */
3000 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3001 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3002 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3003
3004 /* set SCL = 1 (output); set SDA = 0 (output) */
3005 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3006 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3007
3008 /* set SCL = 0 (output); set SDA = 0 (output) */
3009 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3010 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3011
3012 /* set SDA to input,and then the slave will read data from SDA. */
3013 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3014 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3015
3016 return status;
3017 }
3018
3019 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3020 {
3021 int status = 0;
3022
3023 /* set scl to output ; set sda to input */
3024 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3025 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3026 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3027
3028 /* set scl to output 0; set sda to input */
3029 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3030 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3031
3032 /* set scl to output 1; set sda to input */
3033 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3034 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3035
3036 return status;
3037 }
3038
3039 /*****************************************************************************
3040 * G P I O I2C related functions *
3041 ******************************************************************************/
3042 /* cx231xx_gpio_i2c_read
3043 * Function to read data from gpio based I2C interface
3044 */
3045 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3046 {
3047 int status = 0;
3048 int i = 0;
3049
3050 /* get the lock */
3051 mutex_lock(&dev->gpio_i2c_lock);
3052
3053 /* start */
3054 status = cx231xx_gpio_i2c_start(dev);
3055
3056 /* write dev_addr */
3057 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3058
3059 /* readAck */
3060 status = cx231xx_gpio_i2c_read_ack(dev);
3061
3062 /* read data */
3063 for (i = 0; i < len; i++) {
3064 /* read data */
3065 buf[i] = 0;
3066 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3067
3068 if ((i + 1) != len) {
3069 /* only do write ack if we more length */
3070 status = cx231xx_gpio_i2c_write_ack(dev);
3071 }
3072 }
3073
3074 /* write NAK - inform reads are complete */
3075 status = cx231xx_gpio_i2c_write_nak(dev);
3076
3077 /* write end */
3078 status = cx231xx_gpio_i2c_end(dev);
3079
3080 /* release the lock */
3081 mutex_unlock(&dev->gpio_i2c_lock);
3082
3083 return status;
3084 }
3085
3086 /* cx231xx_gpio_i2c_write
3087 * Function to write data to gpio based I2C interface
3088 */
3089 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3090 {
3091 int status = 0;
3092 int i = 0;
3093
3094 /* get the lock */
3095 mutex_lock(&dev->gpio_i2c_lock);
3096
3097 /* start */
3098 status = cx231xx_gpio_i2c_start(dev);
3099
3100 /* write dev_addr */
3101 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3102
3103 /* read Ack */
3104 status = cx231xx_gpio_i2c_read_ack(dev);
3105
3106 for (i = 0; i < len; i++) {
3107 /* Write data */
3108 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3109
3110 /* read Ack */
3111 status = cx231xx_gpio_i2c_read_ack(dev);
3112 }
3113
3114 /* write End */
3115 status = cx231xx_gpio_i2c_end(dev);
3116
3117 /* release the lock */
3118 mutex_unlock(&dev->gpio_i2c_lock);
3119
3120 return 0;
3121 }
Linux with added FPC-III support