drivers/net/wireless/b43/dma.h

   1 #ifndef B43_DMA_H_
   2 #define B43_DMA_H_
   3
   4 #include <linux/ieee80211.h>
   5 #include <linux/spinlock.h>
   6
   7 #include "b43.h"
   8
   9
  10 /* DMA-Interrupt reasons. */
  11 #define B43_DMAIRQ_FATALMASK    ((1 << 10) | (1 << 11) | (1 << 12) \
  12                                          | (1 << 14) | (1 << 15))
  13 #define B43_DMAIRQ_NONFATALMASK (1 << 13)
  14 #define B43_DMAIRQ_RX_DONE              (1 << 16)
  15
  16 /*** 32-bit DMA Engine. ***/
  17
  18 /* 32-bit DMA controller registers. */
  19 #define B43_DMA32_TXCTL                         0x00
  20 #define         B43_DMA32_TXENABLE                      0x00000001
  21 #define         B43_DMA32_TXSUSPEND                     0x00000002
  22 #define         B43_DMA32_TXLOOPBACK            0x00000004
  23 #define         B43_DMA32_TXFLUSH                       0x00000010
  24 #define         B43_DMA32_TXADDREXT_MASK                0x00030000
  25 #define         B43_DMA32_TXADDREXT_SHIFT               16
  26 #define B43_DMA32_TXRING                                0x04
  27 #define B43_DMA32_TXINDEX                               0x08
  28 #define B43_DMA32_TXSTATUS                              0x0C
  29 #define         B43_DMA32_TXDPTR                        0x00000FFF
  30 #define         B43_DMA32_TXSTATE                       0x0000F000
  31 #define                 B43_DMA32_TXSTAT_DISABLED       0x00000000
  32 #define                 B43_DMA32_TXSTAT_ACTIVE 0x00001000
  33 #define                 B43_DMA32_TXSTAT_IDLEWAIT       0x00002000
  34 #define                 B43_DMA32_TXSTAT_STOPPED        0x00003000
  35 #define                 B43_DMA32_TXSTAT_SUSP   0x00004000
  36 #define         B43_DMA32_TXERROR                       0x000F0000
  37 #define                 B43_DMA32_TXERR_NOERR   0x00000000
  38 #define                 B43_DMA32_TXERR_PROT    0x00010000
  39 #define                 B43_DMA32_TXERR_UNDERRUN        0x00020000
  40 #define                 B43_DMA32_TXERR_BUFREAD 0x00030000
  41 #define                 B43_DMA32_TXERR_DESCREAD        0x00040000
  42 #define         B43_DMA32_TXACTIVE                      0xFFF00000
  43 #define B43_DMA32_RXCTL                         0x10
  44 #define         B43_DMA32_RXENABLE                      0x00000001
  45 #define         B43_DMA32_RXFROFF_MASK          0x000000FE
  46 #define         B43_DMA32_RXFROFF_SHIFT         1
  47 #define         B43_DMA32_RXDIRECTFIFO          0x00000100
  48 #define         B43_DMA32_RXADDREXT_MASK                0x00030000
  49 #define         B43_DMA32_RXADDREXT_SHIFT               16
  50 #define B43_DMA32_RXRING                                0x14
  51 #define B43_DMA32_RXINDEX                               0x18
  52 #define B43_DMA32_RXSTATUS                              0x1C
  53 #define         B43_DMA32_RXDPTR                        0x00000FFF
  54 #define         B43_DMA32_RXSTATE                       0x0000F000
  55 #define                 B43_DMA32_RXSTAT_DISABLED       0x00000000
  56 #define                 B43_DMA32_RXSTAT_ACTIVE 0x00001000
  57 #define                 B43_DMA32_RXSTAT_IDLEWAIT       0x00002000
  58 #define                 B43_DMA32_RXSTAT_STOPPED        0x00003000
  59 #define         B43_DMA32_RXERROR                       0x000F0000
  60 #define                 B43_DMA32_RXERR_NOERR   0x00000000
  61 #define                 B43_DMA32_RXERR_PROT    0x00010000
  62 #define                 B43_DMA32_RXERR_OVERFLOW        0x00020000
  63 #define                 B43_DMA32_RXERR_BUFWRITE        0x00030000
  64 #define                 B43_DMA32_RXERR_DESCREAD        0x00040000
  65 #define         B43_DMA32_RXACTIVE                      0xFFF00000
  66
  67 /* 32-bit DMA descriptor. */
  68 struct b43_dmadesc32 {
  69         __le32 control;
  70         __le32 address;
  71 } __attribute__ ((__packed__));
  72 #define B43_DMA32_DCTL_BYTECNT          0x00001FFF
  73 #define B43_DMA32_DCTL_ADDREXT_MASK             0x00030000
  74 #define B43_DMA32_DCTL_ADDREXT_SHIFT    16
  75 #define B43_DMA32_DCTL_DTABLEEND                0x10000000
  76 #define B43_DMA32_DCTL_IRQ                      0x20000000
  77 #define B43_DMA32_DCTL_FRAMEEND         0x40000000
  78 #define B43_DMA32_DCTL_FRAMESTART               0x80000000
  79
  80 /*** 64-bit DMA Engine. ***/
  81
  82 /* 64-bit DMA controller registers. */
  83 #define B43_DMA64_TXCTL                         0x00
  84 #define         B43_DMA64_TXENABLE                      0x00000001
  85 #define         B43_DMA64_TXSUSPEND                     0x00000002
  86 #define         B43_DMA64_TXLOOPBACK            0x00000004
  87 #define         B43_DMA64_TXFLUSH                       0x00000010
  88 #define         B43_DMA64_TXADDREXT_MASK                0x00030000
  89 #define         B43_DMA64_TXADDREXT_SHIFT               16
  90 #define B43_DMA64_TXINDEX                               0x04
  91 #define B43_DMA64_TXRINGLO                              0x08
  92 #define B43_DMA64_TXRINGHI                              0x0C
  93 #define B43_DMA64_TXSTATUS                              0x10
  94 #define         B43_DMA64_TXSTATDPTR            0x00001FFF
  95 #define         B43_DMA64_TXSTAT                        0xF0000000
  96 #define                 B43_DMA64_TXSTAT_DISABLED       0x00000000
  97 #define                 B43_DMA64_TXSTAT_ACTIVE 0x10000000
  98 #define                 B43_DMA64_TXSTAT_IDLEWAIT       0x20000000
  99 #define                 B43_DMA64_TXSTAT_STOPPED        0x30000000
 100 #define                 B43_DMA64_TXSTAT_SUSP   0x40000000
 101 #define B43_DMA64_TXERROR                               0x14
 102 #define         B43_DMA64_TXERRDPTR                     0x0001FFFF
 103 #define         B43_DMA64_TXERR                 0xF0000000
 104 #define                 B43_DMA64_TXERR_NOERR   0x00000000
 105 #define                 B43_DMA64_TXERR_PROT    0x10000000
 106 #define                 B43_DMA64_TXERR_UNDERRUN        0x20000000
 107 #define                 B43_DMA64_TXERR_TRANSFER        0x30000000
 108 #define                 B43_DMA64_TXERR_DESCREAD        0x40000000
 109 #define                 B43_DMA64_TXERR_CORE    0x50000000
 110 #define B43_DMA64_RXCTL                         0x20
 111 #define         B43_DMA64_RXENABLE                      0x00000001
 112 #define         B43_DMA64_RXFROFF_MASK          0x000000FE
 113 #define         B43_DMA64_RXFROFF_SHIFT         1
 114 #define         B43_DMA64_RXDIRECTFIFO          0x00000100
 115 #define         B43_DMA64_RXADDREXT_MASK                0x00030000
 116 #define         B43_DMA64_RXADDREXT_SHIFT               16
 117 #define B43_DMA64_RXINDEX                               0x24
 118 #define B43_DMA64_RXRINGLO                              0x28
 119 #define B43_DMA64_RXRINGHI                              0x2C
 120 #define B43_DMA64_RXSTATUS                              0x30
 121 #define         B43_DMA64_RXSTATDPTR            0x00001FFF
 122 #define         B43_DMA64_RXSTAT                        0xF0000000
 123 #define                 B43_DMA64_RXSTAT_DISABLED       0x00000000
 124 #define                 B43_DMA64_RXSTAT_ACTIVE 0x10000000
 125 #define                 B43_DMA64_RXSTAT_IDLEWAIT       0x20000000
 126 #define                 B43_DMA64_RXSTAT_STOPPED        0x30000000
 127 #define                 B43_DMA64_RXSTAT_SUSP   0x40000000
 128 #define B43_DMA64_RXERROR                               0x34
 129 #define         B43_DMA64_RXERRDPTR                     0x0001FFFF
 130 #define         B43_DMA64_RXERR                 0xF0000000
 131 #define                 B43_DMA64_RXERR_NOERR   0x00000000
 132 #define                 B43_DMA64_RXERR_PROT    0x10000000
 133 #define                 B43_DMA64_RXERR_UNDERRUN        0x20000000
 134 #define                 B43_DMA64_RXERR_TRANSFER        0x30000000
 135 #define                 B43_DMA64_RXERR_DESCREAD        0x40000000
 136 #define                 B43_DMA64_RXERR_CORE    0x50000000
 137
 138 /* 64-bit DMA descriptor. */
 139 struct b43_dmadesc64 {
 140         __le32 control0;
 141         __le32 control1;
 142         __le32 address_low;
 143         __le32 address_high;
 144 } __attribute__ ((__packed__));
 145 #define B43_DMA64_DCTL0_DTABLEEND               0x10000000
 146 #define B43_DMA64_DCTL0_IRQ                     0x20000000
 147 #define B43_DMA64_DCTL0_FRAMEEND                0x40000000
 148 #define B43_DMA64_DCTL0_FRAMESTART              0x80000000
 149 #define B43_DMA64_DCTL1_BYTECNT         0x00001FFF
 150 #define B43_DMA64_DCTL1_ADDREXT_MASK    0x00030000
 151 #define B43_DMA64_DCTL1_ADDREXT_SHIFT   16
 152
 153 struct b43_dmadesc_generic {
 154         union {
 155                 struct b43_dmadesc32 dma32;
 156                 struct b43_dmadesc64 dma64;
 157         } __attribute__ ((__packed__));
 158 } __attribute__ ((__packed__));
 159
 160 /* Misc DMA constants */
 161 #define B43_DMA_RINGMEMSIZE             PAGE_SIZE
 162 #define B43_DMA0_RX_FRAMEOFFSET         30
 163
 164 /* DMA engine tuning knobs */
 165 #define B43_TXRING_SLOTS                256
 166 #define B43_RXRING_SLOTS                64
 167 #define B43_DMA0_RX_BUFFERSIZE          IEEE80211_MAX_FRAME_LEN
 168
 169
 170 struct sk_buff;
 171 struct b43_private;
 172 struct b43_txstatus;
 173
 174 struct b43_dmadesc_meta {
 175         /* The kernel DMA-able buffer. */
 176         struct sk_buff *skb;
 177         /* DMA base bus-address of the descriptor buffer. */
 178         dma_addr_t dmaaddr;
 179         /* ieee80211 TX status. Only used once per 802.11 frag. */
 180         bool is_last_fragment;
 181 };
 182
 183 struct b43_dmaring;
 184
 185 /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
 186 struct b43_dma_ops {
 187         struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
 188                                                  int slot,
 189                                                  struct b43_dmadesc_meta **
 190                                                  meta);
 191         void (*fill_descriptor) (struct b43_dmaring * ring,
 192                                  struct b43_dmadesc_generic * desc,
 193                                  dma_addr_t dmaaddr, u16 bufsize, int start,
 194                                  int end, int irq);
 195         void (*poke_tx) (struct b43_dmaring * ring, int slot);
 196         void (*tx_suspend) (struct b43_dmaring * ring);
 197         void (*tx_resume) (struct b43_dmaring * ring);
 198         int (*get_current_rxslot) (struct b43_dmaring * ring);
 199         void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
 200 };
 201
 202 enum b43_dmatype {
 203         B43_DMA_30BIT   = 30,
 204         B43_DMA_32BIT   = 32,
 205         B43_DMA_64BIT   = 64,
 206 };
 207
 208 struct b43_dmaring {
 209         /* Lowlevel DMA ops. */
 210         const struct b43_dma_ops *ops;
 211         /* Kernel virtual base address of the ring memory. */
 212         void *descbase;
 213         /* Meta data about all descriptors. */
 214         struct b43_dmadesc_meta *meta;
 215         /* Cache of TX headers for each TX frame.
 216          * This is to avoid an allocation on each TX.
 217          * This is NULL for an RX ring.
 218          */
 219         u8 *txhdr_cache;
 220         /* (Unadjusted) DMA base bus-address of the ring memory. */
 221         dma_addr_t dmabase;
 222         /* Number of descriptor slots in the ring. */
 223         int nr_slots;
 224         /* Number of used descriptor slots. */
 225         int used_slots;
 226         /* Currently used slot in the ring. */
 227         int current_slot;
 228         /* Total number of packets sent. Statistics only. */
 229         unsigned int nr_tx_packets;
 230         /* Frameoffset in octets. */
 231         u32 frameoffset;
 232         /* Descriptor buffer size. */
 233         u16 rx_buffersize;
 234         /* The MMIO base register of the DMA controller. */
 235         u16 mmio_base;
 236         /* DMA controller index number (0-5). */
 237         int index;
 238         /* Boolean. Is this a TX ring? */
 239         bool tx;
 240         /* The type of DMA engine used. */
 241         enum b43_dmatype type;
 242         /* Boolean. Is this ring stopped at ieee80211 level? */
 243         bool stopped;
 244         /* The QOS priority assigned to this ring. Only used for TX rings.
 245          * This is the mac80211 "queue" value. */
 246         u8 queue_prio;
 247         /* Lock, only used for TX. */
 248         spinlock_t lock;
 249         struct b43_wldev *dev;
 250 #ifdef CONFIG_B43_DEBUG
 251         /* Maximum number of used slots. */
 252         int max_used_slots;
 253         /* Last time we injected a ring overflow. */
 254         unsigned long last_injected_overflow;
 255         /* Statistics: Number of successfully transmitted packets */
 256         u64 nr_succeed_tx_packets;
 257         /* Statistics: Number of failed TX packets */
 258         u64 nr_failed_tx_packets;
 259         /* Statistics: Total number of TX plus all retries. */
 260         u64 nr_total_packet_tries;
 261 #endif /* CONFIG_B43_DEBUG */
 262 };
 263
 264 static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
 265 {
 266         return b43_read32(ring->dev, ring->mmio_base + offset);
 267 }
 268
 269 static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
 270 {
 271         b43_write32(ring->dev, ring->mmio_base + offset, value);
 272 }
 273
 274 int b43_dma_init(struct b43_wldev *dev);
 275 void b43_dma_free(struct b43_wldev *dev);
 276
 277 void b43_dma_tx_suspend(struct b43_wldev *dev);
 278 void b43_dma_tx_resume(struct b43_wldev *dev);
 279
 280 void b43_dma_get_tx_stats(struct b43_wldev *dev,
 281                           struct ieee80211_tx_queue_stats *stats);
 282
 283 int b43_dma_tx(struct b43_wldev *dev,
 284                struct sk_buff *skb);
 285 void b43_dma_handle_txstatus(struct b43_wldev *dev,
 286                              const struct b43_txstatus *status);
 287
 288 void b43_dma_rx(struct b43_dmaring *ring);
 289
 290 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
 291                             unsigned int engine_index, bool enable);
 292
 293 #endif /* B43_DMA_H_ */