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ALSA: usb-audio: Avoid access before bLength check in build_audio_procunit()
[linux/fpc-iii.git] / sound / pci / hda / patch_hdmi.c
blob76ae627e3f930b1e23518ac534ce0c28834954f2
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <sound/core.h>
38 #include <sound/jack.h>
39 #include <sound/asoundef.h>
40 #include <sound/tlv.h>
41 #include <sound/hdaudio.h>
42 #include <sound/hda_i915.h>
43 #include <sound/hda_chmap.h>
44 #include "hda_codec.h"
45 #include "hda_local.h"
46 #include "hda_jack.h"
47
48 static bool static_hdmi_pcm;
49 module_param(static_hdmi_pcm, bool, 0644);
50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51
52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
57 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
58 || is_skylake(codec) || is_broxton(codec) \
59 || is_kabylake(codec))
60
61 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
62 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
63 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
64
65 struct hdmi_spec_per_cvt {
66 hda_nid_t cvt_nid;
67 int assigned;
68 unsigned int channels_min;
69 unsigned int channels_max;
70 u32 rates;
71 u64 formats;
72 unsigned int maxbps;
73 };
74
75 /* max. connections to a widget */
76 #define HDA_MAX_CONNECTIONS 32
77
78 struct hdmi_spec_per_pin {
79 hda_nid_t pin_nid;
80 /* pin idx, different device entries on the same pin use the same idx */
81 int pin_nid_idx;
82 int num_mux_nids;
83 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
84 int mux_idx;
85 hda_nid_t cvt_nid;
86
87 struct hda_codec *codec;
88 struct hdmi_eld sink_eld;
89 struct mutex lock;
90 struct delayed_work work;
91 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
92 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
93 int repoll_count;
94 bool setup; /* the stream has been set up by prepare callback */
95 int channels; /* current number of channels */
96 bool non_pcm;
97 bool chmap_set; /* channel-map override by ALSA API? */
98 unsigned char chmap[8]; /* ALSA API channel-map */
99 #ifdef CONFIG_SND_PROC_FS
100 struct snd_info_entry *proc_entry;
101 #endif
102 };
103
104 /* operations used by generic code that can be overridden by patches */
105 struct hdmi_ops {
106 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
107 unsigned char *buf, int *eld_size);
108
109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int ca, int active_channels, int conn_type);
111
112 /* enable/disable HBR (HD passthrough) */
113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114
115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
116 hda_nid_t pin_nid, u32 stream_tag, int format);
117
118 void (*pin_cvt_fixup)(struct hda_codec *codec,
119 struct hdmi_spec_per_pin *per_pin,
120 hda_nid_t cvt_nid);
121 };
122
123 struct hdmi_pcm {
124 struct hda_pcm *pcm;
125 struct snd_jack *jack;
126 struct snd_kcontrol *eld_ctl;
127 };
128
129 struct hdmi_spec {
130 int num_cvts;
131 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
132 hda_nid_t cvt_nids[4]; /* only for haswell fix */
133
134 int num_pins;
135 struct snd_array pins; /* struct hdmi_spec_per_pin */
136 struct hdmi_pcm pcm_rec[16];
137 struct mutex pcm_lock;
138 /* pcm_bitmap means which pcms have been assigned to pins*/
139 unsigned long pcm_bitmap;
140 int pcm_used; /* counter of pcm_rec[] */
141 /* bitmap shows whether the pcm is opened in user space
142 * bit 0 means the first playback PCM (PCM3);
143 * bit 1 means the second playback PCM, and so on.
144 */
145 unsigned long pcm_in_use;
146
147 struct hdmi_eld temp_eld;
148 struct hdmi_ops ops;
149
150 bool dyn_pin_out;
151 bool dyn_pcm_assign;
152 /*
153 * Non-generic VIA/NVIDIA specific
154 */
155 struct hda_multi_out multiout;
156 struct hda_pcm_stream pcm_playback;
157
158 /* i915/powerwell (Haswell+/Valleyview+) specific */
159 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
160 struct i915_audio_component_audio_ops i915_audio_ops;
161 bool i915_bound; /* was i915 bound in this driver? */
162
163 struct hdac_chmap chmap;
164 };
165
166 #ifdef CONFIG_SND_HDA_I915
167 static inline bool codec_has_acomp(struct hda_codec *codec)
168 {
169 struct hdmi_spec *spec = codec->spec;
170 return spec->use_acomp_notifier;
171 }
172 #else
173 #define codec_has_acomp(codec) false
174 #endif
175
176 struct hdmi_audio_infoframe {
177 u8 type; /* 0x84 */
178 u8 ver; /* 0x01 */
179 u8 len; /* 0x0a */
180
181 u8 checksum;
182
183 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
184 u8 SS01_SF24;
185 u8 CXT04;
186 u8 CA;
187 u8 LFEPBL01_LSV36_DM_INH7;
188 };
189
190 struct dp_audio_infoframe {
191 u8 type; /* 0x84 */
192 u8 len; /* 0x1b */
193 u8 ver; /* 0x11 << 2 */
194
195 u8 CC02_CT47; /* match with HDMI infoframe from this on */
196 u8 SS01_SF24;
197 u8 CXT04;
198 u8 CA;
199 u8 LFEPBL01_LSV36_DM_INH7;
200 };
201
202 union audio_infoframe {
203 struct hdmi_audio_infoframe hdmi;
204 struct dp_audio_infoframe dp;
205 u8 bytes[0];
206 };
207
208 /*
209 * HDMI routines
210 */
211
212 #define get_pin(spec, idx) \
213 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
214 #define get_cvt(spec, idx) \
215 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
216 /* obtain hdmi_pcm object assigned to idx */
217 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
218 /* obtain hda_pcm object assigned to idx */
219 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
220
221 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
222 {
223 struct hdmi_spec *spec = codec->spec;
224 int pin_idx;
225
226 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
227 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
228 return pin_idx;
229
230 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
231 return -EINVAL;
232 }
233
234 static int hinfo_to_pcm_index(struct hda_codec *codec,
235 struct hda_pcm_stream *hinfo)
236 {
237 struct hdmi_spec *spec = codec->spec;
238 int pcm_idx;
239
240 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
241 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
242 return pcm_idx;
243
244 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
245 return -EINVAL;
246 }
247
248 static int hinfo_to_pin_index(struct hda_codec *codec,
249 struct hda_pcm_stream *hinfo)
250 {
251 struct hdmi_spec *spec = codec->spec;
252 struct hdmi_spec_per_pin *per_pin;
253 int pin_idx;
254
255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
256 per_pin = get_pin(spec, pin_idx);
257 if (per_pin->pcm &&
258 per_pin->pcm->pcm->stream == hinfo)
259 return pin_idx;
260 }
261
262 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
263 return -EINVAL;
264 }
265
266 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
267 int pcm_idx)
268 {
269 int i;
270 struct hdmi_spec_per_pin *per_pin;
271
272 for (i = 0; i < spec->num_pins; i++) {
273 per_pin = get_pin(spec, i);
274 if (per_pin->pcm_idx == pcm_idx)
275 return per_pin;
276 }
277 return NULL;
278 }
279
280 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
281 {
282 struct hdmi_spec *spec = codec->spec;
283 int cvt_idx;
284
285 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
286 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
287 return cvt_idx;
288
289 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
290 return -EINVAL;
291 }
292
293 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
294 struct snd_ctl_elem_info *uinfo)
295 {
296 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
297 struct hdmi_spec *spec = codec->spec;
298 struct hdmi_spec_per_pin *per_pin;
299 struct hdmi_eld *eld;
300 int pcm_idx;
301
302 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
303
304 pcm_idx = kcontrol->private_value;
305 mutex_lock(&spec->pcm_lock);
306 per_pin = pcm_idx_to_pin(spec, pcm_idx);
307 if (!per_pin) {
308 /* no pin is bound to the pcm */
309 uinfo->count = 0;
310 mutex_unlock(&spec->pcm_lock);
311 return 0;
312 }
313 eld = &per_pin->sink_eld;
314 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
315 mutex_unlock(&spec->pcm_lock);
316
317 return 0;
318 }
319
320 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
321 struct snd_ctl_elem_value *ucontrol)
322 {
323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
324 struct hdmi_spec *spec = codec->spec;
325 struct hdmi_spec_per_pin *per_pin;
326 struct hdmi_eld *eld;
327 int pcm_idx;
328
329 pcm_idx = kcontrol->private_value;
330 mutex_lock(&spec->pcm_lock);
331 per_pin = pcm_idx_to_pin(spec, pcm_idx);
332 if (!per_pin) {
333 /* no pin is bound to the pcm */
334 memset(ucontrol->value.bytes.data, 0,
335 ARRAY_SIZE(ucontrol->value.bytes.data));
336 mutex_unlock(&spec->pcm_lock);
337 return 0;
338 }
339 eld = &per_pin->sink_eld;
340
341 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
342 eld->eld_size > ELD_MAX_SIZE) {
343 mutex_unlock(&spec->pcm_lock);
344 snd_BUG();
345 return -EINVAL;
346 }
347
348 memset(ucontrol->value.bytes.data, 0,
349 ARRAY_SIZE(ucontrol->value.bytes.data));
350 if (eld->eld_valid)
351 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
352 eld->eld_size);
353 mutex_unlock(&spec->pcm_lock);
354
355 return 0;
356 }
357
358 static struct snd_kcontrol_new eld_bytes_ctl = {
359 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
360 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
361 .name = "ELD",
362 .info = hdmi_eld_ctl_info,
363 .get = hdmi_eld_ctl_get,
364 };
365
366 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
367 int device)
368 {
369 struct snd_kcontrol *kctl;
370 struct hdmi_spec *spec = codec->spec;
371 int err;
372
373 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
374 if (!kctl)
375 return -ENOMEM;
376 kctl->private_value = pcm_idx;
377 kctl->id.device = device;
378
379 /* no pin nid is associated with the kctl now
380 * tbd: associate pin nid to eld ctl later
381 */
382 err = snd_hda_ctl_add(codec, 0, kctl);
383 if (err < 0)
384 return err;
385
386 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
387 return 0;
388 }
389
390 #ifdef BE_PARANOID
391 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
392 int *packet_index, int *byte_index)
393 {
394 int val;
395
396 val = snd_hda_codec_read(codec, pin_nid, 0,
397 AC_VERB_GET_HDMI_DIP_INDEX, 0);
398
399 *packet_index = val >> 5;
400 *byte_index = val & 0x1f;
401 }
402 #endif
403
404 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
405 int packet_index, int byte_index)
406 {
407 int val;
408
409 val = (packet_index << 5) | (byte_index & 0x1f);
410
411 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
412 }
413
414 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
415 unsigned char val)
416 {
417 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
418 }
419
420 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
421 {
422 struct hdmi_spec *spec = codec->spec;
423 int pin_out;
424
425 /* Unmute */
426 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
427 snd_hda_codec_write(codec, pin_nid, 0,
428 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
429
430 if (spec->dyn_pin_out)
431 /* Disable pin out until stream is active */
432 pin_out = 0;
433 else
434 /* Enable pin out: some machines with GM965 gets broken output
435 * when the pin is disabled or changed while using with HDMI
436 */
437 pin_out = PIN_OUT;
438
439 snd_hda_codec_write(codec, pin_nid, 0,
440 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
441 }
442
443 /*
444 * ELD proc files
445 */
446
447 #ifdef CONFIG_SND_PROC_FS
448 static void print_eld_info(struct snd_info_entry *entry,
449 struct snd_info_buffer *buffer)
450 {
451 struct hdmi_spec_per_pin *per_pin = entry->private_data;
452
453 mutex_lock(&per_pin->lock);
454 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
455 mutex_unlock(&per_pin->lock);
456 }
457
458 static void write_eld_info(struct snd_info_entry *entry,
459 struct snd_info_buffer *buffer)
460 {
461 struct hdmi_spec_per_pin *per_pin = entry->private_data;
462
463 mutex_lock(&per_pin->lock);
464 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
465 mutex_unlock(&per_pin->lock);
466 }
467
468 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
469 {
470 char name[32];
471 struct hda_codec *codec = per_pin->codec;
472 struct snd_info_entry *entry;
473 int err;
474
475 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
476 err = snd_card_proc_new(codec->card, name, &entry);
477 if (err < 0)
478 return err;
479
480 snd_info_set_text_ops(entry, per_pin, print_eld_info);
481 entry->c.text.write = write_eld_info;
482 entry->mode |= S_IWUSR;
483 per_pin->proc_entry = entry;
484
485 return 0;
486 }
487
488 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
489 {
490 if (!per_pin->codec->bus->shutdown) {
491 snd_info_free_entry(per_pin->proc_entry);
492 per_pin->proc_entry = NULL;
493 }
494 }
495 #else
496 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
497 int index)
498 {
499 return 0;
500 }
501 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
502 {
503 }
504 #endif
505
506 /*
507 * Audio InfoFrame routines
508 */
509
510 /*
511 * Enable Audio InfoFrame Transmission
512 */
513 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
514 hda_nid_t pin_nid)
515 {
516 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
517 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
518 AC_DIPXMIT_BEST);
519 }
520
521 /*
522 * Disable Audio InfoFrame Transmission
523 */
524 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
525 hda_nid_t pin_nid)
526 {
527 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
528 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
529 AC_DIPXMIT_DISABLE);
530 }
531
532 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
533 {
534 #ifdef CONFIG_SND_DEBUG_VERBOSE
535 int i;
536 int size;
537
538 size = snd_hdmi_get_eld_size(codec, pin_nid);
539 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
540
541 for (i = 0; i < 8; i++) {
542 size = snd_hda_codec_read(codec, pin_nid, 0,
543 AC_VERB_GET_HDMI_DIP_SIZE, i);
544 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
545 }
546 #endif
547 }
548
549 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
550 {
551 #ifdef BE_PARANOID
552 int i, j;
553 int size;
554 int pi, bi;
555 for (i = 0; i < 8; i++) {
556 size = snd_hda_codec_read(codec, pin_nid, 0,
557 AC_VERB_GET_HDMI_DIP_SIZE, i);
558 if (size == 0)
559 continue;
560
561 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
562 for (j = 1; j < 1000; j++) {
563 hdmi_write_dip_byte(codec, pin_nid, 0x0);
564 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
565 if (pi != i)
566 codec_dbg(codec, "dip index %d: %d != %d\n",
567 bi, pi, i);
568 if (bi == 0) /* byte index wrapped around */
569 break;
570 }
571 codec_dbg(codec,
572 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
573 i, size, j);
574 }
575 #endif
576 }
577
578 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
579 {
580 u8 *bytes = (u8 *)hdmi_ai;
581 u8 sum = 0;
582 int i;
583
584 hdmi_ai->checksum = 0;
585
586 for (i = 0; i < sizeof(*hdmi_ai); i++)
587 sum += bytes[i];
588
589 hdmi_ai->checksum = -sum;
590 }
591
592 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
593 hda_nid_t pin_nid,
594 u8 *dip, int size)
595 {
596 int i;
597
598 hdmi_debug_dip_size(codec, pin_nid);
599 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
600
601 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
602 for (i = 0; i < size; i++)
603 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
604 }
605
606 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
607 u8 *dip, int size)
608 {
609 u8 val;
610 int i;
611
612 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
613 != AC_DIPXMIT_BEST)
614 return false;
615
616 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
617 for (i = 0; i < size; i++) {
618 val = snd_hda_codec_read(codec, pin_nid, 0,
619 AC_VERB_GET_HDMI_DIP_DATA, 0);
620 if (val != dip[i])
621 return false;
622 }
623
624 return true;
625 }
626
627 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
628 hda_nid_t pin_nid,
629 int ca, int active_channels,
630 int conn_type)
631 {
632 union audio_infoframe ai;
633
634 memset(&ai, 0, sizeof(ai));
635 if (conn_type == 0) { /* HDMI */
636 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
637
638 hdmi_ai->type = 0x84;
639 hdmi_ai->ver = 0x01;
640 hdmi_ai->len = 0x0a;
641 hdmi_ai->CC02_CT47 = active_channels - 1;
642 hdmi_ai->CA = ca;
643 hdmi_checksum_audio_infoframe(hdmi_ai);
644 } else if (conn_type == 1) { /* DisplayPort */
645 struct dp_audio_infoframe *dp_ai = &ai.dp;
646
647 dp_ai->type = 0x84;
648 dp_ai->len = 0x1b;
649 dp_ai->ver = 0x11 << 2;
650 dp_ai->CC02_CT47 = active_channels - 1;
651 dp_ai->CA = ca;
652 } else {
653 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
654 pin_nid);
655 return;
656 }
657
658 /*
659 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
660 * sizeof(*dp_ai) to avoid partial match/update problems when
661 * the user switches between HDMI/DP monitors.
662 */
663 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
664 sizeof(ai))) {
665 codec_dbg(codec,
666 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
667 pin_nid,
668 active_channels, ca);
669 hdmi_stop_infoframe_trans(codec, pin_nid);
670 hdmi_fill_audio_infoframe(codec, pin_nid,
671 ai.bytes, sizeof(ai));
672 hdmi_start_infoframe_trans(codec, pin_nid);
673 }
674 }
675
676 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
677 struct hdmi_spec_per_pin *per_pin,
678 bool non_pcm)
679 {
680 struct hdmi_spec *spec = codec->spec;
681 struct hdac_chmap *chmap = &spec->chmap;
682 hda_nid_t pin_nid = per_pin->pin_nid;
683 int channels = per_pin->channels;
684 int active_channels;
685 struct hdmi_eld *eld;
686 int ca;
687
688 if (!channels)
689 return;
690
691 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
692 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
693 snd_hda_codec_write(codec, pin_nid, 0,
694 AC_VERB_SET_AMP_GAIN_MUTE,
695 AMP_OUT_UNMUTE);
696
697 eld = &per_pin->sink_eld;
698
699 ca = snd_hdac_channel_allocation(&codec->core,
700 eld->info.spk_alloc, channels,
701 per_pin->chmap_set, non_pcm, per_pin->chmap);
702
703 active_channels = snd_hdac_get_active_channels(ca);
704
705 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
706 active_channels);
707
708 /*
709 * always configure channel mapping, it may have been changed by the
710 * user in the meantime
711 */
712 snd_hdac_setup_channel_mapping(&spec->chmap,
713 pin_nid, non_pcm, ca, channels,
714 per_pin->chmap, per_pin->chmap_set);
715
716 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
717 eld->info.conn_type);
718
719 per_pin->non_pcm = non_pcm;
720 }
721
722 /*
723 * Unsolicited events
724 */
725
726 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
727
728 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
729 {
730 struct hdmi_spec *spec = codec->spec;
731 int pin_idx = pin_nid_to_pin_index(codec, nid);
732
733 if (pin_idx < 0)
734 return;
735 mutex_lock(&spec->pcm_lock);
736 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
737 snd_hda_jack_report_sync(codec);
738 mutex_unlock(&spec->pcm_lock);
739 }
740
741 static void jack_callback(struct hda_codec *codec,
742 struct hda_jack_callback *jack)
743 {
744 check_presence_and_report(codec, jack->nid);
745 }
746
747 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
748 {
749 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
750 struct hda_jack_tbl *jack;
751 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
752
753 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
754 if (!jack)
755 return;
756 jack->jack_dirty = 1;
757
758 codec_dbg(codec,
759 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
760 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
761 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
762
763 check_presence_and_report(codec, jack->nid);
764 }
765
766 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
767 {
768 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
769 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
770 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
771 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
772
773 codec_info(codec,
774 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
775 codec->addr,
776 tag,
777 subtag,
778 cp_state,
779 cp_ready);
780
781 /* TODO */
782 if (cp_state)
783 ;
784 if (cp_ready)
785 ;
786 }
787
788
789 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
790 {
791 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
792 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
793
794 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
795 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
796 return;
797 }
798
799 if (subtag == 0)
800 hdmi_intrinsic_event(codec, res);
801 else
802 hdmi_non_intrinsic_event(codec, res);
803 }
804
805 static void haswell_verify_D0(struct hda_codec *codec,
806 hda_nid_t cvt_nid, hda_nid_t nid)
807 {
808 int pwr;
809
810 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
811 * thus pins could only choose converter 0 for use. Make sure the
812 * converters are in correct power state */
813 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
814 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
815
816 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
817 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
818 AC_PWRST_D0);
819 msleep(40);
820 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
821 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
822 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
823 }
824 }
825
826 /*
827 * Callbacks
828 */
829
830 /* HBR should be Non-PCM, 8 channels */
831 #define is_hbr_format(format) \
832 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
833
834 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
835 bool hbr)
836 {
837 int pinctl, new_pinctl;
838
839 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
840 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
841 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
842
843 if (pinctl < 0)
844 return hbr ? -EINVAL : 0;
845
846 new_pinctl = pinctl & ~AC_PINCTL_EPT;
847 if (hbr)
848 new_pinctl |= AC_PINCTL_EPT_HBR;
849 else
850 new_pinctl |= AC_PINCTL_EPT_NATIVE;
851
852 codec_dbg(codec,
853 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
854 pin_nid,
855 pinctl == new_pinctl ? "" : "new-",
856 new_pinctl);
857
858 if (pinctl != new_pinctl)
859 snd_hda_codec_write(codec, pin_nid, 0,
860 AC_VERB_SET_PIN_WIDGET_CONTROL,
861 new_pinctl);
862 } else if (hbr)
863 return -EINVAL;
864
865 return 0;
866 }
867
868 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
869 hda_nid_t pin_nid, u32 stream_tag, int format)
870 {
871 struct hdmi_spec *spec = codec->spec;
872 int err;
873
874 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
875
876 if (err) {
877 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
878 return err;
879 }
880
881 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
882 return 0;
883 }
884
885 /* Try to find an available converter
886 * If pin_idx is less then zero, just try to find an available converter.
887 * Otherwise, try to find an available converter and get the cvt mux index
888 * of the pin.
889 */
890 static int hdmi_choose_cvt(struct hda_codec *codec,
891 int pin_idx, int *cvt_id)
892 {
893 struct hdmi_spec *spec = codec->spec;
894 struct hdmi_spec_per_pin *per_pin;
895 struct hdmi_spec_per_cvt *per_cvt = NULL;
896 int cvt_idx, mux_idx = 0;
897
898 /* pin_idx < 0 means no pin will be bound to the converter */
899 if (pin_idx < 0)
900 per_pin = NULL;
901 else
902 per_pin = get_pin(spec, pin_idx);
903
904 /* Dynamically assign converter to stream */
905 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
906 per_cvt = get_cvt(spec, cvt_idx);
907
908 /* Must not already be assigned */
909 if (per_cvt->assigned)
910 continue;
911 if (per_pin == NULL)
912 break;
913 /* Must be in pin's mux's list of converters */
914 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
915 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
916 break;
917 /* Not in mux list */
918 if (mux_idx == per_pin->num_mux_nids)
919 continue;
920 break;
921 }
922
923 /* No free converters */
924 if (cvt_idx == spec->num_cvts)
925 return -EBUSY;
926
927 if (per_pin != NULL)
928 per_pin->mux_idx = mux_idx;
929
930 if (cvt_id)
931 *cvt_id = cvt_idx;
932
933 return 0;
934 }
935
936 /* Assure the pin select the right convetor */
937 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
938 struct hdmi_spec_per_pin *per_pin)
939 {
940 hda_nid_t pin_nid = per_pin->pin_nid;
941 int mux_idx, curr;
942
943 mux_idx = per_pin->mux_idx;
944 curr = snd_hda_codec_read(codec, pin_nid, 0,
945 AC_VERB_GET_CONNECT_SEL, 0);
946 if (curr != mux_idx)
947 snd_hda_codec_write_cache(codec, pin_nid, 0,
948 AC_VERB_SET_CONNECT_SEL,
949 mux_idx);
950 }
951
952 /* get the mux index for the converter of the pins
953 * converter's mux index is the same for all pins on Intel platform
954 */
955 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
956 hda_nid_t cvt_nid)
957 {
958 int i;
959
960 for (i = 0; i < spec->num_cvts; i++)
961 if (spec->cvt_nids[i] == cvt_nid)
962 return i;
963 return -EINVAL;
964 }
965
966 /* Intel HDMI workaround to fix audio routing issue:
967 * For some Intel display codecs, pins share the same connection list.
968 * So a conveter can be selected by multiple pins and playback on any of these
969 * pins will generate sound on the external display, because audio flows from
970 * the same converter to the display pipeline. Also muting one pin may make
971 * other pins have no sound output.
972 * So this function assures that an assigned converter for a pin is not selected
973 * by any other pins.
974 */
975 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
976 hda_nid_t pin_nid, int mux_idx)
977 {
978 struct hdmi_spec *spec = codec->spec;
979 hda_nid_t nid;
980 int cvt_idx, curr;
981 struct hdmi_spec_per_cvt *per_cvt;
982
983 /* configure all pins, including "no physical connection" ones */
984 for_each_hda_codec_node(nid, codec) {
985 unsigned int wid_caps = get_wcaps(codec, nid);
986 unsigned int wid_type = get_wcaps_type(wid_caps);
987
988 if (wid_type != AC_WID_PIN)
989 continue;
990
991 if (nid == pin_nid)
992 continue;
993
994 curr = snd_hda_codec_read(codec, nid, 0,
995 AC_VERB_GET_CONNECT_SEL, 0);
996 if (curr != mux_idx)
997 continue;
998
999 /* choose an unassigned converter. The conveters in the
1000 * connection list are in the same order as in the codec.
1001 */
1002 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1003 per_cvt = get_cvt(spec, cvt_idx);
1004 if (!per_cvt->assigned) {
1005 codec_dbg(codec,
1006 "choose cvt %d for pin nid %d\n",
1007 cvt_idx, nid);
1008 snd_hda_codec_write_cache(codec, nid, 0,
1009 AC_VERB_SET_CONNECT_SEL,
1010 cvt_idx);
1011 break;
1012 }
1013 }
1014 }
1015 }
1016
1017 /* A wrapper of intel_not_share_asigned_cvt() */
1018 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1019 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1020 {
1021 int mux_idx;
1022 struct hdmi_spec *spec = codec->spec;
1023
1024 /* On Intel platform, the mapping of converter nid to
1025 * mux index of the pins are always the same.
1026 * The pin nid may be 0, this means all pins will not
1027 * share the converter.
1028 */
1029 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1030 if (mux_idx >= 0)
1031 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1032 }
1033
1034 /* skeleton caller of pin_cvt_fixup ops */
1035 static void pin_cvt_fixup(struct hda_codec *codec,
1036 struct hdmi_spec_per_pin *per_pin,
1037 hda_nid_t cvt_nid)
1038 {
1039 struct hdmi_spec *spec = codec->spec;
1040
1041 if (spec->ops.pin_cvt_fixup)
1042 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1043 }
1044
1045 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1046 * in dyn_pcm_assign mode.
1047 */
1048 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1049 struct hda_codec *codec,
1050 struct snd_pcm_substream *substream)
1051 {
1052 struct hdmi_spec *spec = codec->spec;
1053 struct snd_pcm_runtime *runtime = substream->runtime;
1054 int cvt_idx, pcm_idx;
1055 struct hdmi_spec_per_cvt *per_cvt = NULL;
1056 int err;
1057
1058 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1059 if (pcm_idx < 0)
1060 return -EINVAL;
1061
1062 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1063 if (err)
1064 return err;
1065
1066 per_cvt = get_cvt(spec, cvt_idx);
1067 per_cvt->assigned = 1;
1068 hinfo->nid = per_cvt->cvt_nid;
1069
1070 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1071
1072 set_bit(pcm_idx, &spec->pcm_in_use);
1073 /* todo: setup spdif ctls assign */
1074
1075 /* Initially set the converter's capabilities */
1076 hinfo->channels_min = per_cvt->channels_min;
1077 hinfo->channels_max = per_cvt->channels_max;
1078 hinfo->rates = per_cvt->rates;
1079 hinfo->formats = per_cvt->formats;
1080 hinfo->maxbps = per_cvt->maxbps;
1081
1082 /* Store the updated parameters */
1083 runtime->hw.channels_min = hinfo->channels_min;
1084 runtime->hw.channels_max = hinfo->channels_max;
1085 runtime->hw.formats = hinfo->formats;
1086 runtime->hw.rates = hinfo->rates;
1087
1088 snd_pcm_hw_constraint_step(substream->runtime, 0,
1089 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1090 return 0;
1091 }
1092
1093 /*
1094 * HDA PCM callbacks
1095 */
1096 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1097 struct hda_codec *codec,
1098 struct snd_pcm_substream *substream)
1099 {
1100 struct hdmi_spec *spec = codec->spec;
1101 struct snd_pcm_runtime *runtime = substream->runtime;
1102 int pin_idx, cvt_idx, pcm_idx;
1103 struct hdmi_spec_per_pin *per_pin;
1104 struct hdmi_eld *eld;
1105 struct hdmi_spec_per_cvt *per_cvt = NULL;
1106 int err;
1107
1108 /* Validate hinfo */
1109 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1110 if (pcm_idx < 0)
1111 return -EINVAL;
1112
1113 mutex_lock(&spec->pcm_lock);
1114 pin_idx = hinfo_to_pin_index(codec, hinfo);
1115 if (!spec->dyn_pcm_assign) {
1116 if (snd_BUG_ON(pin_idx < 0)) {
1117 mutex_unlock(&spec->pcm_lock);
1118 return -EINVAL;
1119 }
1120 } else {
1121 /* no pin is assigned to the PCM
1122 * PA need pcm open successfully when probe
1123 */
1124 if (pin_idx < 0) {
1125 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1126 mutex_unlock(&spec->pcm_lock);
1127 return err;
1128 }
1129 }
1130
1131 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1132 if (err < 0) {
1133 mutex_unlock(&spec->pcm_lock);
1134 return err;
1135 }
1136
1137 per_cvt = get_cvt(spec, cvt_idx);
1138 /* Claim converter */
1139 per_cvt->assigned = 1;
1140
1141 set_bit(pcm_idx, &spec->pcm_in_use);
1142 per_pin = get_pin(spec, pin_idx);
1143 per_pin->cvt_nid = per_cvt->cvt_nid;
1144 hinfo->nid = per_cvt->cvt_nid;
1145
1146 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1147 AC_VERB_SET_CONNECT_SEL,
1148 per_pin->mux_idx);
1149
1150 /* configure unused pins to choose other converters */
1151 pin_cvt_fixup(codec, per_pin, 0);
1152
1153 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1154
1155 /* Initially set the converter's capabilities */
1156 hinfo->channels_min = per_cvt->channels_min;
1157 hinfo->channels_max = per_cvt->channels_max;
1158 hinfo->rates = per_cvt->rates;
1159 hinfo->formats = per_cvt->formats;
1160 hinfo->maxbps = per_cvt->maxbps;
1161
1162 eld = &per_pin->sink_eld;
1163 /* Restrict capabilities by ELD if this isn't disabled */
1164 if (!static_hdmi_pcm && eld->eld_valid) {
1165 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1166 if (hinfo->channels_min > hinfo->channels_max ||
1167 !hinfo->rates || !hinfo->formats) {
1168 per_cvt->assigned = 0;
1169 hinfo->nid = 0;
1170 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1171 mutex_unlock(&spec->pcm_lock);
1172 return -ENODEV;
1173 }
1174 }
1175
1176 mutex_unlock(&spec->pcm_lock);
1177 /* Store the updated parameters */
1178 runtime->hw.channels_min = hinfo->channels_min;
1179 runtime->hw.channels_max = hinfo->channels_max;
1180 runtime->hw.formats = hinfo->formats;
1181 runtime->hw.rates = hinfo->rates;
1182
1183 snd_pcm_hw_constraint_step(substream->runtime, 0,
1184 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1185 return 0;
1186 }
1187
1188 /*
1189 * HDA/HDMI auto parsing
1190 */
1191 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1192 {
1193 struct hdmi_spec *spec = codec->spec;
1194 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1195 hda_nid_t pin_nid = per_pin->pin_nid;
1196
1197 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1198 codec_warn(codec,
1199 "HDMI: pin %d wcaps %#x does not support connection list\n",
1200 pin_nid, get_wcaps(codec, pin_nid));
1201 return -EINVAL;
1202 }
1203
1204 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1205 per_pin->mux_nids,
1206 HDA_MAX_CONNECTIONS);
1207
1208 return 0;
1209 }
1210
1211 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1212 struct hdmi_spec_per_pin *per_pin)
1213 {
1214 int i;
1215
1216 /* try the prefer PCM */
1217 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1218 return per_pin->pin_nid_idx;
1219
1220 /* have a second try; check the "reserved area" over num_pins */
1221 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1222 if (!test_bit(i, &spec->pcm_bitmap))
1223 return i;
1224 }
1225
1226 /* the last try; check the empty slots in pins */
1227 for (i = 0; i < spec->num_pins; i++) {
1228 if (!test_bit(i, &spec->pcm_bitmap))
1229 return i;
1230 }
1231 return -EBUSY;
1232 }
1233
1234 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1235 struct hdmi_spec_per_pin *per_pin)
1236 {
1237 int idx;
1238
1239 /* pcm already be attached to the pin */
1240 if (per_pin->pcm)
1241 return;
1242 idx = hdmi_find_pcm_slot(spec, per_pin);
1243 if (idx == -EBUSY)
1244 return;
1245 per_pin->pcm_idx = idx;
1246 per_pin->pcm = get_hdmi_pcm(spec, idx);
1247 set_bit(idx, &spec->pcm_bitmap);
1248 }
1249
1250 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1251 struct hdmi_spec_per_pin *per_pin)
1252 {
1253 int idx;
1254
1255 /* pcm already be detached from the pin */
1256 if (!per_pin->pcm)
1257 return;
1258 idx = per_pin->pcm_idx;
1259 per_pin->pcm_idx = -1;
1260 per_pin->pcm = NULL;
1261 if (idx >= 0 && idx < spec->pcm_used)
1262 clear_bit(idx, &spec->pcm_bitmap);
1263 }
1264
1265 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1266 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1267 {
1268 int mux_idx;
1269
1270 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1271 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1272 break;
1273 return mux_idx;
1274 }
1275
1276 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1277
1278 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1279 struct hdmi_spec_per_pin *per_pin)
1280 {
1281 struct hda_codec *codec = per_pin->codec;
1282 struct hda_pcm *pcm;
1283 struct hda_pcm_stream *hinfo;
1284 struct snd_pcm_substream *substream;
1285 int mux_idx;
1286 bool non_pcm;
1287
1288 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1289 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1290 else
1291 return;
1292 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1293 return;
1294
1295 /* hdmi audio only uses playback and one substream */
1296 hinfo = pcm->stream;
1297 substream = pcm->pcm->streams[0].substream;
1298
1299 per_pin->cvt_nid = hinfo->nid;
1300
1301 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1302 if (mux_idx < per_pin->num_mux_nids)
1303 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1304 AC_VERB_SET_CONNECT_SEL,
1305 mux_idx);
1306 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1307
1308 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1309 if (substream->runtime)
1310 per_pin->channels = substream->runtime->channels;
1311 per_pin->setup = true;
1312 per_pin->mux_idx = mux_idx;
1313
1314 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1315 }
1316
1317 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1318 struct hdmi_spec_per_pin *per_pin)
1319 {
1320 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1321 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1322
1323 per_pin->chmap_set = false;
1324 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1325
1326 per_pin->setup = false;
1327 per_pin->channels = 0;
1328 }
1329
1330 /* update per_pin ELD from the given new ELD;
1331 * setup info frame and notification accordingly
1332 */
1333 static void update_eld(struct hda_codec *codec,
1334 struct hdmi_spec_per_pin *per_pin,
1335 struct hdmi_eld *eld)
1336 {
1337 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1338 struct hdmi_spec *spec = codec->spec;
1339 bool old_eld_valid = pin_eld->eld_valid;
1340 bool eld_changed;
1341 int pcm_idx = -1;
1342
1343 /* for monitor disconnection, save pcm_idx firstly */
1344 pcm_idx = per_pin->pcm_idx;
1345 if (spec->dyn_pcm_assign) {
1346 if (eld->eld_valid) {
1347 hdmi_attach_hda_pcm(spec, per_pin);
1348 hdmi_pcm_setup_pin(spec, per_pin);
1349 } else {
1350 hdmi_pcm_reset_pin(spec, per_pin);
1351 hdmi_detach_hda_pcm(spec, per_pin);
1352 }
1353 }
1354 /* if pcm_idx == -1, it means this is in monitor connection event
1355 * we can get the correct pcm_idx now.
1356 */
1357 if (pcm_idx == -1)
1358 pcm_idx = per_pin->pcm_idx;
1359
1360 if (eld->eld_valid)
1361 snd_hdmi_show_eld(codec, &eld->info);
1362
1363 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1364 if (eld->eld_valid && pin_eld->eld_valid)
1365 if (pin_eld->eld_size != eld->eld_size ||
1366 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1367 eld->eld_size) != 0)
1368 eld_changed = true;
1369
1370 pin_eld->monitor_present = eld->monitor_present;
1371 pin_eld->eld_valid = eld->eld_valid;
1372 pin_eld->eld_size = eld->eld_size;
1373 if (eld->eld_valid)
1374 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1375 pin_eld->info = eld->info;
1376
1377 /*
1378 * Re-setup pin and infoframe. This is needed e.g. when
1379 * - sink is first plugged-in
1380 * - transcoder can change during stream playback on Haswell
1381 * and this can make HW reset converter selection on a pin.
1382 */
1383 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1384 pin_cvt_fixup(codec, per_pin, 0);
1385 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1386 }
1387
1388 if (eld_changed && pcm_idx >= 0)
1389 snd_ctl_notify(codec->card,
1390 SNDRV_CTL_EVENT_MASK_VALUE |
1391 SNDRV_CTL_EVENT_MASK_INFO,
1392 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1393 }
1394
1395 /* update ELD and jack state via HD-audio verbs */
1396 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1397 int repoll)
1398 {
1399 struct hda_jack_tbl *jack;
1400 struct hda_codec *codec = per_pin->codec;
1401 struct hdmi_spec *spec = codec->spec;
1402 struct hdmi_eld *eld = &spec->temp_eld;
1403 hda_nid_t pin_nid = per_pin->pin_nid;
1404 /*
1405 * Always execute a GetPinSense verb here, even when called from
1406 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1407 * response's PD bit is not the real PD value, but indicates that
1408 * the real PD value changed. An older version of the HD-audio
1409 * specification worked this way. Hence, we just ignore the data in
1410 * the unsolicited response to avoid custom WARs.
1411 */
1412 int present;
1413 bool ret;
1414 bool do_repoll = false;
1415
1416 present = snd_hda_pin_sense(codec, pin_nid);
1417
1418 mutex_lock(&per_pin->lock);
1419 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1420 if (eld->monitor_present)
1421 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1422 else
1423 eld->eld_valid = false;
1424
1425 codec_dbg(codec,
1426 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1427 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1428
1429 if (eld->eld_valid) {
1430 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1431 &eld->eld_size) < 0)
1432 eld->eld_valid = false;
1433 else {
1434 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1435 eld->eld_size) < 0)
1436 eld->eld_valid = false;
1437 }
1438 if (!eld->eld_valid && repoll)
1439 do_repoll = true;
1440 }
1441
1442 if (do_repoll)
1443 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1444 else
1445 update_eld(codec, per_pin, eld);
1446
1447 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1448
1449 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1450 if (jack)
1451 jack->block_report = !ret;
1452
1453 mutex_unlock(&per_pin->lock);
1454 return ret;
1455 }
1456
1457 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1458 struct hdmi_spec_per_pin *per_pin)
1459 {
1460 struct hdmi_spec *spec = codec->spec;
1461 struct snd_jack *jack = NULL;
1462 struct hda_jack_tbl *jack_tbl;
1463
1464 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1465 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1466 * NULL even after snd_hda_jack_tbl_clear() is called to
1467 * free snd_jack. This may cause access invalid memory
1468 * when calling snd_jack_report
1469 */
1470 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1471 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1472 else if (!spec->dyn_pcm_assign) {
1473 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1474 if (jack_tbl)
1475 jack = jack_tbl->jack;
1476 }
1477 return jack;
1478 }
1479
1480 /* update ELD and jack state via audio component */
1481 static void sync_eld_via_acomp(struct hda_codec *codec,
1482 struct hdmi_spec_per_pin *per_pin)
1483 {
1484 struct hdmi_spec *spec = codec->spec;
1485 struct hdmi_eld *eld = &spec->temp_eld;
1486 struct snd_jack *jack = NULL;
1487 int size;
1488
1489 mutex_lock(&per_pin->lock);
1490 eld->monitor_present = false;
1491 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1492 &eld->monitor_present, eld->eld_buffer,
1493 ELD_MAX_SIZE);
1494 if (size > 0) {
1495 size = min(size, ELD_MAX_SIZE);
1496 if (snd_hdmi_parse_eld(codec, &eld->info,
1497 eld->eld_buffer, size) < 0)
1498 size = -EINVAL;
1499 }
1500
1501 if (size > 0) {
1502 eld->eld_valid = true;
1503 eld->eld_size = size;
1504 } else {
1505 eld->eld_valid = false;
1506 eld->eld_size = 0;
1507 }
1508
1509 /* pcm_idx >=0 before update_eld() means it is in monitor
1510 * disconnected event. Jack must be fetched before update_eld()
1511 */
1512 jack = pin_idx_to_jack(codec, per_pin);
1513 update_eld(codec, per_pin, eld);
1514 if (jack == NULL)
1515 jack = pin_idx_to_jack(codec, per_pin);
1516 if (jack == NULL)
1517 goto unlock;
1518 snd_jack_report(jack,
1519 eld->monitor_present ? SND_JACK_AVOUT : 0);
1520 unlock:
1521 mutex_unlock(&per_pin->lock);
1522 }
1523
1524 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1525 {
1526 struct hda_codec *codec = per_pin->codec;
1527 int ret;
1528
1529 /* no temporary power up/down needed for component notifier */
1530 if (!codec_has_acomp(codec)) {
1531 ret = snd_hda_power_up_pm(codec);
1532 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1533 snd_hda_power_down_pm(codec);
1534 return false;
1535 }
1536 }
1537
1538 if (codec_has_acomp(codec)) {
1539 sync_eld_via_acomp(codec, per_pin);
1540 ret = false; /* don't call snd_hda_jack_report_sync() */
1541 } else {
1542 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1543 }
1544
1545 if (!codec_has_acomp(codec))
1546 snd_hda_power_down_pm(codec);
1547
1548 return ret;
1549 }
1550
1551 static void hdmi_repoll_eld(struct work_struct *work)
1552 {
1553 struct hdmi_spec_per_pin *per_pin =
1554 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1555 struct hda_codec *codec = per_pin->codec;
1556 struct hdmi_spec *spec = codec->spec;
1557
1558 if (per_pin->repoll_count++ > 6)
1559 per_pin->repoll_count = 0;
1560
1561 mutex_lock(&spec->pcm_lock);
1562 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1563 snd_hda_jack_report_sync(per_pin->codec);
1564 mutex_unlock(&spec->pcm_lock);
1565 }
1566
1567 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1568 hda_nid_t nid);
1569
1570 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1571 {
1572 struct hdmi_spec *spec = codec->spec;
1573 unsigned int caps, config;
1574 int pin_idx;
1575 struct hdmi_spec_per_pin *per_pin;
1576 int err;
1577
1578 caps = snd_hda_query_pin_caps(codec, pin_nid);
1579 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1580 return 0;
1581
1582 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1583 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1584 return 0;
1585
1586 if (is_haswell_plus(codec))
1587 intel_haswell_fixup_connect_list(codec, pin_nid);
1588
1589 pin_idx = spec->num_pins;
1590 per_pin = snd_array_new(&spec->pins);
1591 if (!per_pin)
1592 return -ENOMEM;
1593
1594 per_pin->pin_nid = pin_nid;
1595 per_pin->non_pcm = false;
1596 if (spec->dyn_pcm_assign)
1597 per_pin->pcm_idx = -1;
1598 else {
1599 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1600 per_pin->pcm_idx = pin_idx;
1601 }
1602 per_pin->pin_nid_idx = pin_idx;
1603
1604 err = hdmi_read_pin_conn(codec, pin_idx);
1605 if (err < 0)
1606 return err;
1607
1608 spec->num_pins++;
1609
1610 return 0;
1611 }
1612
1613 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1614 {
1615 struct hdmi_spec *spec = codec->spec;
1616 struct hdmi_spec_per_cvt *per_cvt;
1617 unsigned int chans;
1618 int err;
1619
1620 chans = get_wcaps(codec, cvt_nid);
1621 chans = get_wcaps_channels(chans);
1622
1623 per_cvt = snd_array_new(&spec->cvts);
1624 if (!per_cvt)
1625 return -ENOMEM;
1626
1627 per_cvt->cvt_nid = cvt_nid;
1628 per_cvt->channels_min = 2;
1629 if (chans <= 16) {
1630 per_cvt->channels_max = chans;
1631 if (chans > spec->chmap.channels_max)
1632 spec->chmap.channels_max = chans;
1633 }
1634
1635 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1636 &per_cvt->rates,
1637 &per_cvt->formats,
1638 &per_cvt->maxbps);
1639 if (err < 0)
1640 return err;
1641
1642 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1643 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1644 spec->num_cvts++;
1645
1646 return 0;
1647 }
1648
1649 static int hdmi_parse_codec(struct hda_codec *codec)
1650 {
1651 hda_nid_t nid;
1652 int i, nodes;
1653
1654 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1655 if (!nid || nodes < 0) {
1656 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1657 return -EINVAL;
1658 }
1659
1660 for (i = 0; i < nodes; i++, nid++) {
1661 unsigned int caps;
1662 unsigned int type;
1663
1664 caps = get_wcaps(codec, nid);
1665 type = get_wcaps_type(caps);
1666
1667 if (!(caps & AC_WCAP_DIGITAL))
1668 continue;
1669
1670 switch (type) {
1671 case AC_WID_AUD_OUT:
1672 hdmi_add_cvt(codec, nid);
1673 break;
1674 case AC_WID_PIN:
1675 hdmi_add_pin(codec, nid);
1676 break;
1677 }
1678 }
1679
1680 return 0;
1681 }
1682
1683 /*
1684 */
1685 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1686 {
1687 struct hda_spdif_out *spdif;
1688 bool non_pcm;
1689
1690 mutex_lock(&codec->spdif_mutex);
1691 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1692 /* Add sanity check to pass klockwork check.
1693 * This should never happen.
1694 */
1695 if (WARN_ON(spdif == NULL))
1696 return true;
1697 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1698 mutex_unlock(&codec->spdif_mutex);
1699 return non_pcm;
1700 }
1701
1702 /*
1703 * HDMI callbacks
1704 */
1705
1706 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1707 struct hda_codec *codec,
1708 unsigned int stream_tag,
1709 unsigned int format,
1710 struct snd_pcm_substream *substream)
1711 {
1712 hda_nid_t cvt_nid = hinfo->nid;
1713 struct hdmi_spec *spec = codec->spec;
1714 int pin_idx;
1715 struct hdmi_spec_per_pin *per_pin;
1716 hda_nid_t pin_nid;
1717 struct snd_pcm_runtime *runtime = substream->runtime;
1718 bool non_pcm;
1719 int pinctl;
1720 int err;
1721
1722 mutex_lock(&spec->pcm_lock);
1723 pin_idx = hinfo_to_pin_index(codec, hinfo);
1724 if (spec->dyn_pcm_assign && pin_idx < 0) {
1725 /* when dyn_pcm_assign and pcm is not bound to a pin
1726 * skip pin setup and return 0 to make audio playback
1727 * be ongoing
1728 */
1729 pin_cvt_fixup(codec, NULL, cvt_nid);
1730 snd_hda_codec_setup_stream(codec, cvt_nid,
1731 stream_tag, 0, format);
1732 mutex_unlock(&spec->pcm_lock);
1733 return 0;
1734 }
1735
1736 if (snd_BUG_ON(pin_idx < 0)) {
1737 mutex_unlock(&spec->pcm_lock);
1738 return -EINVAL;
1739 }
1740 per_pin = get_pin(spec, pin_idx);
1741 pin_nid = per_pin->pin_nid;
1742
1743 /* Verify pin:cvt selections to avoid silent audio after S3.
1744 * After S3, the audio driver restores pin:cvt selections
1745 * but this can happen before gfx is ready and such selection
1746 * is overlooked by HW. Thus multiple pins can share a same
1747 * default convertor and mute control will affect each other,
1748 * which can cause a resumed audio playback become silent
1749 * after S3.
1750 */
1751 pin_cvt_fixup(codec, per_pin, 0);
1752
1753 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1754 /* Todo: add DP1.2 MST audio support later */
1755 if (codec_has_acomp(codec))
1756 snd_hdac_sync_audio_rate(&codec->core, pin_nid, runtime->rate);
1757
1758 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1759 mutex_lock(&per_pin->lock);
1760 per_pin->channels = substream->runtime->channels;
1761 per_pin->setup = true;
1762
1763 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1764 mutex_unlock(&per_pin->lock);
1765 if (spec->dyn_pin_out) {
1766 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1767 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1768 snd_hda_codec_write(codec, pin_nid, 0,
1769 AC_VERB_SET_PIN_WIDGET_CONTROL,
1770 pinctl | PIN_OUT);
1771 }
1772
1773 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1774 stream_tag, format);
1775 mutex_unlock(&spec->pcm_lock);
1776 return err;
1777 }
1778
1779 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1780 struct hda_codec *codec,
1781 struct snd_pcm_substream *substream)
1782 {
1783 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1784 return 0;
1785 }
1786
1787 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1788 struct hda_codec *codec,
1789 struct snd_pcm_substream *substream)
1790 {
1791 struct hdmi_spec *spec = codec->spec;
1792 int cvt_idx, pin_idx, pcm_idx;
1793 struct hdmi_spec_per_cvt *per_cvt;
1794 struct hdmi_spec_per_pin *per_pin;
1795 int pinctl;
1796
1797 if (hinfo->nid) {
1798 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1799 if (snd_BUG_ON(pcm_idx < 0))
1800 return -EINVAL;
1801 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1802 if (snd_BUG_ON(cvt_idx < 0))
1803 return -EINVAL;
1804 per_cvt = get_cvt(spec, cvt_idx);
1805
1806 snd_BUG_ON(!per_cvt->assigned);
1807 per_cvt->assigned = 0;
1808 hinfo->nid = 0;
1809
1810 mutex_lock(&spec->pcm_lock);
1811 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1812 clear_bit(pcm_idx, &spec->pcm_in_use);
1813 pin_idx = hinfo_to_pin_index(codec, hinfo);
1814 if (spec->dyn_pcm_assign && pin_idx < 0) {
1815 mutex_unlock(&spec->pcm_lock);
1816 return 0;
1817 }
1818
1819 if (snd_BUG_ON(pin_idx < 0)) {
1820 mutex_unlock(&spec->pcm_lock);
1821 return -EINVAL;
1822 }
1823 per_pin = get_pin(spec, pin_idx);
1824
1825 if (spec->dyn_pin_out) {
1826 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1827 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1828 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1829 AC_VERB_SET_PIN_WIDGET_CONTROL,
1830 pinctl & ~PIN_OUT);
1831 }
1832
1833 mutex_lock(&per_pin->lock);
1834 per_pin->chmap_set = false;
1835 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1836
1837 per_pin->setup = false;
1838 per_pin->channels = 0;
1839 mutex_unlock(&per_pin->lock);
1840 mutex_unlock(&spec->pcm_lock);
1841 }
1842
1843 return 0;
1844 }
1845
1846 static const struct hda_pcm_ops generic_ops = {
1847 .open = hdmi_pcm_open,
1848 .close = hdmi_pcm_close,
1849 .prepare = generic_hdmi_playback_pcm_prepare,
1850 .cleanup = generic_hdmi_playback_pcm_cleanup,
1851 };
1852
1853 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1854 {
1855 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1856 struct hdmi_spec *spec = codec->spec;
1857 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1858
1859 if (!per_pin)
1860 return 0;
1861
1862 return per_pin->sink_eld.info.spk_alloc;
1863 }
1864
1865 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1866 unsigned char *chmap)
1867 {
1868 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1869 struct hdmi_spec *spec = codec->spec;
1870 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1871
1872 /* chmap is already set to 0 in caller */
1873 if (!per_pin)
1874 return;
1875
1876 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1877 }
1878
1879 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1880 unsigned char *chmap, int prepared)
1881 {
1882 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1883 struct hdmi_spec *spec = codec->spec;
1884 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1885
1886 if (!per_pin)
1887 return;
1888 mutex_lock(&per_pin->lock);
1889 per_pin->chmap_set = true;
1890 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1891 if (prepared)
1892 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1893 mutex_unlock(&per_pin->lock);
1894 }
1895
1896 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1897 {
1898 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1899 struct hdmi_spec *spec = codec->spec;
1900 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1901
1902 return per_pin ? true:false;
1903 }
1904
1905 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1906 {
1907 struct hdmi_spec *spec = codec->spec;
1908 int pin_idx;
1909
1910 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1911 struct hda_pcm *info;
1912 struct hda_pcm_stream *pstr;
1913
1914 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1915 if (!info)
1916 return -ENOMEM;
1917
1918 spec->pcm_rec[pin_idx].pcm = info;
1919 spec->pcm_used++;
1920 info->pcm_type = HDA_PCM_TYPE_HDMI;
1921 info->own_chmap = true;
1922
1923 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1924 pstr->substreams = 1;
1925 pstr->ops = generic_ops;
1926 /* other pstr fields are set in open */
1927 }
1928
1929 return 0;
1930 }
1931
1932 static void free_hdmi_jack_priv(struct snd_jack *jack)
1933 {
1934 struct hdmi_pcm *pcm = jack->private_data;
1935
1936 pcm->jack = NULL;
1937 }
1938
1939 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1940 struct hdmi_spec *spec,
1941 int pcm_idx,
1942 const char *name)
1943 {
1944 struct snd_jack *jack;
1945 int err;
1946
1947 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1948 true, false);
1949 if (err < 0)
1950 return err;
1951
1952 spec->pcm_rec[pcm_idx].jack = jack;
1953 jack->private_data = &spec->pcm_rec[pcm_idx];
1954 jack->private_free = free_hdmi_jack_priv;
1955 return 0;
1956 }
1957
1958 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1959 {
1960 char hdmi_str[32] = "HDMI/DP";
1961 struct hdmi_spec *spec = codec->spec;
1962 struct hdmi_spec_per_pin *per_pin;
1963 struct hda_jack_tbl *jack;
1964 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1965 bool phantom_jack;
1966 int ret;
1967
1968 if (pcmdev > 0)
1969 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1970
1971 if (spec->dyn_pcm_assign)
1972 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1973
1974 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1975 /* if !dyn_pcm_assign, it must be non-MST mode.
1976 * This means pcms and pins are statically mapped.
1977 * And pcm_idx is pin_idx.
1978 */
1979 per_pin = get_pin(spec, pcm_idx);
1980 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1981 if (phantom_jack)
1982 strncat(hdmi_str, " Phantom",
1983 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1984 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1985 phantom_jack);
1986 if (ret < 0)
1987 return ret;
1988 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1989 if (jack == NULL)
1990 return 0;
1991 /* assign jack->jack to pcm_rec[].jack to
1992 * align with dyn_pcm_assign mode
1993 */
1994 spec->pcm_rec[pcm_idx].jack = jack->jack;
1995 return 0;
1996 }
1997
1998 static int generic_hdmi_build_controls(struct hda_codec *codec)
1999 {
2000 struct hdmi_spec *spec = codec->spec;
2001 int err;
2002 int pin_idx, pcm_idx;
2003
2004
2005 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2006 err = generic_hdmi_build_jack(codec, pcm_idx);
2007 if (err < 0)
2008 return err;
2009
2010 /* create the spdif for each pcm
2011 * pin will be bound when monitor is connected
2012 */
2013 if (spec->dyn_pcm_assign)
2014 err = snd_hda_create_dig_out_ctls(codec,
2015 0, spec->cvt_nids[0],
2016 HDA_PCM_TYPE_HDMI);
2017 else {
2018 struct hdmi_spec_per_pin *per_pin =
2019 get_pin(spec, pcm_idx);
2020 err = snd_hda_create_dig_out_ctls(codec,
2021 per_pin->pin_nid,
2022 per_pin->mux_nids[0],
2023 HDA_PCM_TYPE_HDMI);
2024 }
2025 if (err < 0)
2026 return err;
2027 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2028
2029 /* add control for ELD Bytes */
2030 err = hdmi_create_eld_ctl(codec, pcm_idx,
2031 get_pcm_rec(spec, pcm_idx)->device);
2032 if (err < 0)
2033 return err;
2034 }
2035
2036 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2037 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2038
2039 hdmi_present_sense(per_pin, 0);
2040 }
2041
2042 /* add channel maps */
2043 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2044 struct hda_pcm *pcm;
2045
2046 pcm = get_pcm_rec(spec, pcm_idx);
2047 if (!pcm || !pcm->pcm)
2048 break;
2049 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2050 if (err < 0)
2051 return err;
2052 }
2053
2054 return 0;
2055 }
2056
2057 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2058 {
2059 struct hdmi_spec *spec = codec->spec;
2060 int pin_idx;
2061
2062 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2063 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2064
2065 per_pin->codec = codec;
2066 mutex_init(&per_pin->lock);
2067 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2068 eld_proc_new(per_pin, pin_idx);
2069 }
2070 return 0;
2071 }
2072
2073 static int generic_hdmi_init(struct hda_codec *codec)
2074 {
2075 struct hdmi_spec *spec = codec->spec;
2076 int pin_idx;
2077
2078 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2079 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2080 hda_nid_t pin_nid = per_pin->pin_nid;
2081
2082 hdmi_init_pin(codec, pin_nid);
2083 if (!codec_has_acomp(codec))
2084 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2085 codec->jackpoll_interval > 0 ?
2086 jack_callback : NULL);
2087 }
2088 return 0;
2089 }
2090
2091 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2092 {
2093 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2094 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2095 }
2096
2097 static void hdmi_array_free(struct hdmi_spec *spec)
2098 {
2099 snd_array_free(&spec->pins);
2100 snd_array_free(&spec->cvts);
2101 }
2102
2103 static void generic_spec_free(struct hda_codec *codec)
2104 {
2105 struct hdmi_spec *spec = codec->spec;
2106
2107 if (spec) {
2108 if (spec->i915_bound)
2109 snd_hdac_i915_exit(&codec->bus->core);
2110 hdmi_array_free(spec);
2111 kfree(spec);
2112 codec->spec = NULL;
2113 }
2114 codec->dp_mst = false;
2115 }
2116
2117 static void generic_hdmi_free(struct hda_codec *codec)
2118 {
2119 struct hdmi_spec *spec = codec->spec;
2120 int pin_idx, pcm_idx;
2121
2122 if (codec_has_acomp(codec))
2123 snd_hdac_i915_register_notifier(NULL);
2124
2125 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2126 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2127 cancel_delayed_work_sync(&per_pin->work);
2128 eld_proc_free(per_pin);
2129 }
2130
2131 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2132 if (spec->pcm_rec[pcm_idx].jack == NULL)
2133 continue;
2134 if (spec->dyn_pcm_assign)
2135 snd_device_free(codec->card,
2136 spec->pcm_rec[pcm_idx].jack);
2137 else
2138 spec->pcm_rec[pcm_idx].jack = NULL;
2139 }
2140
2141 generic_spec_free(codec);
2142 }
2143
2144 #ifdef CONFIG_PM
2145 static int generic_hdmi_resume(struct hda_codec *codec)
2146 {
2147 struct hdmi_spec *spec = codec->spec;
2148 int pin_idx;
2149
2150 codec->patch_ops.init(codec);
2151 regcache_sync(codec->core.regmap);
2152
2153 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2154 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2155 hdmi_present_sense(per_pin, 1);
2156 }
2157 return 0;
2158 }
2159 #endif
2160
2161 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2162 .init = generic_hdmi_init,
2163 .free = generic_hdmi_free,
2164 .build_pcms = generic_hdmi_build_pcms,
2165 .build_controls = generic_hdmi_build_controls,
2166 .unsol_event = hdmi_unsol_event,
2167 #ifdef CONFIG_PM
2168 .resume = generic_hdmi_resume,
2169 #endif
2170 };
2171
2172 static const struct hdmi_ops generic_standard_hdmi_ops = {
2173 .pin_get_eld = snd_hdmi_get_eld,
2174 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2175 .pin_hbr_setup = hdmi_pin_hbr_setup,
2176 .setup_stream = hdmi_setup_stream,
2177 };
2178
2179 /* allocate codec->spec and assign/initialize generic parser ops */
2180 static int alloc_generic_hdmi(struct hda_codec *codec)
2181 {
2182 struct hdmi_spec *spec;
2183
2184 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2185 if (!spec)
2186 return -ENOMEM;
2187
2188 spec->ops = generic_standard_hdmi_ops;
2189 mutex_init(&spec->pcm_lock);
2190 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2191
2192 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2193 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2194 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2195 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2196
2197 codec->spec = spec;
2198 hdmi_array_init(spec, 4);
2199
2200 codec->patch_ops = generic_hdmi_patch_ops;
2201
2202 return 0;
2203 }
2204
2205 /* generic HDMI parser */
2206 static int patch_generic_hdmi(struct hda_codec *codec)
2207 {
2208 int err;
2209
2210 err = alloc_generic_hdmi(codec);
2211 if (err < 0)
2212 return err;
2213
2214 err = hdmi_parse_codec(codec);
2215 if (err < 0) {
2216 generic_spec_free(codec);
2217 return err;
2218 }
2219
2220 generic_hdmi_init_per_pins(codec);
2221 return 0;
2222 }
2223
2224 /*
2225 * Intel codec parsers and helpers
2226 */
2227
2228 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2229 hda_nid_t nid)
2230 {
2231 struct hdmi_spec *spec = codec->spec;
2232 hda_nid_t conns[4];
2233 int nconns;
2234
2235 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2236 if (nconns == spec->num_cvts &&
2237 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2238 return;
2239
2240 /* override pins connection list */
2241 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2242 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2243 }
2244
2245 #define INTEL_VENDOR_NID 0x08
2246 #define INTEL_GET_VENDOR_VERB 0xf81
2247 #define INTEL_SET_VENDOR_VERB 0x781
2248 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2249 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2250
2251 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2252 bool update_tree)
2253 {
2254 unsigned int vendor_param;
2255
2256 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2257 INTEL_GET_VENDOR_VERB, 0);
2258 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2259 return;
2260
2261 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2262 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2263 INTEL_SET_VENDOR_VERB, vendor_param);
2264 if (vendor_param == -1)
2265 return;
2266
2267 if (update_tree)
2268 snd_hda_codec_update_widgets(codec);
2269 }
2270
2271 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2272 {
2273 unsigned int vendor_param;
2274
2275 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2276 INTEL_GET_VENDOR_VERB, 0);
2277 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2278 return;
2279
2280 /* enable DP1.2 mode */
2281 vendor_param |= INTEL_EN_DP12;
2282 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2283 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2284 INTEL_SET_VENDOR_VERB, vendor_param);
2285 }
2286
2287 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2288 * Otherwise you may get severe h/w communication errors.
2289 */
2290 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2291 unsigned int power_state)
2292 {
2293 if (power_state == AC_PWRST_D0) {
2294 intel_haswell_enable_all_pins(codec, false);
2295 intel_haswell_fixup_enable_dp12(codec);
2296 }
2297
2298 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2299 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2300 }
2301
2302 static void intel_pin_eld_notify(void *audio_ptr, int port)
2303 {
2304 struct hda_codec *codec = audio_ptr;
2305 int pin_nid;
2306
2307 /* we assume only from port-B to port-D */
2308 if (port < 1 || port > 3)
2309 return;
2310
2311 switch (codec->core.vendor_id) {
2312 case 0x80860054: /* ILK */
2313 case 0x80862804: /* ILK */
2314 case 0x80862882: /* VLV */
2315 pin_nid = port + 0x03;
2316 break;
2317 default:
2318 pin_nid = port + 0x04;
2319 break;
2320 }
2321
2322 /* skip notification during system suspend (but not in runtime PM);
2323 * the state will be updated at resume
2324 */
2325 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2326 return;
2327 /* ditto during suspend/resume process itself */
2328 if (atomic_read(&(codec)->core.in_pm))
2329 return;
2330
2331 snd_hdac_i915_set_bclk(&codec->bus->core);
2332 check_presence_and_report(codec, pin_nid);
2333 }
2334
2335 /* register i915 component pin_eld_notify callback */
2336 static void register_i915_notifier(struct hda_codec *codec)
2337 {
2338 struct hdmi_spec *spec = codec->spec;
2339
2340 spec->use_acomp_notifier = true;
2341 spec->i915_audio_ops.audio_ptr = codec;
2342 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2343 * will call pin_eld_notify with using audio_ptr pointer
2344 * We need make sure audio_ptr is really setup
2345 */
2346 wmb();
2347 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2348 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2349 }
2350
2351 /* setup_stream ops override for HSW+ */
2352 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2353 hda_nid_t pin_nid, u32 stream_tag, int format)
2354 {
2355 haswell_verify_D0(codec, cvt_nid, pin_nid);
2356 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2357 }
2358
2359 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2360 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2361 struct hdmi_spec_per_pin *per_pin,
2362 hda_nid_t cvt_nid)
2363 {
2364 if (per_pin) {
2365 intel_verify_pin_cvt_connect(codec, per_pin);
2366 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2367 per_pin->mux_idx);
2368 } else {
2369 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2370 }
2371 }
2372
2373 /* Intel Haswell and onwards; audio component with eld notifier */
2374 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2375 {
2376 struct hdmi_spec *spec;
2377 int err;
2378
2379 /* HSW+ requires i915 binding */
2380 if (!codec->bus->core.audio_component) {
2381 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2382 return -ENODEV;
2383 }
2384
2385 err = alloc_generic_hdmi(codec);
2386 if (err < 0)
2387 return err;
2388 spec = codec->spec;
2389
2390 intel_haswell_enable_all_pins(codec, true);
2391 intel_haswell_fixup_enable_dp12(codec);
2392
2393 /* For Haswell/Broadwell, the controller is also in the power well and
2394 * can cover the codec power request, and so need not set this flag.
2395 */
2396 if (!is_haswell(codec) && !is_broadwell(codec))
2397 codec->core.link_power_control = 1;
2398
2399 codec->patch_ops.set_power_state = haswell_set_power_state;
2400 codec->dp_mst = true;
2401 codec->depop_delay = 0;
2402 codec->auto_runtime_pm = 1;
2403
2404 spec->ops.setup_stream = i915_hsw_setup_stream;
2405 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2406
2407 err = hdmi_parse_codec(codec);
2408 if (err < 0) {
2409 generic_spec_free(codec);
2410 return err;
2411 }
2412
2413 generic_hdmi_init_per_pins(codec);
2414 register_i915_notifier(codec);
2415 return 0;
2416 }
2417
2418 /* Intel Baytrail and Braswell; with eld notifier */
2419 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2420 {
2421 struct hdmi_spec *spec;
2422 int err;
2423
2424 /* requires i915 binding */
2425 if (!codec->bus->core.audio_component) {
2426 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2427 return -ENODEV;
2428 }
2429
2430 err = alloc_generic_hdmi(codec);
2431 if (err < 0)
2432 return err;
2433 spec = codec->spec;
2434
2435 /* For Valleyview/Cherryview, only the display codec is in the display
2436 * power well and can use link_power ops to request/release the power.
2437 */
2438 codec->core.link_power_control = 1;
2439
2440 codec->depop_delay = 0;
2441 codec->auto_runtime_pm = 1;
2442
2443 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2444
2445 err = hdmi_parse_codec(codec);
2446 if (err < 0) {
2447 generic_spec_free(codec);
2448 return err;
2449 }
2450
2451 generic_hdmi_init_per_pins(codec);
2452 register_i915_notifier(codec);
2453 return 0;
2454 }
2455
2456 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2457 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2458 {
2459 struct hdmi_spec *spec;
2460 int err;
2461
2462 /* no i915 component should have been bound before this */
2463 if (WARN_ON(codec->bus->core.audio_component))
2464 return -EBUSY;
2465
2466 err = alloc_generic_hdmi(codec);
2467 if (err < 0)
2468 return err;
2469 spec = codec->spec;
2470
2471 /* Try to bind with i915 now */
2472 err = snd_hdac_i915_init(&codec->bus->core);
2473 if (err < 0)
2474 goto error;
2475 spec->i915_bound = true;
2476
2477 err = hdmi_parse_codec(codec);
2478 if (err < 0)
2479 goto error;
2480
2481 generic_hdmi_init_per_pins(codec);
2482 register_i915_notifier(codec);
2483 return 0;
2484
2485 error:
2486 generic_spec_free(codec);
2487 return err;
2488 }
2489
2490 /*
2491 * Shared non-generic implementations
2492 */
2493
2494 static int simple_playback_build_pcms(struct hda_codec *codec)
2495 {
2496 struct hdmi_spec *spec = codec->spec;
2497 struct hda_pcm *info;
2498 unsigned int chans;
2499 struct hda_pcm_stream *pstr;
2500 struct hdmi_spec_per_cvt *per_cvt;
2501
2502 per_cvt = get_cvt(spec, 0);
2503 chans = get_wcaps(codec, per_cvt->cvt_nid);
2504 chans = get_wcaps_channels(chans);
2505
2506 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2507 if (!info)
2508 return -ENOMEM;
2509 spec->pcm_rec[0].pcm = info;
2510 info->pcm_type = HDA_PCM_TYPE_HDMI;
2511 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2512 *pstr = spec->pcm_playback;
2513 pstr->nid = per_cvt->cvt_nid;
2514 if (pstr->channels_max <= 2 && chans && chans <= 16)
2515 pstr->channels_max = chans;
2516
2517 return 0;
2518 }
2519
2520 /* unsolicited event for jack sensing */
2521 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2522 unsigned int res)
2523 {
2524 snd_hda_jack_set_dirty_all(codec);
2525 snd_hda_jack_report_sync(codec);
2526 }
2527
2528 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2529 * as long as spec->pins[] is set correctly
2530 */
2531 #define simple_hdmi_build_jack generic_hdmi_build_jack
2532
2533 static int simple_playback_build_controls(struct hda_codec *codec)
2534 {
2535 struct hdmi_spec *spec = codec->spec;
2536 struct hdmi_spec_per_cvt *per_cvt;
2537 int err;
2538
2539 per_cvt = get_cvt(spec, 0);
2540 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2541 per_cvt->cvt_nid,
2542 HDA_PCM_TYPE_HDMI);
2543 if (err < 0)
2544 return err;
2545 return simple_hdmi_build_jack(codec, 0);
2546 }
2547
2548 static int simple_playback_init(struct hda_codec *codec)
2549 {
2550 struct hdmi_spec *spec = codec->spec;
2551 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2552 hda_nid_t pin = per_pin->pin_nid;
2553
2554 snd_hda_codec_write(codec, pin, 0,
2555 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2556 /* some codecs require to unmute the pin */
2557 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2558 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2559 AMP_OUT_UNMUTE);
2560 snd_hda_jack_detect_enable(codec, pin);
2561 return 0;
2562 }
2563
2564 static void simple_playback_free(struct hda_codec *codec)
2565 {
2566 struct hdmi_spec *spec = codec->spec;
2567
2568 hdmi_array_free(spec);
2569 kfree(spec);
2570 }
2571
2572 /*
2573 * Nvidia specific implementations
2574 */
2575
2576 #define Nv_VERB_SET_Channel_Allocation 0xF79
2577 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2578 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2579 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2580
2581 #define nvhdmi_master_con_nid_7x 0x04
2582 #define nvhdmi_master_pin_nid_7x 0x05
2583
2584 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2585 /*front, rear, clfe, rear_surr */
2586 0x6, 0x8, 0xa, 0xc,
2587 };
2588
2589 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2590 /* set audio protect on */
2591 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2592 /* enable digital output on pin widget */
2593 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2594 {} /* terminator */
2595 };
2596
2597 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2598 /* set audio protect on */
2599 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2600 /* enable digital output on pin widget */
2601 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2602 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2603 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2604 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2605 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2606 {} /* terminator */
2607 };
2608
2609 #ifdef LIMITED_RATE_FMT_SUPPORT
2610 /* support only the safe format and rate */
2611 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2612 #define SUPPORTED_MAXBPS 16
2613 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2614 #else
2615 /* support all rates and formats */
2616 #define SUPPORTED_RATES \
2617 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2618 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2619 SNDRV_PCM_RATE_192000)
2620 #define SUPPORTED_MAXBPS 24
2621 #define SUPPORTED_FORMATS \
2622 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2623 #endif
2624
2625 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2626 {
2627 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2628 return 0;
2629 }
2630
2631 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2632 {
2633 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2634 return 0;
2635 }
2636
2637 static unsigned int channels_2_6_8[] = {
2638 2, 6, 8
2639 };
2640
2641 static unsigned int channels_2_8[] = {
2642 2, 8
2643 };
2644
2645 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2646 .count = ARRAY_SIZE(channels_2_6_8),
2647 .list = channels_2_6_8,
2648 .mask = 0,
2649 };
2650
2651 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2652 .count = ARRAY_SIZE(channels_2_8),
2653 .list = channels_2_8,
2654 .mask = 0,
2655 };
2656
2657 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2658 struct hda_codec *codec,
2659 struct snd_pcm_substream *substream)
2660 {
2661 struct hdmi_spec *spec = codec->spec;
2662 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2663
2664 switch (codec->preset->vendor_id) {
2665 case 0x10de0002:
2666 case 0x10de0003:
2667 case 0x10de0005:
2668 case 0x10de0006:
2669 hw_constraints_channels = &hw_constraints_2_8_channels;
2670 break;
2671 case 0x10de0007:
2672 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2673 break;
2674 default:
2675 break;
2676 }
2677
2678 if (hw_constraints_channels != NULL) {
2679 snd_pcm_hw_constraint_list(substream->runtime, 0,
2680 SNDRV_PCM_HW_PARAM_CHANNELS,
2681 hw_constraints_channels);
2682 } else {
2683 snd_pcm_hw_constraint_step(substream->runtime, 0,
2684 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2685 }
2686
2687 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2688 }
2689
2690 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2691 struct hda_codec *codec,
2692 struct snd_pcm_substream *substream)
2693 {
2694 struct hdmi_spec *spec = codec->spec;
2695 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2696 }
2697
2698 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2699 struct hda_codec *codec,
2700 unsigned int stream_tag,
2701 unsigned int format,
2702 struct snd_pcm_substream *substream)
2703 {
2704 struct hdmi_spec *spec = codec->spec;
2705 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2706 stream_tag, format, substream);
2707 }
2708
2709 static const struct hda_pcm_stream simple_pcm_playback = {
2710 .substreams = 1,
2711 .channels_min = 2,
2712 .channels_max = 2,
2713 .ops = {
2714 .open = simple_playback_pcm_open,
2715 .close = simple_playback_pcm_close,
2716 .prepare = simple_playback_pcm_prepare
2717 },
2718 };
2719
2720 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2721 .build_controls = simple_playback_build_controls,
2722 .build_pcms = simple_playback_build_pcms,
2723 .init = simple_playback_init,
2724 .free = simple_playback_free,
2725 .unsol_event = simple_hdmi_unsol_event,
2726 };
2727
2728 static int patch_simple_hdmi(struct hda_codec *codec,
2729 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2730 {
2731 struct hdmi_spec *spec;
2732 struct hdmi_spec_per_cvt *per_cvt;
2733 struct hdmi_spec_per_pin *per_pin;
2734
2735 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2736 if (!spec)
2737 return -ENOMEM;
2738
2739 codec->spec = spec;
2740 hdmi_array_init(spec, 1);
2741
2742 spec->multiout.num_dacs = 0; /* no analog */
2743 spec->multiout.max_channels = 2;
2744 spec->multiout.dig_out_nid = cvt_nid;
2745 spec->num_cvts = 1;
2746 spec->num_pins = 1;
2747 per_pin = snd_array_new(&spec->pins);
2748 per_cvt = snd_array_new(&spec->cvts);
2749 if (!per_pin || !per_cvt) {
2750 simple_playback_free(codec);
2751 return -ENOMEM;
2752 }
2753 per_cvt->cvt_nid = cvt_nid;
2754 per_pin->pin_nid = pin_nid;
2755 spec->pcm_playback = simple_pcm_playback;
2756
2757 codec->patch_ops = simple_hdmi_patch_ops;
2758
2759 return 0;
2760 }
2761
2762 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2763 int channels)
2764 {
2765 unsigned int chanmask;
2766 int chan = channels ? (channels - 1) : 1;
2767
2768 switch (channels) {
2769 default:
2770 case 0:
2771 case 2:
2772 chanmask = 0x00;
2773 break;
2774 case 4:
2775 chanmask = 0x08;
2776 break;
2777 case 6:
2778 chanmask = 0x0b;
2779 break;
2780 case 8:
2781 chanmask = 0x13;
2782 break;
2783 }
2784
2785 /* Set the audio infoframe channel allocation and checksum fields. The
2786 * channel count is computed implicitly by the hardware. */
2787 snd_hda_codec_write(codec, 0x1, 0,
2788 Nv_VERB_SET_Channel_Allocation, chanmask);
2789
2790 snd_hda_codec_write(codec, 0x1, 0,
2791 Nv_VERB_SET_Info_Frame_Checksum,
2792 (0x71 - chan - chanmask));
2793 }
2794
2795 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2796 struct hda_codec *codec,
2797 struct snd_pcm_substream *substream)
2798 {
2799 struct hdmi_spec *spec = codec->spec;
2800 int i;
2801
2802 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2803 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2804 for (i = 0; i < 4; i++) {
2805 /* set the stream id */
2806 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2807 AC_VERB_SET_CHANNEL_STREAMID, 0);
2808 /* set the stream format */
2809 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2810 AC_VERB_SET_STREAM_FORMAT, 0);
2811 }
2812
2813 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2814 * streams are disabled. */
2815 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2816
2817 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2818 }
2819
2820 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2821 struct hda_codec *codec,
2822 unsigned int stream_tag,
2823 unsigned int format,
2824 struct snd_pcm_substream *substream)
2825 {
2826 int chs;
2827 unsigned int dataDCC2, channel_id;
2828 int i;
2829 struct hdmi_spec *spec = codec->spec;
2830 struct hda_spdif_out *spdif;
2831 struct hdmi_spec_per_cvt *per_cvt;
2832
2833 mutex_lock(&codec->spdif_mutex);
2834 per_cvt = get_cvt(spec, 0);
2835 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2836
2837 chs = substream->runtime->channels;
2838
2839 dataDCC2 = 0x2;
2840
2841 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2842 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2843 snd_hda_codec_write(codec,
2844 nvhdmi_master_con_nid_7x,
2845 0,
2846 AC_VERB_SET_DIGI_CONVERT_1,
2847 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2848
2849 /* set the stream id */
2850 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2851 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2852
2853 /* set the stream format */
2854 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2855 AC_VERB_SET_STREAM_FORMAT, format);
2856
2857 /* turn on again (if needed) */
2858 /* enable and set the channel status audio/data flag */
2859 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2860 snd_hda_codec_write(codec,
2861 nvhdmi_master_con_nid_7x,
2862 0,
2863 AC_VERB_SET_DIGI_CONVERT_1,
2864 spdif->ctls & 0xff);
2865 snd_hda_codec_write(codec,
2866 nvhdmi_master_con_nid_7x,
2867 0,
2868 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2869 }
2870
2871 for (i = 0; i < 4; i++) {
2872 if (chs == 2)
2873 channel_id = 0;
2874 else
2875 channel_id = i * 2;
2876
2877 /* turn off SPDIF once;
2878 *otherwise the IEC958 bits won't be updated
2879 */
2880 if (codec->spdif_status_reset &&
2881 (spdif->ctls & AC_DIG1_ENABLE))
2882 snd_hda_codec_write(codec,
2883 nvhdmi_con_nids_7x[i],
2884 0,
2885 AC_VERB_SET_DIGI_CONVERT_1,
2886 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2887 /* set the stream id */
2888 snd_hda_codec_write(codec,
2889 nvhdmi_con_nids_7x[i],
2890 0,
2891 AC_VERB_SET_CHANNEL_STREAMID,
2892 (stream_tag << 4) | channel_id);
2893 /* set the stream format */
2894 snd_hda_codec_write(codec,
2895 nvhdmi_con_nids_7x[i],
2896 0,
2897 AC_VERB_SET_STREAM_FORMAT,
2898 format);
2899 /* turn on again (if needed) */
2900 /* enable and set the channel status audio/data flag */
2901 if (codec->spdif_status_reset &&
2902 (spdif->ctls & AC_DIG1_ENABLE)) {
2903 snd_hda_codec_write(codec,
2904 nvhdmi_con_nids_7x[i],
2905 0,
2906 AC_VERB_SET_DIGI_CONVERT_1,
2907 spdif->ctls & 0xff);
2908 snd_hda_codec_write(codec,
2909 nvhdmi_con_nids_7x[i],
2910 0,
2911 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2912 }
2913 }
2914
2915 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2916
2917 mutex_unlock(&codec->spdif_mutex);
2918 return 0;
2919 }
2920
2921 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2922 .substreams = 1,
2923 .channels_min = 2,
2924 .channels_max = 8,
2925 .nid = nvhdmi_master_con_nid_7x,
2926 .rates = SUPPORTED_RATES,
2927 .maxbps = SUPPORTED_MAXBPS,
2928 .formats = SUPPORTED_FORMATS,
2929 .ops = {
2930 .open = simple_playback_pcm_open,
2931 .close = nvhdmi_8ch_7x_pcm_close,
2932 .prepare = nvhdmi_8ch_7x_pcm_prepare
2933 },
2934 };
2935
2936 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2937 {
2938 struct hdmi_spec *spec;
2939 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2940 nvhdmi_master_pin_nid_7x);
2941 if (err < 0)
2942 return err;
2943
2944 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2945 /* override the PCM rates, etc, as the codec doesn't give full list */
2946 spec = codec->spec;
2947 spec->pcm_playback.rates = SUPPORTED_RATES;
2948 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2949 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2950 return 0;
2951 }
2952
2953 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2954 {
2955 struct hdmi_spec *spec = codec->spec;
2956 int err = simple_playback_build_pcms(codec);
2957 if (!err) {
2958 struct hda_pcm *info = get_pcm_rec(spec, 0);
2959 info->own_chmap = true;
2960 }
2961 return err;
2962 }
2963
2964 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2965 {
2966 struct hdmi_spec *spec = codec->spec;
2967 struct hda_pcm *info;
2968 struct snd_pcm_chmap *chmap;
2969 int err;
2970
2971 err = simple_playback_build_controls(codec);
2972 if (err < 0)
2973 return err;
2974
2975 /* add channel maps */
2976 info = get_pcm_rec(spec, 0);
2977 err = snd_pcm_add_chmap_ctls(info->pcm,
2978 SNDRV_PCM_STREAM_PLAYBACK,
2979 snd_pcm_alt_chmaps, 8, 0, &chmap);
2980 if (err < 0)
2981 return err;
2982 switch (codec->preset->vendor_id) {
2983 case 0x10de0002:
2984 case 0x10de0003:
2985 case 0x10de0005:
2986 case 0x10de0006:
2987 chmap->channel_mask = (1U << 2) | (1U << 8);
2988 break;
2989 case 0x10de0007:
2990 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2991 }
2992 return 0;
2993 }
2994
2995 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2996 {
2997 struct hdmi_spec *spec;
2998 int err = patch_nvhdmi_2ch(codec);
2999 if (err < 0)
3000 return err;
3001 spec = codec->spec;
3002 spec->multiout.max_channels = 8;
3003 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3004 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3005 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3006 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3007
3008 /* Initialize the audio infoframe channel mask and checksum to something
3009 * valid */
3010 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3011
3012 return 0;
3013 }
3014
3015 /*
3016 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3017 * - 0x10de0015
3018 * - 0x10de0040
3019 */
3020 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3021 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3022 {
3023 if (cap->ca_index == 0x00 && channels == 2)
3024 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3025
3026 /* If the speaker allocation matches the channel count, it is OK. */
3027 if (cap->channels != channels)
3028 return -1;
3029
3030 /* all channels are remappable freely */
3031 return SNDRV_CTL_TLVT_CHMAP_VAR;
3032 }
3033
3034 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3035 int ca, int chs, unsigned char *map)
3036 {
3037 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3038 return -EINVAL;
3039
3040 return 0;
3041 }
3042
3043 static int patch_nvhdmi(struct hda_codec *codec)
3044 {
3045 struct hdmi_spec *spec;
3046 int err;
3047
3048 err = patch_generic_hdmi(codec);
3049 if (err)
3050 return err;
3051
3052 spec = codec->spec;
3053 spec->dyn_pin_out = true;
3054
3055 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3056 nvhdmi_chmap_cea_alloc_validate_get_type;
3057 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3058
3059 return 0;
3060 }
3061
3062 /*
3063 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3064 * accessed using vendor-defined verbs. These registers can be used for
3065 * interoperability between the HDA and HDMI drivers.
3066 */
3067
3068 /* Audio Function Group node */
3069 #define NVIDIA_AFG_NID 0x01
3070
3071 /*
3072 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3073 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3074 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3075 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3076 * additional bit (at position 30) to signal the validity of the format.
3077 *
3078 * | 31 | 30 | 29 16 | 15 0 |
3079 * +---------+-------+--------+--------+
3080 * | TRIGGER | VALID | UNUSED | FORMAT |
3081 * +-----------------------------------|
3082 *
3083 * Note that for the trigger bit to take effect it needs to change value
3084 * (i.e. it needs to be toggled).
3085 */
3086 #define NVIDIA_GET_SCRATCH0 0xfa6
3087 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3088 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3089 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3090 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3091 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3092 #define NVIDIA_SCRATCH_VALID (1 << 6)
3093
3094 #define NVIDIA_GET_SCRATCH1 0xfab
3095 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3096 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3097 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3098 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3099
3100 /*
3101 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3102 * the format is invalidated so that the HDMI codec can be disabled.
3103 */
3104 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3105 {
3106 unsigned int value;
3107
3108 /* bits [31:30] contain the trigger and valid bits */
3109 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3110 NVIDIA_GET_SCRATCH0, 0);
3111 value = (value >> 24) & 0xff;
3112
3113 /* bits [15:0] are used to store the HDA format */
3114 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3115 NVIDIA_SET_SCRATCH0_BYTE0,
3116 (format >> 0) & 0xff);
3117 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3118 NVIDIA_SET_SCRATCH0_BYTE1,
3119 (format >> 8) & 0xff);
3120
3121 /* bits [16:24] are unused */
3122 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3123 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3124
3125 /*
3126 * Bit 30 signals that the data is valid and hence that HDMI audio can
3127 * be enabled.
3128 */
3129 if (format == 0)
3130 value &= ~NVIDIA_SCRATCH_VALID;
3131 else
3132 value |= NVIDIA_SCRATCH_VALID;
3133
3134 /*
3135 * Whenever the trigger bit is toggled, an interrupt is raised in the
3136 * HDMI codec. The HDMI driver will use that as trigger to update its
3137 * configuration.
3138 */
3139 value ^= NVIDIA_SCRATCH_TRIGGER;
3140
3141 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3142 NVIDIA_SET_SCRATCH0_BYTE3, value);
3143 }
3144
3145 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3146 struct hda_codec *codec,
3147 unsigned int stream_tag,
3148 unsigned int format,
3149 struct snd_pcm_substream *substream)
3150 {
3151 int err;
3152
3153 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3154 format, substream);
3155 if (err < 0)
3156 return err;
3157
3158 /* notify the HDMI codec of the format change */
3159 tegra_hdmi_set_format(codec, format);
3160
3161 return 0;
3162 }
3163
3164 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3165 struct hda_codec *codec,
3166 struct snd_pcm_substream *substream)
3167 {
3168 /* invalidate the format in the HDMI codec */
3169 tegra_hdmi_set_format(codec, 0);
3170
3171 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3172 }
3173
3174 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3175 {
3176 struct hdmi_spec *spec = codec->spec;
3177 unsigned int i;
3178
3179 for (i = 0; i < spec->num_pins; i++) {
3180 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3181
3182 if (pcm->pcm_type == type)
3183 return pcm;
3184 }
3185
3186 return NULL;
3187 }
3188
3189 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3190 {
3191 struct hda_pcm_stream *stream;
3192 struct hda_pcm *pcm;
3193 int err;
3194
3195 err = generic_hdmi_build_pcms(codec);
3196 if (err < 0)
3197 return err;
3198
3199 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3200 if (!pcm)
3201 return -ENODEV;
3202
3203 /*
3204 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3205 * codec about format changes.
3206 */
3207 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3208 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3209 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3210
3211 return 0;
3212 }
3213
3214 static int patch_tegra_hdmi(struct hda_codec *codec)
3215 {
3216 int err;
3217
3218 err = patch_generic_hdmi(codec);
3219 if (err)
3220 return err;
3221
3222 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3223
3224 return 0;
3225 }
3226
3227 /*
3228 * ATI/AMD-specific implementations
3229 */
3230
3231 #define is_amdhdmi_rev3_or_later(codec) \
3232 ((codec)->core.vendor_id == 0x1002aa01 && \
3233 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3234 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3235
3236 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3237 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3238 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3239 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3240 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3241 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3242 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3243 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3244 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3245 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3246 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3247 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3248 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3249 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3250 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3251 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3252 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3253 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3254 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3255 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3256 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3257 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3258 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3259 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3260 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3261
3262 /* AMD specific HDA cvt verbs */
3263 #define ATI_VERB_SET_RAMP_RATE 0x770
3264 #define ATI_VERB_GET_RAMP_RATE 0xf70
3265
3266 #define ATI_OUT_ENABLE 0x1
3267
3268 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3269 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3270
3271 #define ATI_HBR_CAPABLE 0x01
3272 #define ATI_HBR_ENABLE 0x10
3273
3274 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3275 unsigned char *buf, int *eld_size)
3276 {
3277 /* call hda_eld.c ATI/AMD-specific function */
3278 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3279 is_amdhdmi_rev3_or_later(codec));
3280 }
3281
3282 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3283 int active_channels, int conn_type)
3284 {
3285 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3286 }
3287
3288 static int atihdmi_paired_swap_fc_lfe(int pos)
3289 {
3290 /*
3291 * ATI/AMD have automatic FC/LFE swap built-in
3292 * when in pairwise mapping mode.
3293 */
3294
3295 switch (pos) {
3296 /* see channel_allocations[].speakers[] */
3297 case 2: return 3;
3298 case 3: return 2;
3299 default: break;
3300 }
3301
3302 return pos;
3303 }
3304
3305 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3306 int ca, int chs, unsigned char *map)
3307 {
3308 struct hdac_cea_channel_speaker_allocation *cap;
3309 int i, j;
3310
3311 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3312
3313 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3314 for (i = 0; i < chs; ++i) {
3315 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3316 bool ok = false;
3317 bool companion_ok = false;
3318
3319 if (!mask)
3320 continue;
3321
3322 for (j = 0 + i % 2; j < 8; j += 2) {
3323 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3324 if (cap->speakers[chan_idx] == mask) {
3325 /* channel is in a supported position */
3326 ok = true;
3327
3328 if (i % 2 == 0 && i + 1 < chs) {
3329 /* even channel, check the odd companion */
3330 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3331 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3332 int comp_mask_act = cap->speakers[comp_chan_idx];
3333
3334 if (comp_mask_req == comp_mask_act)
3335 companion_ok = true;
3336 else
3337 return -EINVAL;
3338 }
3339 break;
3340 }
3341 }
3342
3343 if (!ok)
3344 return -EINVAL;
3345
3346 if (companion_ok)
3347 i++; /* companion channel already checked */
3348 }
3349
3350 return 0;
3351 }
3352
3353 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3354 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3355 {
3356 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3357 int verb;
3358 int ati_channel_setup = 0;
3359
3360 if (hdmi_slot > 7)
3361 return -EINVAL;
3362
3363 if (!has_amd_full_remap_support(codec)) {
3364 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3365
3366 /* In case this is an odd slot but without stream channel, do not
3367 * disable the slot since the corresponding even slot could have a
3368 * channel. In case neither have a channel, the slot pair will be
3369 * disabled when this function is called for the even slot. */
3370 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3371 return 0;
3372
3373 hdmi_slot -= hdmi_slot % 2;
3374
3375 if (stream_channel != 0xf)
3376 stream_channel -= stream_channel % 2;
3377 }
3378
3379 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3380
3381 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3382
3383 if (stream_channel != 0xf)
3384 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3385
3386 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3387 }
3388
3389 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3390 hda_nid_t pin_nid, int asp_slot)
3391 {
3392 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3393 bool was_odd = false;
3394 int ati_asp_slot = asp_slot;
3395 int verb;
3396 int ati_channel_setup;
3397
3398 if (asp_slot > 7)
3399 return -EINVAL;
3400
3401 if (!has_amd_full_remap_support(codec)) {
3402 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3403 if (ati_asp_slot % 2 != 0) {
3404 ati_asp_slot -= 1;
3405 was_odd = true;
3406 }
3407 }
3408
3409 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3410
3411 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3412
3413 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3414 return 0xf;
3415
3416 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3417 }
3418
3419 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3420 struct hdac_chmap *chmap,
3421 struct hdac_cea_channel_speaker_allocation *cap,
3422 int channels)
3423 {
3424 int c;
3425
3426 /*
3427 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3428 * we need to take that into account (a single channel may take 2
3429 * channel slots if we need to carry a silent channel next to it).
3430 * On Rev3+ AMD codecs this function is not used.
3431 */
3432 int chanpairs = 0;
3433
3434 /* We only produce even-numbered channel count TLVs */
3435 if ((channels % 2) != 0)
3436 return -1;
3437
3438 for (c = 0; c < 7; c += 2) {
3439 if (cap->speakers[c] || cap->speakers[c+1])
3440 chanpairs++;
3441 }
3442
3443 if (chanpairs * 2 != channels)
3444 return -1;
3445
3446 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3447 }
3448
3449 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3450 struct hdac_cea_channel_speaker_allocation *cap,
3451 unsigned int *chmap, int channels)
3452 {
3453 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3454 int count = 0;
3455 int c;
3456
3457 for (c = 7; c >= 0; c--) {
3458 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3459 int spk = cap->speakers[chan];
3460 if (!spk) {
3461 /* add N/A channel if the companion channel is occupied */
3462 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3463 chmap[count++] = SNDRV_CHMAP_NA;
3464
3465 continue;
3466 }
3467
3468 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3469 }
3470
3471 WARN_ON(count != channels);
3472 }
3473
3474 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3475 bool hbr)
3476 {
3477 int hbr_ctl, hbr_ctl_new;
3478
3479 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3480 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3481 if (hbr)
3482 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3483 else
3484 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3485
3486 codec_dbg(codec,
3487 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3488 pin_nid,
3489 hbr_ctl == hbr_ctl_new ? "" : "new-",
3490 hbr_ctl_new);
3491
3492 if (hbr_ctl != hbr_ctl_new)
3493 snd_hda_codec_write(codec, pin_nid, 0,
3494 ATI_VERB_SET_HBR_CONTROL,
3495 hbr_ctl_new);
3496
3497 } else if (hbr)
3498 return -EINVAL;
3499
3500 return 0;
3501 }
3502
3503 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3504 hda_nid_t pin_nid, u32 stream_tag, int format)
3505 {
3506
3507 if (is_amdhdmi_rev3_or_later(codec)) {
3508 int ramp_rate = 180; /* default as per AMD spec */
3509 /* disable ramp-up/down for non-pcm as per AMD spec */
3510 if (format & AC_FMT_TYPE_NON_PCM)
3511 ramp_rate = 0;
3512
3513 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3514 }
3515
3516 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3517 }
3518
3519
3520 static int atihdmi_init(struct hda_codec *codec)
3521 {
3522 struct hdmi_spec *spec = codec->spec;
3523 int pin_idx, err;
3524
3525 err = generic_hdmi_init(codec);
3526
3527 if (err)
3528 return err;
3529
3530 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3531 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3532
3533 /* make sure downmix information in infoframe is zero */
3534 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3535
3536 /* enable channel-wise remap mode if supported */
3537 if (has_amd_full_remap_support(codec))
3538 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3539 ATI_VERB_SET_MULTICHANNEL_MODE,
3540 ATI_MULTICHANNEL_MODE_SINGLE);
3541 }
3542
3543 return 0;
3544 }
3545
3546 static int patch_atihdmi(struct hda_codec *codec)
3547 {
3548 struct hdmi_spec *spec;
3549 struct hdmi_spec_per_cvt *per_cvt;
3550 int err, cvt_idx;
3551
3552 err = patch_generic_hdmi(codec);
3553
3554 if (err)
3555 return err;
3556
3557 codec->patch_ops.init = atihdmi_init;
3558
3559 spec = codec->spec;
3560
3561 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3562 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3563 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3564 spec->ops.setup_stream = atihdmi_setup_stream;
3565
3566 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3567 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3568
3569 if (!has_amd_full_remap_support(codec)) {
3570 /* override to ATI/AMD-specific versions with pairwise mapping */
3571 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3572 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3573 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3574 atihdmi_paired_cea_alloc_to_tlv_chmap;
3575 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3576 }
3577
3578 /* ATI/AMD converters do not advertise all of their capabilities */
3579 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3580 per_cvt = get_cvt(spec, cvt_idx);
3581 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3582 per_cvt->rates |= SUPPORTED_RATES;
3583 per_cvt->formats |= SUPPORTED_FORMATS;
3584 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3585 }
3586
3587 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3588
3589 return 0;
3590 }
3591
3592 /* VIA HDMI Implementation */
3593 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3594 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3595
3596 static int patch_via_hdmi(struct hda_codec *codec)
3597 {
3598 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3599 }
3600
3601 /*
3602 * patch entries
3603 */
3604 static const struct hda_device_id snd_hda_id_hdmi[] = {
3605 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3606 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3607 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3608 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3609 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3610 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3611 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3612 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3613 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3614 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3615 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3616 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3617 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3618 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3619 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3620 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3621 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3622 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3623 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3624 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3625 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3626 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3627 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3628 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3629 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3630 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3631 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3632 /* 17 is known to be absent */
3633 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3634 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3635 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3636 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3637 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3638 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3639 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3640 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3641 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3642 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3643 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3644 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3645 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3646 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3647 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3648 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3649 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3650 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3651 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3652 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3653 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3654 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3655 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3656 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3657 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3658 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3659 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3660 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3661 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3662 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3663 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3664 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3665 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3666 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3667 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3668 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3669 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3670 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3671 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3672 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3673 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3674 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3675 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3676 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3677 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3678 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3679 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3680 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3681 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3682 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3683 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3684 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3685 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3686 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3687 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3688 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3689 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3690 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3691 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3692 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3693 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3694 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3695 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3696 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3697 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_hsw_hdmi),
3698 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3699 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3700 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3701 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3702 /* special ID for generic HDMI */
3703 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3704 {} /* terminator */
3705 };
3706 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3707
3708 MODULE_LICENSE("GPL");
3709 MODULE_DESCRIPTION("HDMI HD-audio codec");
3710 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3711 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3712 MODULE_ALIAS("snd-hda-codec-atihdmi");
3713
3714 static struct hda_codec_driver hdmi_driver = {
3715 .id = snd_hda_id_hdmi,
3716 };
3717
3718 module_hda_codec_driver(hdmi_driver);
Linux with added FPC-III support