arch/arm/include/asm/io.h

   1 /*
   2  *  arch/arm/include/asm/io.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Modifications:
  11  *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12  *                      constant addresses and variable addresses.
  13  *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14  *                      specific IO header files.
  15  *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16  *  04-Apr-1999 PJB     Added check_signature.
  17  *  12-Dec-1999 RMK     More cleanups
  18  *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20  */
  21 #ifndef __ASM_ARM_IO_H
  22 #define __ASM_ARM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <linux/blk_types.h>
  28 #include <asm/byteorder.h>
  29 #include <asm/memory.h>
  30 #include <asm-generic/pci_iomap.h>
  31 #include <xen/xen.h>
  32
  33 /*
  34  * ISA I/O bus memory addresses are 1:1 with the physical address.
  35  */
  36 #define isa_virt_to_bus virt_to_phys
  37 #define isa_page_to_bus page_to_phys
  38 #define isa_bus_to_virt phys_to_virt
  39
  40 /*
  41  * Atomic MMIO-wide IO modify
  42  */
  43 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
  44 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
  45
  46 /*
  47  * Generic IO read/write.  These perform native-endian accesses.  Note
  48  * that some architectures will want to re-define __raw_{read,write}w.
  49  */
  50 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  51 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  52 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  53
  54 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  55 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  56 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  57
  58 #if __LINUX_ARM_ARCH__ < 6
  59 /*
  60  * Half-word accesses are problematic with RiscPC due to limitations of
  61  * the bus. Rather than special-case the machine, just let the compiler
  62  * generate the access for CPUs prior to ARMv6.
  63  */
  64 #define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  65 #define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
  66 #else
  67 /*
  68  * When running under a hypervisor, we want to avoid I/O accesses with
  69  * writeback addressing modes as these incur a significant performance
  70  * overhead (the address generation must be emulated in software).
  71  */
  72 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  73 {
  74         asm volatile("strh %1, %0"
  75                      : "+Q" (*(volatile u16 __force *)addr)
  76                      : "r" (val));
  77 }
  78
  79 static inline u16 __raw_readw(const volatile void __iomem *addr)
  80 {
  81         u16 val;
  82         asm volatile("ldrh %1, %0"
  83                      : "+Q" (*(volatile u16 __force *)addr),
  84                        "=r" (val));
  85         return val;
  86 }
  87 #endif
  88
  89 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  90 {
  91         asm volatile("strb %1, %0"
  92                      : "+Qo" (*(volatile u8 __force *)addr)
  93                      : "r" (val));
  94 }
  95
  96 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  97 {
  98         asm volatile("str %1, %0"
  99                      : "+Qo" (*(volatile u32 __force *)addr)
 100                      : "r" (val));
 101 }
 102
 103 static inline u8 __raw_readb(const volatile void __iomem *addr)
 104 {
 105         u8 val;
 106         asm volatile("ldrb %1, %0"
 107                      : "+Qo" (*(volatile u8 __force *)addr),
 108                        "=r" (val));
 109         return val;
 110 }
 111
 112 static inline u32 __raw_readl(const volatile void __iomem *addr)
 113 {
 114         u32 val;
 115         asm volatile("ldr %1, %0"
 116                      : "+Qo" (*(volatile u32 __force *)addr),
 117                        "=r" (val));
 118         return val;
 119 }
 120
 121 /*
 122  * Architecture ioremap implementation.
 123  */
 124 #define MT_DEVICE               0
 125 #define MT_DEVICE_NONSHARED     1
 126 #define MT_DEVICE_CACHED        2
 127 #define MT_DEVICE_WC            3
 128 /*
 129  * types 4 onwards can be found in asm/mach/map.h and are undefined
 130  * for ioremap
 131  */
 132
 133 /*
 134  * __arm_ioremap takes CPU physical address.
 135  * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
 136  * The _caller variety takes a __builtin_return_address(0) value for
 137  * /proc/vmalloc to use - and should only be used in non-inline functions.
 138  */
 139 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
 140         size_t, unsigned int, void *);
 141 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
 142         void *);
 143
 144 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
 145 extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
 146 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 147 extern void __iounmap(volatile void __iomem *addr);
 148 extern void __arm_iounmap(volatile void __iomem *addr);
 149
 150 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
 151         unsigned int, void *);
 152 extern void (*arch_iounmap)(volatile void __iomem *);
 153
 154 /*
 155  * Bad read/write accesses...
 156  */
 157 extern void __readwrite_bug(const char *fn);
 158
 159 /*
 160  * A typesafe __io() helper
 161  */
 162 static inline void __iomem *__typesafe_io(unsigned long addr)
 163 {
 164         return (void __iomem *)addr;
 165 }
 166
 167 #define IOMEM(x)        ((void __force __iomem *)(x))
 168
 169 /* IO barriers */
 170 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 171 #include <asm/barrier.h>
 172 #define __iormb()               rmb()
 173 #define __iowmb()               wmb()
 174 #else
 175 #define __iormb()               do { } while (0)
 176 #define __iowmb()               do { } while (0)
 177 #endif
 178
 179 /* PCI fixed i/o mapping */
 180 #define PCI_IO_VIRT_BASE        0xfee00000
 181
 182 #if defined(CONFIG_PCI)
 183 void pci_ioremap_set_mem_type(int mem_type);
 184 #else
 185 static inline void pci_ioremap_set_mem_type(int mem_type) {}
 186 #endif
 187
 188 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
 189
 190 /*
 191  * Now, pick up the machine-defined IO definitions
 192  */
 193 #ifdef CONFIG_NEED_MACH_IO_H
 194 #include <mach/io.h>
 195 #elif defined(CONFIG_PCI)
 196 #define IO_SPACE_LIMIT  ((resource_size_t)0xfffff)
 197 #define __io(a)         __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 198 #else
 199 #define __io(a)         __typesafe_io((a) & IO_SPACE_LIMIT)
 200 #endif
 201
 202 /*
 203  * This is the limit of PC card/PCI/ISA IO space, which is by default
 204  * 64K if we have PC card, PCI or ISA support.  Otherwise, default to
 205  * zero to prevent ISA/PCI drivers claiming IO space (and potentially
 206  * oopsing.)
 207  *
 208  * Only set this larger if you really need inb() et.al. to operate over
 209  * a larger address space.  Note that SOC_COMMON ioremaps each sockets
 210  * IO space area, and so inb() et.al. must be defined to operate as per
 211  * readb() et.al. on such platforms.
 212  */
 213 #ifndef IO_SPACE_LIMIT
 214 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
 215 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
 216 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
 217 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
 218 #else
 219 #define IO_SPACE_LIMIT ((resource_size_t)0)
 220 #endif
 221 #endif
 222
 223 /*
 224  *  IO port access primitives
 225  *  -------------------------
 226  *
 227  * The ARM doesn't have special IO access instructions; all IO is memory
 228  * mapped.  Note that these are defined to perform little endian accesses
 229  * only.  Their primary purpose is to access PCI and ISA peripherals.
 230  *
 231  * Note that for a big endian machine, this implies that the following
 232  * big endian mode connectivity is in place, as described by numerous
 233  * ARM documents:
 234  *
 235  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
 236  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 237  *
 238  * The machine specific io.h include defines __io to translate an "IO"
 239  * address to a memory address.
 240  *
 241  * Note that we prevent GCC re-ordering or caching values in expressions
 242  * by introducing sequence points into the in*() definitions.  Note that
 243  * __raw_* do not guarantee this behaviour.
 244  *
 245  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 246  */
 247 #ifdef __io
 248 #define outb(v,p)       ({ __iowmb(); __raw_writeb(v,__io(p)); })
 249 #define outw(v,p)       ({ __iowmb(); __raw_writew((__force __u16) \
 250                                         cpu_to_le16(v),__io(p)); })
 251 #define outl(v,p)       ({ __iowmb(); __raw_writel((__force __u32) \
 252                                         cpu_to_le32(v),__io(p)); })
 253
 254 #define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
 255 #define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 256                         __raw_readw(__io(p))); __iormb(); __v; })
 257 #define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 258                         __raw_readl(__io(p))); __iormb(); __v; })
 259
 260 #define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 261 #define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 262 #define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 263
 264 #define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 265 #define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 266 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 267 #endif
 268
 269 #define outb_p(val,port)        outb((val),(port))
 270 #define outw_p(val,port)        outw((val),(port))
 271 #define outl_p(val,port)        outl((val),(port))
 272 #define inb_p(port)             inb((port))
 273 #define inw_p(port)             inw((port))
 274 #define inl_p(port)             inl((port))
 275
 276 #define outsb_p(port,from,len)  outsb(port,from,len)
 277 #define outsw_p(port,from,len)  outsw(port,from,len)
 278 #define outsl_p(port,from,len)  outsl(port,from,len)
 279 #define insb_p(port,to,len)     insb(port,to,len)
 280 #define insw_p(port,to,len)     insw(port,to,len)
 281 #define insl_p(port,to,len)     insl(port,to,len)
 282
 283 /*
 284  * String version of IO memory access ops:
 285  */
 286 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 287 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 288 extern void _memset_io(volatile void __iomem *, int, size_t);
 289
 290 #define mmiowb()
 291
 292 /*
 293  *  Memory access primitives
 294  *  ------------------------
 295  *
 296  * These perform PCI memory accesses via an ioremap region.  They don't
 297  * take an address as such, but a cookie.
 298  *
 299  * Again, this are defined to perform little endian accesses.  See the
 300  * IO port primitives for more information.
 301  */
 302 #ifndef readl
 303 #define readb_relaxed(c) ({ u8  __r = __raw_readb(c); __r; })
 304 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 305                                         __raw_readw(c)); __r; })
 306 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 307                                         __raw_readl(c)); __r; })
 308
 309 #define writeb_relaxed(v,c)     __raw_writeb(v,c)
 310 #define writew_relaxed(v,c)     __raw_writew((__force u16) cpu_to_le16(v),c)
 311 #define writel_relaxed(v,c)     __raw_writel((__force u32) cpu_to_le32(v),c)
 312
 313 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 314 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 315 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 316
 317 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 318 #define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 319 #define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 320
 321 #define readsb(p,d,l)           __raw_readsb(p,d,l)
 322 #define readsw(p,d,l)           __raw_readsw(p,d,l)
 323 #define readsl(p,d,l)           __raw_readsl(p,d,l)
 324
 325 #define writesb(p,d,l)          __raw_writesb(p,d,l)
 326 #define writesw(p,d,l)          __raw_writesw(p,d,l)
 327 #define writesl(p,d,l)          __raw_writesl(p,d,l)
 328
 329 #define memset_io(c,v,l)        _memset_io(c,(v),(l))
 330 #define memcpy_fromio(a,c,l)    _memcpy_fromio((a),c,(l))
 331 #define memcpy_toio(c,a,l)      _memcpy_toio(c,(a),(l))
 332
 333 #endif  /* readl */
 334
 335 /*
 336  * ioremap and friends.
 337  *
 338  * ioremap takes a PCI memory address, as specified in
 339  * Documentation/io-mapping.txt.
 340  *
 341  */
 342 #define ioremap(cookie,size)            __arm_ioremap((cookie), (size), MT_DEVICE)
 343 #define ioremap_nocache(cookie,size)    __arm_ioremap((cookie), (size), MT_DEVICE)
 344 #define ioremap_cache(cookie,size)      __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
 345 #define ioremap_wc(cookie,size)         __arm_ioremap((cookie), (size), MT_DEVICE_WC)
 346 #define iounmap                         __arm_iounmap
 347
 348 /*
 349  * io{read,write}{8,16,32} macros
 350  */
 351 #ifndef ioread8
 352 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
 353 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
 354 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
 355
 356 #define ioread16be(p)   ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
 357 #define ioread32be(p)   ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
 358
 359 #define iowrite8(v,p)   ({ __iowmb(); __raw_writeb(v, p); })
 360 #define iowrite16(v,p)  ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
 361 #define iowrite32(v,p)  ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
 362
 363 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
 364 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 365
 366 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 367 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 368 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 369
 370 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 371 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 372 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 373
 374 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 375 extern void ioport_unmap(void __iomem *addr);
 376 #endif
 377
 378 struct pci_dev;
 379
 380 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 381
 382 /*
 383  * can the hardware map this into one segment or not, given no other
 384  * constraints.
 385  */
 386 #define BIOVEC_MERGEABLE(vec1, vec2)    \
 387         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 388
 389 struct bio_vec;
 390 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 391                                       const struct bio_vec *vec2);
 392 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 393         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 394          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 395
 396 #ifdef CONFIG_MMU
 397 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 398 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 399 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 400 extern int devmem_is_allowed(unsigned long pfn);
 401 #endif
 402
 403 /*
 404  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 405  * access
 406  */
 407 #define xlate_dev_mem_ptr(p)    __va(p)
 408
 409 /*
 410  * Convert a virtual cached pointer to an uncached pointer
 411  */
 412 #define xlate_dev_kmem_ptr(p)   p
 413
 414 /*
 415  * Register ISA memory and port locations for glibc iopl/inb/outb
 416  * emulation.
 417  */
 418 extern void register_isa_ports(unsigned int mmio, unsigned int io,
 419                                unsigned int io_shift);
 420
 421 #endif  /* __KERNEL__ */
 422 #endif  /* __ASM_ARM_IO_H */