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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / crypto / omap-sham.c
blobff6ac4e824b5eeb7ef0a84ce8c3e40d840ad107a
1 /*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * Some ideas are from old omap-sha1-md5.c driver.
15 */
16
17 #define pr_fmt(fmt) "%s: " fmt, __func__
18
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
27 #include <linux/io.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/internal/hash.h>
45
46 #define MD5_DIGEST_SIZE 16
47
48 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
49 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
50 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
51
52 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
53
54 #define SHA_REG_CTRL 0x18
55 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
56 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
57 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
58 #define SHA_REG_CTRL_ALGO (1 << 2)
59 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
60 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
61
62 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
63
64 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
65 #define SHA_REG_MASK_DMA_EN (1 << 3)
66 #define SHA_REG_MASK_IT_EN (1 << 2)
67 #define SHA_REG_MASK_SOFTRESET (1 << 1)
68 #define SHA_REG_AUTOIDLE (1 << 0)
69
70 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
71 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
72
73 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
74 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
75 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
76 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
77 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
78
79 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
80 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
81 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
85 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
86
87 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
88
89 #define SHA_REG_IRQSTATUS 0x118
90 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
92 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
94
95 #define SHA_REG_IRQENA 0x11C
96 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
97 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
98 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
99 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
100
101 #define DEFAULT_TIMEOUT_INTERVAL HZ
102
103 #define DEFAULT_AUTOSUSPEND_DELAY 1000
104
105 /* mostly device flags */
106 #define FLAGS_BUSY 0
107 #define FLAGS_FINAL 1
108 #define FLAGS_DMA_ACTIVE 2
109 #define FLAGS_OUTPUT_READY 3
110 #define FLAGS_INIT 4
111 #define FLAGS_CPU 5
112 #define FLAGS_DMA_READY 6
113 #define FLAGS_AUTO_XOR 7
114 #define FLAGS_BE32_SHA1 8
115 #define FLAGS_SGS_COPIED 9
116 #define FLAGS_SGS_ALLOCED 10
117 /* context flags */
118 #define FLAGS_FINUP 16
119
120 #define FLAGS_MODE_SHIFT 18
121 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
128
129 #define FLAGS_HMAC 21
130 #define FLAGS_ERROR 22
131
132 #define OP_UPDATE 1
133 #define OP_FINAL 2
134
135 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
136 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
137
138 #define BUFLEN SHA512_BLOCK_SIZE
139 #define OMAP_SHA_DMA_THRESHOLD 256
140
141 struct omap_sham_dev;
142
143 struct omap_sham_reqctx {
144 struct omap_sham_dev *dd;
145 unsigned long flags;
146 unsigned long op;
147
148 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
149 size_t digcnt;
150 size_t bufcnt;
151 size_t buflen;
152
153 /* walk state */
154 struct scatterlist *sg;
155 struct scatterlist sgl[2];
156 int offset; /* offset in current sg */
157 int sg_len;
158 unsigned int total; /* total request */
159
160 u8 buffer[0] OMAP_ALIGNED;
161 };
162
163 struct omap_sham_hmac_ctx {
164 struct crypto_shash *shash;
165 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
166 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 };
168
169 struct omap_sham_ctx {
170 struct omap_sham_dev *dd;
171
172 unsigned long flags;
173
174 /* fallback stuff */
175 struct crypto_shash *fallback;
176
177 struct omap_sham_hmac_ctx base[0];
178 };
179
180 #define OMAP_SHAM_QUEUE_LENGTH 10
181
182 struct omap_sham_algs_info {
183 struct ahash_alg *algs_list;
184 unsigned int size;
185 unsigned int registered;
186 };
187
188 struct omap_sham_pdata {
189 struct omap_sham_algs_info *algs_info;
190 unsigned int algs_info_size;
191 unsigned long flags;
192 int digest_size;
193
194 void (*copy_hash)(struct ahash_request *req, int out);
195 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
196 int final, int dma);
197 void (*trigger)(struct omap_sham_dev *dd, size_t length);
198 int (*poll_irq)(struct omap_sham_dev *dd);
199 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
200
201 u32 odigest_ofs;
202 u32 idigest_ofs;
203 u32 din_ofs;
204 u32 digcnt_ofs;
205 u32 rev_ofs;
206 u32 mask_ofs;
207 u32 sysstatus_ofs;
208 u32 mode_ofs;
209 u32 length_ofs;
210
211 u32 major_mask;
212 u32 major_shift;
213 u32 minor_mask;
214 u32 minor_shift;
215 };
216
217 struct omap_sham_dev {
218 struct list_head list;
219 unsigned long phys_base;
220 struct device *dev;
221 void __iomem *io_base;
222 int irq;
223 spinlock_t lock;
224 int err;
225 struct dma_chan *dma_lch;
226 struct tasklet_struct done_task;
227 u8 polling_mode;
228 u8 xmit_buf[BUFLEN];
229
230 unsigned long flags;
231 struct crypto_queue queue;
232 struct ahash_request *req;
233
234 const struct omap_sham_pdata *pdata;
235 };
236
237 struct omap_sham_drv {
238 struct list_head dev_list;
239 spinlock_t lock;
240 unsigned long flags;
241 };
242
243 static struct omap_sham_drv sham = {
244 .dev_list = LIST_HEAD_INIT(sham.dev_list),
245 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
246 };
247
248 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
249 {
250 return __raw_readl(dd->io_base + offset);
251 }
252
253 static inline void omap_sham_write(struct omap_sham_dev *dd,
254 u32 offset, u32 value)
255 {
256 __raw_writel(value, dd->io_base + offset);
257 }
258
259 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
260 u32 value, u32 mask)
261 {
262 u32 val;
263
264 val = omap_sham_read(dd, address);
265 val &= ~mask;
266 val |= value;
267 omap_sham_write(dd, address, val);
268 }
269
270 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
271 {
272 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
273
274 while (!(omap_sham_read(dd, offset) & bit)) {
275 if (time_is_before_jiffies(timeout))
276 return -ETIMEDOUT;
277 }
278
279 return 0;
280 }
281
282 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
283 {
284 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
285 struct omap_sham_dev *dd = ctx->dd;
286 u32 *hash = (u32 *)ctx->digest;
287 int i;
288
289 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
290 if (out)
291 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
292 else
293 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
294 }
295 }
296
297 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
298 {
299 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
300 struct omap_sham_dev *dd = ctx->dd;
301 int i;
302
303 if (ctx->flags & BIT(FLAGS_HMAC)) {
304 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
305 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
306 struct omap_sham_hmac_ctx *bctx = tctx->base;
307 u32 *opad = (u32 *)bctx->opad;
308
309 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
310 if (out)
311 opad[i] = omap_sham_read(dd,
312 SHA_REG_ODIGEST(dd, i));
313 else
314 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
315 opad[i]);
316 }
317 }
318
319 omap_sham_copy_hash_omap2(req, out);
320 }
321
322 static void omap_sham_copy_ready_hash(struct ahash_request *req)
323 {
324 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
325 u32 *in = (u32 *)ctx->digest;
326 u32 *hash = (u32 *)req->result;
327 int i, d, big_endian = 0;
328
329 if (!hash)
330 return;
331
332 switch (ctx->flags & FLAGS_MODE_MASK) {
333 case FLAGS_MODE_MD5:
334 d = MD5_DIGEST_SIZE / sizeof(u32);
335 break;
336 case FLAGS_MODE_SHA1:
337 /* OMAP2 SHA1 is big endian */
338 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
339 big_endian = 1;
340 d = SHA1_DIGEST_SIZE / sizeof(u32);
341 break;
342 case FLAGS_MODE_SHA224:
343 d = SHA224_DIGEST_SIZE / sizeof(u32);
344 break;
345 case FLAGS_MODE_SHA256:
346 d = SHA256_DIGEST_SIZE / sizeof(u32);
347 break;
348 case FLAGS_MODE_SHA384:
349 d = SHA384_DIGEST_SIZE / sizeof(u32);
350 break;
351 case FLAGS_MODE_SHA512:
352 d = SHA512_DIGEST_SIZE / sizeof(u32);
353 break;
354 default:
355 d = 0;
356 }
357
358 if (big_endian)
359 for (i = 0; i < d; i++)
360 hash[i] = be32_to_cpu(in[i]);
361 else
362 for (i = 0; i < d; i++)
363 hash[i] = le32_to_cpu(in[i]);
364 }
365
366 static int omap_sham_hw_init(struct omap_sham_dev *dd)
367 {
368 int err;
369
370 err = pm_runtime_get_sync(dd->dev);
371 if (err < 0) {
372 dev_err(dd->dev, "failed to get sync: %d\n", err);
373 return err;
374 }
375
376 if (!test_bit(FLAGS_INIT, &dd->flags)) {
377 set_bit(FLAGS_INIT, &dd->flags);
378 dd->err = 0;
379 }
380
381 return 0;
382 }
383
384 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
385 int final, int dma)
386 {
387 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
388 u32 val = length << 5, mask;
389
390 if (likely(ctx->digcnt))
391 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
392
393 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
394 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
395 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
396 /*
397 * Setting ALGO_CONST only for the first iteration
398 * and CLOSE_HASH only for the last one.
399 */
400 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
401 val |= SHA_REG_CTRL_ALGO;
402 if (!ctx->digcnt)
403 val |= SHA_REG_CTRL_ALGO_CONST;
404 if (final)
405 val |= SHA_REG_CTRL_CLOSE_HASH;
406
407 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
408 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
409
410 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
411 }
412
413 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
414 {
415 }
416
417 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
418 {
419 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
420 }
421
422 static int get_block_size(struct omap_sham_reqctx *ctx)
423 {
424 int d;
425
426 switch (ctx->flags & FLAGS_MODE_MASK) {
427 case FLAGS_MODE_MD5:
428 case FLAGS_MODE_SHA1:
429 d = SHA1_BLOCK_SIZE;
430 break;
431 case FLAGS_MODE_SHA224:
432 case FLAGS_MODE_SHA256:
433 d = SHA256_BLOCK_SIZE;
434 break;
435 case FLAGS_MODE_SHA384:
436 case FLAGS_MODE_SHA512:
437 d = SHA512_BLOCK_SIZE;
438 break;
439 default:
440 d = 0;
441 }
442
443 return d;
444 }
445
446 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
447 u32 *value, int count)
448 {
449 for (; count--; value++, offset += 4)
450 omap_sham_write(dd, offset, *value);
451 }
452
453 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
454 int final, int dma)
455 {
456 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
457 u32 val, mask;
458
459 /*
460 * Setting ALGO_CONST only for the first iteration and
461 * CLOSE_HASH only for the last one. Note that flags mode bits
462 * correspond to algorithm encoding in mode register.
463 */
464 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
465 if (!ctx->digcnt) {
466 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
467 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
468 struct omap_sham_hmac_ctx *bctx = tctx->base;
469 int bs, nr_dr;
470
471 val |= SHA_REG_MODE_ALGO_CONSTANT;
472
473 if (ctx->flags & BIT(FLAGS_HMAC)) {
474 bs = get_block_size(ctx);
475 nr_dr = bs / (2 * sizeof(u32));
476 val |= SHA_REG_MODE_HMAC_KEY_PROC;
477 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
478 (u32 *)bctx->ipad, nr_dr);
479 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
480 (u32 *)bctx->ipad + nr_dr, nr_dr);
481 ctx->digcnt += bs;
482 }
483 }
484
485 if (final) {
486 val |= SHA_REG_MODE_CLOSE_HASH;
487
488 if (ctx->flags & BIT(FLAGS_HMAC))
489 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
490 }
491
492 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
493 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
494 SHA_REG_MODE_HMAC_KEY_PROC;
495
496 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
497 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
498 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
499 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
500 SHA_REG_MASK_IT_EN |
501 (dma ? SHA_REG_MASK_DMA_EN : 0),
502 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
503 }
504
505 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
506 {
507 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
508 }
509
510 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
511 {
512 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
513 SHA_REG_IRQSTATUS_INPUT_RDY);
514 }
515
516 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
517 int final)
518 {
519 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
520 int count, len32, bs32, offset = 0;
521 const u32 *buffer;
522 int mlen;
523 struct sg_mapping_iter mi;
524
525 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
526 ctx->digcnt, length, final);
527
528 dd->pdata->write_ctrl(dd, length, final, 0);
529 dd->pdata->trigger(dd, length);
530
531 /* should be non-zero before next lines to disable clocks later */
532 ctx->digcnt += length;
533 ctx->total -= length;
534
535 if (final)
536 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
537
538 set_bit(FLAGS_CPU, &dd->flags);
539
540 len32 = DIV_ROUND_UP(length, sizeof(u32));
541 bs32 = get_block_size(ctx) / sizeof(u32);
542
543 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
544 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
545
546 mlen = 0;
547
548 while (len32) {
549 if (dd->pdata->poll_irq(dd))
550 return -ETIMEDOUT;
551
552 for (count = 0; count < min(len32, bs32); count++, offset++) {
553 if (!mlen) {
554 sg_miter_next(&mi);
555 mlen = mi.length;
556 if (!mlen) {
557 pr_err("sg miter failure.\n");
558 return -EINVAL;
559 }
560 offset = 0;
561 buffer = mi.addr;
562 }
563 omap_sham_write(dd, SHA_REG_DIN(dd, count),
564 buffer[offset]);
565 mlen -= 4;
566 }
567 len32 -= min(len32, bs32);
568 }
569
570 sg_miter_stop(&mi);
571
572 return -EINPROGRESS;
573 }
574
575 static void omap_sham_dma_callback(void *param)
576 {
577 struct omap_sham_dev *dd = param;
578
579 set_bit(FLAGS_DMA_READY, &dd->flags);
580 tasklet_schedule(&dd->done_task);
581 }
582
583 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
584 int final)
585 {
586 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
587 struct dma_async_tx_descriptor *tx;
588 struct dma_slave_config cfg;
589 int ret;
590
591 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
592 ctx->digcnt, length, final);
593
594 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
595 dev_err(dd->dev, "dma_map_sg error\n");
596 return -EINVAL;
597 }
598
599 memset(&cfg, 0, sizeof(cfg));
600
601 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
602 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
603 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
604
605 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
606 if (ret) {
607 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
608 return ret;
609 }
610
611 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
612 DMA_MEM_TO_DEV,
613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
614
615 if (!tx) {
616 dev_err(dd->dev, "prep_slave_sg failed\n");
617 return -EINVAL;
618 }
619
620 tx->callback = omap_sham_dma_callback;
621 tx->callback_param = dd;
622
623 dd->pdata->write_ctrl(dd, length, final, 1);
624
625 ctx->digcnt += length;
626 ctx->total -= length;
627
628 if (final)
629 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
630
631 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
632
633 dmaengine_submit(tx);
634 dma_async_issue_pending(dd->dma_lch);
635
636 dd->pdata->trigger(dd, length);
637
638 return -EINPROGRESS;
639 }
640
641 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
642 struct scatterlist *sg, int bs, int new_len)
643 {
644 int n = sg_nents(sg);
645 struct scatterlist *tmp;
646 int offset = ctx->offset;
647
648 if (ctx->bufcnt)
649 n++;
650
651 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
652 if (!ctx->sg)
653 return -ENOMEM;
654
655 sg_init_table(ctx->sg, n);
656
657 tmp = ctx->sg;
658
659 ctx->sg_len = 0;
660
661 if (ctx->bufcnt) {
662 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
663 tmp = sg_next(tmp);
664 ctx->sg_len++;
665 }
666
667 while (sg && new_len) {
668 int len = sg->length - offset;
669
670 if (offset) {
671 offset -= sg->length;
672 if (offset < 0)
673 offset = 0;
674 }
675
676 if (new_len < len)
677 len = new_len;
678
679 if (len > 0) {
680 new_len -= len;
681 sg_set_page(tmp, sg_page(sg), len, sg->offset);
682 if (new_len <= 0)
683 sg_mark_end(tmp);
684 tmp = sg_next(tmp);
685 ctx->sg_len++;
686 }
687
688 sg = sg_next(sg);
689 }
690
691 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
692
693 ctx->bufcnt = 0;
694
695 return 0;
696 }
697
698 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
699 struct scatterlist *sg, int bs, int new_len)
700 {
701 int pages;
702 void *buf;
703 int len;
704
705 len = new_len + ctx->bufcnt;
706
707 pages = get_order(ctx->total);
708
709 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
710 if (!buf) {
711 pr_err("Couldn't allocate pages for unaligned cases.\n");
712 return -ENOMEM;
713 }
714
715 if (ctx->bufcnt)
716 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
717
718 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
719 ctx->total - ctx->bufcnt, 0);
720 sg_init_table(ctx->sgl, 1);
721 sg_set_buf(ctx->sgl, buf, len);
722 ctx->sg = ctx->sgl;
723 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
724 ctx->sg_len = 1;
725 ctx->bufcnt = 0;
726 ctx->offset = 0;
727
728 return 0;
729 }
730
731 static int omap_sham_align_sgs(struct scatterlist *sg,
732 int nbytes, int bs, bool final,
733 struct omap_sham_reqctx *rctx)
734 {
735 int n = 0;
736 bool aligned = true;
737 bool list_ok = true;
738 struct scatterlist *sg_tmp = sg;
739 int new_len;
740 int offset = rctx->offset;
741
742 if (!sg || !sg->length || !nbytes)
743 return 0;
744
745 new_len = nbytes;
746
747 if (offset)
748 list_ok = false;
749
750 if (final)
751 new_len = DIV_ROUND_UP(new_len, bs) * bs;
752 else
753 new_len = (new_len - 1) / bs * bs;
754
755 if (nbytes != new_len)
756 list_ok = false;
757
758 while (nbytes > 0 && sg_tmp) {
759 n++;
760
761 if (offset < sg_tmp->length) {
762 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
763 aligned = false;
764 break;
765 }
766
767 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
768 aligned = false;
769 break;
770 }
771 }
772
773 if (offset) {
774 offset -= sg_tmp->length;
775 if (offset < 0) {
776 nbytes += offset;
777 offset = 0;
778 }
779 } else {
780 nbytes -= sg_tmp->length;
781 }
782
783 sg_tmp = sg_next(sg_tmp);
784
785 if (nbytes < 0) {
786 list_ok = false;
787 break;
788 }
789 }
790
791 if (!aligned)
792 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
793 else if (!list_ok)
794 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
795
796 rctx->sg_len = n;
797 rctx->sg = sg;
798
799 return 0;
800 }
801
802 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
803 {
804 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
805 int bs;
806 int ret;
807 int nbytes;
808 bool final = rctx->flags & BIT(FLAGS_FINUP);
809 int xmit_len, hash_later;
810
811 if (!req)
812 return 0;
813
814 bs = get_block_size(rctx);
815
816 if (update)
817 nbytes = req->nbytes;
818 else
819 nbytes = 0;
820
821 rctx->total = nbytes + rctx->bufcnt;
822
823 if (!rctx->total)
824 return 0;
825
826 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
827 int len = bs - rctx->bufcnt % bs;
828
829 if (len > nbytes)
830 len = nbytes;
831 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
832 0, len, 0);
833 rctx->bufcnt += len;
834 nbytes -= len;
835 rctx->offset = len;
836 }
837
838 if (rctx->bufcnt)
839 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
840
841 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
842 if (ret)
843 return ret;
844
845 xmit_len = rctx->total;
846
847 if (!IS_ALIGNED(xmit_len, bs)) {
848 if (final)
849 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
850 else
851 xmit_len = xmit_len / bs * bs;
852 } else if (!final) {
853 xmit_len -= bs;
854 }
855
856 hash_later = rctx->total - xmit_len;
857 if (hash_later < 0)
858 hash_later = 0;
859
860 if (rctx->bufcnt && nbytes) {
861 /* have data from previous operation and current */
862 sg_init_table(rctx->sgl, 2);
863 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
864
865 sg_chain(rctx->sgl, 2, req->src);
866
867 rctx->sg = rctx->sgl;
868
869 rctx->sg_len++;
870 } else if (rctx->bufcnt) {
871 /* have buffered data only */
872 sg_init_table(rctx->sgl, 1);
873 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
874
875 rctx->sg = rctx->sgl;
876
877 rctx->sg_len = 1;
878 }
879
880 if (hash_later) {
881 int offset = 0;
882
883 if (hash_later > req->nbytes) {
884 memcpy(rctx->buffer, rctx->buffer + xmit_len,
885 hash_later - req->nbytes);
886 offset = hash_later - req->nbytes;
887 }
888
889 if (req->nbytes) {
890 scatterwalk_map_and_copy(rctx->buffer + offset,
891 req->src,
892 offset + req->nbytes -
893 hash_later, hash_later, 0);
894 }
895
896 rctx->bufcnt = hash_later;
897 } else {
898 rctx->bufcnt = 0;
899 }
900
901 if (!final)
902 rctx->total = xmit_len;
903
904 return 0;
905 }
906
907 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
908 {
909 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
910
911 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
912
913 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
914
915 return 0;
916 }
917
918 static int omap_sham_init(struct ahash_request *req)
919 {
920 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
921 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
922 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
923 struct omap_sham_dev *dd = NULL, *tmp;
924 int bs = 0;
925
926 spin_lock_bh(&sham.lock);
927 if (!tctx->dd) {
928 list_for_each_entry(tmp, &sham.dev_list, list) {
929 dd = tmp;
930 break;
931 }
932 tctx->dd = dd;
933 } else {
934 dd = tctx->dd;
935 }
936 spin_unlock_bh(&sham.lock);
937
938 ctx->dd = dd;
939
940 ctx->flags = 0;
941
942 dev_dbg(dd->dev, "init: digest size: %d\n",
943 crypto_ahash_digestsize(tfm));
944
945 switch (crypto_ahash_digestsize(tfm)) {
946 case MD5_DIGEST_SIZE:
947 ctx->flags |= FLAGS_MODE_MD5;
948 bs = SHA1_BLOCK_SIZE;
949 break;
950 case SHA1_DIGEST_SIZE:
951 ctx->flags |= FLAGS_MODE_SHA1;
952 bs = SHA1_BLOCK_SIZE;
953 break;
954 case SHA224_DIGEST_SIZE:
955 ctx->flags |= FLAGS_MODE_SHA224;
956 bs = SHA224_BLOCK_SIZE;
957 break;
958 case SHA256_DIGEST_SIZE:
959 ctx->flags |= FLAGS_MODE_SHA256;
960 bs = SHA256_BLOCK_SIZE;
961 break;
962 case SHA384_DIGEST_SIZE:
963 ctx->flags |= FLAGS_MODE_SHA384;
964 bs = SHA384_BLOCK_SIZE;
965 break;
966 case SHA512_DIGEST_SIZE:
967 ctx->flags |= FLAGS_MODE_SHA512;
968 bs = SHA512_BLOCK_SIZE;
969 break;
970 }
971
972 ctx->bufcnt = 0;
973 ctx->digcnt = 0;
974 ctx->total = 0;
975 ctx->offset = 0;
976 ctx->buflen = BUFLEN;
977
978 if (tctx->flags & BIT(FLAGS_HMAC)) {
979 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
980 struct omap_sham_hmac_ctx *bctx = tctx->base;
981
982 memcpy(ctx->buffer, bctx->ipad, bs);
983 ctx->bufcnt = bs;
984 }
985
986 ctx->flags |= BIT(FLAGS_HMAC);
987 }
988
989 return 0;
990
991 }
992
993 static int omap_sham_update_req(struct omap_sham_dev *dd)
994 {
995 struct ahash_request *req = dd->req;
996 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
997 int err;
998 bool final = ctx->flags & BIT(FLAGS_FINUP);
999
1000 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1001 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1002
1003 if (ctx->total < get_block_size(ctx) ||
1004 ctx->total < OMAP_SHA_DMA_THRESHOLD)
1005 ctx->flags |= BIT(FLAGS_CPU);
1006
1007 if (ctx->flags & BIT(FLAGS_CPU))
1008 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1009 else
1010 err = omap_sham_xmit_dma(dd, ctx->total, final);
1011
1012 /* wait for dma completion before can take more data */
1013 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1014
1015 return err;
1016 }
1017
1018 static int omap_sham_final_req(struct omap_sham_dev *dd)
1019 {
1020 struct ahash_request *req = dd->req;
1021 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1022 int err = 0, use_dma = 1;
1023
1024 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1025 /*
1026 * faster to handle last block with cpu or
1027 * use cpu when dma is not present.
1028 */
1029 use_dma = 0;
1030
1031 if (use_dma)
1032 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1033 else
1034 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1035
1036 ctx->bufcnt = 0;
1037
1038 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1039
1040 return err;
1041 }
1042
1043 static int omap_sham_finish_hmac(struct ahash_request *req)
1044 {
1045 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1046 struct omap_sham_hmac_ctx *bctx = tctx->base;
1047 int bs = crypto_shash_blocksize(bctx->shash);
1048 int ds = crypto_shash_digestsize(bctx->shash);
1049 SHASH_DESC_ON_STACK(shash, bctx->shash);
1050
1051 shash->tfm = bctx->shash;
1052 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1053
1054 return crypto_shash_init(shash) ?:
1055 crypto_shash_update(shash, bctx->opad, bs) ?:
1056 crypto_shash_finup(shash, req->result, ds, req->result);
1057 }
1058
1059 static int omap_sham_finish(struct ahash_request *req)
1060 {
1061 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1062 struct omap_sham_dev *dd = ctx->dd;
1063 int err = 0;
1064
1065 if (ctx->digcnt) {
1066 omap_sham_copy_ready_hash(req);
1067 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1068 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1069 err = omap_sham_finish_hmac(req);
1070 }
1071
1072 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1073
1074 return err;
1075 }
1076
1077 static void omap_sham_finish_req(struct ahash_request *req, int err)
1078 {
1079 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1080 struct omap_sham_dev *dd = ctx->dd;
1081
1082 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1083 free_pages((unsigned long)sg_virt(ctx->sg),
1084 get_order(ctx->sg->length + ctx->bufcnt));
1085
1086 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1087 kfree(ctx->sg);
1088
1089 ctx->sg = NULL;
1090
1091 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1092
1093 if (!err) {
1094 dd->pdata->copy_hash(req, 1);
1095 if (test_bit(FLAGS_FINAL, &dd->flags))
1096 err = omap_sham_finish(req);
1097 } else {
1098 ctx->flags |= BIT(FLAGS_ERROR);
1099 }
1100
1101 /* atomic operation is not needed here */
1102 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1103 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1104
1105 pm_runtime_mark_last_busy(dd->dev);
1106 pm_runtime_put_autosuspend(dd->dev);
1107
1108 if (req->base.complete)
1109 req->base.complete(&req->base, err);
1110 }
1111
1112 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1113 struct ahash_request *req)
1114 {
1115 struct crypto_async_request *async_req, *backlog;
1116 struct omap_sham_reqctx *ctx;
1117 unsigned long flags;
1118 int err = 0, ret = 0;
1119
1120 retry:
1121 spin_lock_irqsave(&dd->lock, flags);
1122 if (req)
1123 ret = ahash_enqueue_request(&dd->queue, req);
1124 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1125 spin_unlock_irqrestore(&dd->lock, flags);
1126 return ret;
1127 }
1128 backlog = crypto_get_backlog(&dd->queue);
1129 async_req = crypto_dequeue_request(&dd->queue);
1130 if (async_req)
1131 set_bit(FLAGS_BUSY, &dd->flags);
1132 spin_unlock_irqrestore(&dd->lock, flags);
1133
1134 if (!async_req)
1135 return ret;
1136
1137 if (backlog)
1138 backlog->complete(backlog, -EINPROGRESS);
1139
1140 req = ahash_request_cast(async_req);
1141 dd->req = req;
1142 ctx = ahash_request_ctx(req);
1143
1144 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1145 if (err || !ctx->total)
1146 goto err1;
1147
1148 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1149 ctx->op, req->nbytes);
1150
1151 err = omap_sham_hw_init(dd);
1152 if (err)
1153 goto err1;
1154
1155 if (ctx->digcnt)
1156 /* request has changed - restore hash */
1157 dd->pdata->copy_hash(req, 0);
1158
1159 if (ctx->op == OP_UPDATE) {
1160 err = omap_sham_update_req(dd);
1161 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1162 /* no final() after finup() */
1163 err = omap_sham_final_req(dd);
1164 } else if (ctx->op == OP_FINAL) {
1165 err = omap_sham_final_req(dd);
1166 }
1167 err1:
1168 dev_dbg(dd->dev, "exit, err: %d\n", err);
1169
1170 if (err != -EINPROGRESS) {
1171 /* done_task will not finish it, so do it here */
1172 omap_sham_finish_req(req, err);
1173 req = NULL;
1174
1175 /*
1176 * Execute next request immediately if there is anything
1177 * in queue.
1178 */
1179 goto retry;
1180 }
1181
1182 return ret;
1183 }
1184
1185 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1186 {
1187 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1188 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1189 struct omap_sham_dev *dd = tctx->dd;
1190
1191 ctx->op = op;
1192
1193 return omap_sham_handle_queue(dd, req);
1194 }
1195
1196 static int omap_sham_update(struct ahash_request *req)
1197 {
1198 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1199 struct omap_sham_dev *dd = ctx->dd;
1200
1201 if (!req->nbytes)
1202 return 0;
1203
1204 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1205 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1206 0, req->nbytes, 0);
1207 ctx->bufcnt += req->nbytes;
1208 return 0;
1209 }
1210
1211 if (dd->polling_mode)
1212 ctx->flags |= BIT(FLAGS_CPU);
1213
1214 return omap_sham_enqueue(req, OP_UPDATE);
1215 }
1216
1217 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1218 const u8 *data, unsigned int len, u8 *out)
1219 {
1220 SHASH_DESC_ON_STACK(shash, tfm);
1221
1222 shash->tfm = tfm;
1223 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1224
1225 return crypto_shash_digest(shash, data, len, out);
1226 }
1227
1228 static int omap_sham_final_shash(struct ahash_request *req)
1229 {
1230 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1231 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1232 int offset = 0;
1233
1234 /*
1235 * If we are running HMAC on limited hardware support, skip
1236 * the ipad in the beginning of the buffer if we are going for
1237 * software fallback algorithm.
1238 */
1239 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1240 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1241 offset = get_block_size(ctx);
1242
1243 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1244 ctx->buffer + offset,
1245 ctx->bufcnt - offset, req->result);
1246 }
1247
1248 static int omap_sham_final(struct ahash_request *req)
1249 {
1250 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1251
1252 ctx->flags |= BIT(FLAGS_FINUP);
1253
1254 if (ctx->flags & BIT(FLAGS_ERROR))
1255 return 0; /* uncompleted hash is not needed */
1256
1257 /*
1258 * OMAP HW accel works only with buffers >= 9.
1259 * HMAC is always >= 9 because ipad == block size.
1260 * If buffersize is less than DMA_THRESHOLD, we use fallback
1261 * SW encoding, as using DMA + HW in this case doesn't provide
1262 * any benefit.
1263 */
1264 if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1265 return omap_sham_final_shash(req);
1266 else if (ctx->bufcnt)
1267 return omap_sham_enqueue(req, OP_FINAL);
1268
1269 /* copy ready hash (+ finalize hmac) */
1270 return omap_sham_finish(req);
1271 }
1272
1273 static int omap_sham_finup(struct ahash_request *req)
1274 {
1275 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1276 int err1, err2;
1277
1278 ctx->flags |= BIT(FLAGS_FINUP);
1279
1280 err1 = omap_sham_update(req);
1281 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1282 return err1;
1283 /*
1284 * final() has to be always called to cleanup resources
1285 * even if udpate() failed, except EINPROGRESS
1286 */
1287 err2 = omap_sham_final(req);
1288
1289 return err1 ?: err2;
1290 }
1291
1292 static int omap_sham_digest(struct ahash_request *req)
1293 {
1294 return omap_sham_init(req) ?: omap_sham_finup(req);
1295 }
1296
1297 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1298 unsigned int keylen)
1299 {
1300 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1301 struct omap_sham_hmac_ctx *bctx = tctx->base;
1302 int bs = crypto_shash_blocksize(bctx->shash);
1303 int ds = crypto_shash_digestsize(bctx->shash);
1304 struct omap_sham_dev *dd = NULL, *tmp;
1305 int err, i;
1306
1307 spin_lock_bh(&sham.lock);
1308 if (!tctx->dd) {
1309 list_for_each_entry(tmp, &sham.dev_list, list) {
1310 dd = tmp;
1311 break;
1312 }
1313 tctx->dd = dd;
1314 } else {
1315 dd = tctx->dd;
1316 }
1317 spin_unlock_bh(&sham.lock);
1318
1319 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1320 if (err)
1321 return err;
1322
1323 if (keylen > bs) {
1324 err = omap_sham_shash_digest(bctx->shash,
1325 crypto_shash_get_flags(bctx->shash),
1326 key, keylen, bctx->ipad);
1327 if (err)
1328 return err;
1329 keylen = ds;
1330 } else {
1331 memcpy(bctx->ipad, key, keylen);
1332 }
1333
1334 memset(bctx->ipad + keylen, 0, bs - keylen);
1335
1336 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1337 memcpy(bctx->opad, bctx->ipad, bs);
1338
1339 for (i = 0; i < bs; i++) {
1340 bctx->ipad[i] ^= 0x36;
1341 bctx->opad[i] ^= 0x5c;
1342 }
1343 }
1344
1345 return err;
1346 }
1347
1348 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1349 {
1350 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1351 const char *alg_name = crypto_tfm_alg_name(tfm);
1352
1353 /* Allocate a fallback and abort if it failed. */
1354 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1355 CRYPTO_ALG_NEED_FALLBACK);
1356 if (IS_ERR(tctx->fallback)) {
1357 pr_err("omap-sham: fallback driver '%s' "
1358 "could not be loaded.\n", alg_name);
1359 return PTR_ERR(tctx->fallback);
1360 }
1361
1362 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1363 sizeof(struct omap_sham_reqctx) + BUFLEN);
1364
1365 if (alg_base) {
1366 struct omap_sham_hmac_ctx *bctx = tctx->base;
1367 tctx->flags |= BIT(FLAGS_HMAC);
1368 bctx->shash = crypto_alloc_shash(alg_base, 0,
1369 CRYPTO_ALG_NEED_FALLBACK);
1370 if (IS_ERR(bctx->shash)) {
1371 pr_err("omap-sham: base driver '%s' "
1372 "could not be loaded.\n", alg_base);
1373 crypto_free_shash(tctx->fallback);
1374 return PTR_ERR(bctx->shash);
1375 }
1376
1377 }
1378
1379 return 0;
1380 }
1381
1382 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1383 {
1384 return omap_sham_cra_init_alg(tfm, NULL);
1385 }
1386
1387 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1388 {
1389 return omap_sham_cra_init_alg(tfm, "sha1");
1390 }
1391
1392 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1393 {
1394 return omap_sham_cra_init_alg(tfm, "sha224");
1395 }
1396
1397 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1398 {
1399 return omap_sham_cra_init_alg(tfm, "sha256");
1400 }
1401
1402 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1403 {
1404 return omap_sham_cra_init_alg(tfm, "md5");
1405 }
1406
1407 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1408 {
1409 return omap_sham_cra_init_alg(tfm, "sha384");
1410 }
1411
1412 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1413 {
1414 return omap_sham_cra_init_alg(tfm, "sha512");
1415 }
1416
1417 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1418 {
1419 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1420
1421 crypto_free_shash(tctx->fallback);
1422 tctx->fallback = NULL;
1423
1424 if (tctx->flags & BIT(FLAGS_HMAC)) {
1425 struct omap_sham_hmac_ctx *bctx = tctx->base;
1426 crypto_free_shash(bctx->shash);
1427 }
1428 }
1429
1430 static int omap_sham_export(struct ahash_request *req, void *out)
1431 {
1432 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1433
1434 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1435
1436 return 0;
1437 }
1438
1439 static int omap_sham_import(struct ahash_request *req, const void *in)
1440 {
1441 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1442 const struct omap_sham_reqctx *ctx_in = in;
1443
1444 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1445
1446 return 0;
1447 }
1448
1449 static struct ahash_alg algs_sha1_md5[] = {
1450 {
1451 .init = omap_sham_init,
1452 .update = omap_sham_update,
1453 .final = omap_sham_final,
1454 .finup = omap_sham_finup,
1455 .digest = omap_sham_digest,
1456 .halg.digestsize = SHA1_DIGEST_SIZE,
1457 .halg.base = {
1458 .cra_name = "sha1",
1459 .cra_driver_name = "omap-sha1",
1460 .cra_priority = 400,
1461 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1462 CRYPTO_ALG_KERN_DRIVER_ONLY |
1463 CRYPTO_ALG_ASYNC |
1464 CRYPTO_ALG_NEED_FALLBACK,
1465 .cra_blocksize = SHA1_BLOCK_SIZE,
1466 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1467 .cra_alignmask = OMAP_ALIGN_MASK,
1468 .cra_module = THIS_MODULE,
1469 .cra_init = omap_sham_cra_init,
1470 .cra_exit = omap_sham_cra_exit,
1471 }
1472 },
1473 {
1474 .init = omap_sham_init,
1475 .update = omap_sham_update,
1476 .final = omap_sham_final,
1477 .finup = omap_sham_finup,
1478 .digest = omap_sham_digest,
1479 .halg.digestsize = MD5_DIGEST_SIZE,
1480 .halg.base = {
1481 .cra_name = "md5",
1482 .cra_driver_name = "omap-md5",
1483 .cra_priority = 400,
1484 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1485 CRYPTO_ALG_KERN_DRIVER_ONLY |
1486 CRYPTO_ALG_ASYNC |
1487 CRYPTO_ALG_NEED_FALLBACK,
1488 .cra_blocksize = SHA1_BLOCK_SIZE,
1489 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1490 .cra_alignmask = OMAP_ALIGN_MASK,
1491 .cra_module = THIS_MODULE,
1492 .cra_init = omap_sham_cra_init,
1493 .cra_exit = omap_sham_cra_exit,
1494 }
1495 },
1496 {
1497 .init = omap_sham_init,
1498 .update = omap_sham_update,
1499 .final = omap_sham_final,
1500 .finup = omap_sham_finup,
1501 .digest = omap_sham_digest,
1502 .setkey = omap_sham_setkey,
1503 .halg.digestsize = SHA1_DIGEST_SIZE,
1504 .halg.base = {
1505 .cra_name = "hmac(sha1)",
1506 .cra_driver_name = "omap-hmac-sha1",
1507 .cra_priority = 400,
1508 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1509 CRYPTO_ALG_KERN_DRIVER_ONLY |
1510 CRYPTO_ALG_ASYNC |
1511 CRYPTO_ALG_NEED_FALLBACK,
1512 .cra_blocksize = SHA1_BLOCK_SIZE,
1513 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1514 sizeof(struct omap_sham_hmac_ctx),
1515 .cra_alignmask = OMAP_ALIGN_MASK,
1516 .cra_module = THIS_MODULE,
1517 .cra_init = omap_sham_cra_sha1_init,
1518 .cra_exit = omap_sham_cra_exit,
1519 }
1520 },
1521 {
1522 .init = omap_sham_init,
1523 .update = omap_sham_update,
1524 .final = omap_sham_final,
1525 .finup = omap_sham_finup,
1526 .digest = omap_sham_digest,
1527 .setkey = omap_sham_setkey,
1528 .halg.digestsize = MD5_DIGEST_SIZE,
1529 .halg.base = {
1530 .cra_name = "hmac(md5)",
1531 .cra_driver_name = "omap-hmac-md5",
1532 .cra_priority = 400,
1533 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1534 CRYPTO_ALG_KERN_DRIVER_ONLY |
1535 CRYPTO_ALG_ASYNC |
1536 CRYPTO_ALG_NEED_FALLBACK,
1537 .cra_blocksize = SHA1_BLOCK_SIZE,
1538 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1539 sizeof(struct omap_sham_hmac_ctx),
1540 .cra_alignmask = OMAP_ALIGN_MASK,
1541 .cra_module = THIS_MODULE,
1542 .cra_init = omap_sham_cra_md5_init,
1543 .cra_exit = omap_sham_cra_exit,
1544 }
1545 }
1546 };
1547
1548 /* OMAP4 has some algs in addition to what OMAP2 has */
1549 static struct ahash_alg algs_sha224_sha256[] = {
1550 {
1551 .init = omap_sham_init,
1552 .update = omap_sham_update,
1553 .final = omap_sham_final,
1554 .finup = omap_sham_finup,
1555 .digest = omap_sham_digest,
1556 .halg.digestsize = SHA224_DIGEST_SIZE,
1557 .halg.base = {
1558 .cra_name = "sha224",
1559 .cra_driver_name = "omap-sha224",
1560 .cra_priority = 400,
1561 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1562 CRYPTO_ALG_ASYNC |
1563 CRYPTO_ALG_NEED_FALLBACK,
1564 .cra_blocksize = SHA224_BLOCK_SIZE,
1565 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1566 .cra_alignmask = OMAP_ALIGN_MASK,
1567 .cra_module = THIS_MODULE,
1568 .cra_init = omap_sham_cra_init,
1569 .cra_exit = omap_sham_cra_exit,
1570 }
1571 },
1572 {
1573 .init = omap_sham_init,
1574 .update = omap_sham_update,
1575 .final = omap_sham_final,
1576 .finup = omap_sham_finup,
1577 .digest = omap_sham_digest,
1578 .halg.digestsize = SHA256_DIGEST_SIZE,
1579 .halg.base = {
1580 .cra_name = "sha256",
1581 .cra_driver_name = "omap-sha256",
1582 .cra_priority = 400,
1583 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1584 CRYPTO_ALG_ASYNC |
1585 CRYPTO_ALG_NEED_FALLBACK,
1586 .cra_blocksize = SHA256_BLOCK_SIZE,
1587 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1588 .cra_alignmask = OMAP_ALIGN_MASK,
1589 .cra_module = THIS_MODULE,
1590 .cra_init = omap_sham_cra_init,
1591 .cra_exit = omap_sham_cra_exit,
1592 }
1593 },
1594 {
1595 .init = omap_sham_init,
1596 .update = omap_sham_update,
1597 .final = omap_sham_final,
1598 .finup = omap_sham_finup,
1599 .digest = omap_sham_digest,
1600 .setkey = omap_sham_setkey,
1601 .halg.digestsize = SHA224_DIGEST_SIZE,
1602 .halg.base = {
1603 .cra_name = "hmac(sha224)",
1604 .cra_driver_name = "omap-hmac-sha224",
1605 .cra_priority = 400,
1606 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1607 CRYPTO_ALG_ASYNC |
1608 CRYPTO_ALG_NEED_FALLBACK,
1609 .cra_blocksize = SHA224_BLOCK_SIZE,
1610 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1611 sizeof(struct omap_sham_hmac_ctx),
1612 .cra_alignmask = OMAP_ALIGN_MASK,
1613 .cra_module = THIS_MODULE,
1614 .cra_init = omap_sham_cra_sha224_init,
1615 .cra_exit = omap_sham_cra_exit,
1616 }
1617 },
1618 {
1619 .init = omap_sham_init,
1620 .update = omap_sham_update,
1621 .final = omap_sham_final,
1622 .finup = omap_sham_finup,
1623 .digest = omap_sham_digest,
1624 .setkey = omap_sham_setkey,
1625 .halg.digestsize = SHA256_DIGEST_SIZE,
1626 .halg.base = {
1627 .cra_name = "hmac(sha256)",
1628 .cra_driver_name = "omap-hmac-sha256",
1629 .cra_priority = 400,
1630 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1631 CRYPTO_ALG_ASYNC |
1632 CRYPTO_ALG_NEED_FALLBACK,
1633 .cra_blocksize = SHA256_BLOCK_SIZE,
1634 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1635 sizeof(struct omap_sham_hmac_ctx),
1636 .cra_alignmask = OMAP_ALIGN_MASK,
1637 .cra_module = THIS_MODULE,
1638 .cra_init = omap_sham_cra_sha256_init,
1639 .cra_exit = omap_sham_cra_exit,
1640 }
1641 },
1642 };
1643
1644 static struct ahash_alg algs_sha384_sha512[] = {
1645 {
1646 .init = omap_sham_init,
1647 .update = omap_sham_update,
1648 .final = omap_sham_final,
1649 .finup = omap_sham_finup,
1650 .digest = omap_sham_digest,
1651 .halg.digestsize = SHA384_DIGEST_SIZE,
1652 .halg.base = {
1653 .cra_name = "sha384",
1654 .cra_driver_name = "omap-sha384",
1655 .cra_priority = 400,
1656 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1657 CRYPTO_ALG_ASYNC |
1658 CRYPTO_ALG_NEED_FALLBACK,
1659 .cra_blocksize = SHA384_BLOCK_SIZE,
1660 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1661 .cra_alignmask = OMAP_ALIGN_MASK,
1662 .cra_module = THIS_MODULE,
1663 .cra_init = omap_sham_cra_init,
1664 .cra_exit = omap_sham_cra_exit,
1665 }
1666 },
1667 {
1668 .init = omap_sham_init,
1669 .update = omap_sham_update,
1670 .final = omap_sham_final,
1671 .finup = omap_sham_finup,
1672 .digest = omap_sham_digest,
1673 .halg.digestsize = SHA512_DIGEST_SIZE,
1674 .halg.base = {
1675 .cra_name = "sha512",
1676 .cra_driver_name = "omap-sha512",
1677 .cra_priority = 400,
1678 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1679 CRYPTO_ALG_ASYNC |
1680 CRYPTO_ALG_NEED_FALLBACK,
1681 .cra_blocksize = SHA512_BLOCK_SIZE,
1682 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1683 .cra_alignmask = OMAP_ALIGN_MASK,
1684 .cra_module = THIS_MODULE,
1685 .cra_init = omap_sham_cra_init,
1686 .cra_exit = omap_sham_cra_exit,
1687 }
1688 },
1689 {
1690 .init = omap_sham_init,
1691 .update = omap_sham_update,
1692 .final = omap_sham_final,
1693 .finup = omap_sham_finup,
1694 .digest = omap_sham_digest,
1695 .setkey = omap_sham_setkey,
1696 .halg.digestsize = SHA384_DIGEST_SIZE,
1697 .halg.base = {
1698 .cra_name = "hmac(sha384)",
1699 .cra_driver_name = "omap-hmac-sha384",
1700 .cra_priority = 400,
1701 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1702 CRYPTO_ALG_ASYNC |
1703 CRYPTO_ALG_NEED_FALLBACK,
1704 .cra_blocksize = SHA384_BLOCK_SIZE,
1705 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1706 sizeof(struct omap_sham_hmac_ctx),
1707 .cra_alignmask = OMAP_ALIGN_MASK,
1708 .cra_module = THIS_MODULE,
1709 .cra_init = omap_sham_cra_sha384_init,
1710 .cra_exit = omap_sham_cra_exit,
1711 }
1712 },
1713 {
1714 .init = omap_sham_init,
1715 .update = omap_sham_update,
1716 .final = omap_sham_final,
1717 .finup = omap_sham_finup,
1718 .digest = omap_sham_digest,
1719 .setkey = omap_sham_setkey,
1720 .halg.digestsize = SHA512_DIGEST_SIZE,
1721 .halg.base = {
1722 .cra_name = "hmac(sha512)",
1723 .cra_driver_name = "omap-hmac-sha512",
1724 .cra_priority = 400,
1725 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1726 CRYPTO_ALG_ASYNC |
1727 CRYPTO_ALG_NEED_FALLBACK,
1728 .cra_blocksize = SHA512_BLOCK_SIZE,
1729 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1730 sizeof(struct omap_sham_hmac_ctx),
1731 .cra_alignmask = OMAP_ALIGN_MASK,
1732 .cra_module = THIS_MODULE,
1733 .cra_init = omap_sham_cra_sha512_init,
1734 .cra_exit = omap_sham_cra_exit,
1735 }
1736 },
1737 };
1738
1739 static void omap_sham_done_task(unsigned long data)
1740 {
1741 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1742 int err = 0;
1743
1744 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1745 omap_sham_handle_queue(dd, NULL);
1746 return;
1747 }
1748
1749 if (test_bit(FLAGS_CPU, &dd->flags)) {
1750 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1751 goto finish;
1752 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1753 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1754 omap_sham_update_dma_stop(dd);
1755 if (dd->err) {
1756 err = dd->err;
1757 goto finish;
1758 }
1759 }
1760 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1761 /* hash or semi-hash ready */
1762 clear_bit(FLAGS_DMA_READY, &dd->flags);
1763 goto finish;
1764 }
1765 }
1766
1767 return;
1768
1769 finish:
1770 dev_dbg(dd->dev, "update done: err: %d\n", err);
1771 /* finish curent request */
1772 omap_sham_finish_req(dd->req, err);
1773
1774 /* If we are not busy, process next req */
1775 if (!test_bit(FLAGS_BUSY, &dd->flags))
1776 omap_sham_handle_queue(dd, NULL);
1777 }
1778
1779 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1780 {
1781 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1782 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1783 } else {
1784 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1785 tasklet_schedule(&dd->done_task);
1786 }
1787
1788 return IRQ_HANDLED;
1789 }
1790
1791 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1792 {
1793 struct omap_sham_dev *dd = dev_id;
1794
1795 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1796 /* final -> allow device to go to power-saving mode */
1797 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1798
1799 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1800 SHA_REG_CTRL_OUTPUT_READY);
1801 omap_sham_read(dd, SHA_REG_CTRL);
1802
1803 return omap_sham_irq_common(dd);
1804 }
1805
1806 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1807 {
1808 struct omap_sham_dev *dd = dev_id;
1809
1810 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1811
1812 return omap_sham_irq_common(dd);
1813 }
1814
1815 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1816 {
1817 .algs_list = algs_sha1_md5,
1818 .size = ARRAY_SIZE(algs_sha1_md5),
1819 },
1820 };
1821
1822 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1823 .algs_info = omap_sham_algs_info_omap2,
1824 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1825 .flags = BIT(FLAGS_BE32_SHA1),
1826 .digest_size = SHA1_DIGEST_SIZE,
1827 .copy_hash = omap_sham_copy_hash_omap2,
1828 .write_ctrl = omap_sham_write_ctrl_omap2,
1829 .trigger = omap_sham_trigger_omap2,
1830 .poll_irq = omap_sham_poll_irq_omap2,
1831 .intr_hdlr = omap_sham_irq_omap2,
1832 .idigest_ofs = 0x00,
1833 .din_ofs = 0x1c,
1834 .digcnt_ofs = 0x14,
1835 .rev_ofs = 0x5c,
1836 .mask_ofs = 0x60,
1837 .sysstatus_ofs = 0x64,
1838 .major_mask = 0xf0,
1839 .major_shift = 4,
1840 .minor_mask = 0x0f,
1841 .minor_shift = 0,
1842 };
1843
1844 #ifdef CONFIG_OF
1845 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1846 {
1847 .algs_list = algs_sha1_md5,
1848 .size = ARRAY_SIZE(algs_sha1_md5),
1849 },
1850 {
1851 .algs_list = algs_sha224_sha256,
1852 .size = ARRAY_SIZE(algs_sha224_sha256),
1853 },
1854 };
1855
1856 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1857 .algs_info = omap_sham_algs_info_omap4,
1858 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1859 .flags = BIT(FLAGS_AUTO_XOR),
1860 .digest_size = SHA256_DIGEST_SIZE,
1861 .copy_hash = omap_sham_copy_hash_omap4,
1862 .write_ctrl = omap_sham_write_ctrl_omap4,
1863 .trigger = omap_sham_trigger_omap4,
1864 .poll_irq = omap_sham_poll_irq_omap4,
1865 .intr_hdlr = omap_sham_irq_omap4,
1866 .idigest_ofs = 0x020,
1867 .odigest_ofs = 0x0,
1868 .din_ofs = 0x080,
1869 .digcnt_ofs = 0x040,
1870 .rev_ofs = 0x100,
1871 .mask_ofs = 0x110,
1872 .sysstatus_ofs = 0x114,
1873 .mode_ofs = 0x44,
1874 .length_ofs = 0x48,
1875 .major_mask = 0x0700,
1876 .major_shift = 8,
1877 .minor_mask = 0x003f,
1878 .minor_shift = 0,
1879 };
1880
1881 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1882 {
1883 .algs_list = algs_sha1_md5,
1884 .size = ARRAY_SIZE(algs_sha1_md5),
1885 },
1886 {
1887 .algs_list = algs_sha224_sha256,
1888 .size = ARRAY_SIZE(algs_sha224_sha256),
1889 },
1890 {
1891 .algs_list = algs_sha384_sha512,
1892 .size = ARRAY_SIZE(algs_sha384_sha512),
1893 },
1894 };
1895
1896 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1897 .algs_info = omap_sham_algs_info_omap5,
1898 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1899 .flags = BIT(FLAGS_AUTO_XOR),
1900 .digest_size = SHA512_DIGEST_SIZE,
1901 .copy_hash = omap_sham_copy_hash_omap4,
1902 .write_ctrl = omap_sham_write_ctrl_omap4,
1903 .trigger = omap_sham_trigger_omap4,
1904 .poll_irq = omap_sham_poll_irq_omap4,
1905 .intr_hdlr = omap_sham_irq_omap4,
1906 .idigest_ofs = 0x240,
1907 .odigest_ofs = 0x200,
1908 .din_ofs = 0x080,
1909 .digcnt_ofs = 0x280,
1910 .rev_ofs = 0x100,
1911 .mask_ofs = 0x110,
1912 .sysstatus_ofs = 0x114,
1913 .mode_ofs = 0x284,
1914 .length_ofs = 0x288,
1915 .major_mask = 0x0700,
1916 .major_shift = 8,
1917 .minor_mask = 0x003f,
1918 .minor_shift = 0,
1919 };
1920
1921 static const struct of_device_id omap_sham_of_match[] = {
1922 {
1923 .compatible = "ti,omap2-sham",
1924 .data = &omap_sham_pdata_omap2,
1925 },
1926 {
1927 .compatible = "ti,omap3-sham",
1928 .data = &omap_sham_pdata_omap2,
1929 },
1930 {
1931 .compatible = "ti,omap4-sham",
1932 .data = &omap_sham_pdata_omap4,
1933 },
1934 {
1935 .compatible = "ti,omap5-sham",
1936 .data = &omap_sham_pdata_omap5,
1937 },
1938 {},
1939 };
1940 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1941
1942 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1943 struct device *dev, struct resource *res)
1944 {
1945 struct device_node *node = dev->of_node;
1946 const struct of_device_id *match;
1947 int err = 0;
1948
1949 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1950 if (!match) {
1951 dev_err(dev, "no compatible OF match\n");
1952 err = -EINVAL;
1953 goto err;
1954 }
1955
1956 err = of_address_to_resource(node, 0, res);
1957 if (err < 0) {
1958 dev_err(dev, "can't translate OF node address\n");
1959 err = -EINVAL;
1960 goto err;
1961 }
1962
1963 dd->irq = irq_of_parse_and_map(node, 0);
1964 if (!dd->irq) {
1965 dev_err(dev, "can't translate OF irq value\n");
1966 err = -EINVAL;
1967 goto err;
1968 }
1969
1970 dd->pdata = match->data;
1971
1972 err:
1973 return err;
1974 }
1975 #else
1976 static const struct of_device_id omap_sham_of_match[] = {
1977 {},
1978 };
1979
1980 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1981 struct device *dev, struct resource *res)
1982 {
1983 return -EINVAL;
1984 }
1985 #endif
1986
1987 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1988 struct platform_device *pdev, struct resource *res)
1989 {
1990 struct device *dev = &pdev->dev;
1991 struct resource *r;
1992 int err = 0;
1993
1994 /* Get the base address */
1995 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1996 if (!r) {
1997 dev_err(dev, "no MEM resource info\n");
1998 err = -ENODEV;
1999 goto err;
2000 }
2001 memcpy(res, r, sizeof(*res));
2002
2003 /* Get the IRQ */
2004 dd->irq = platform_get_irq(pdev, 0);
2005 if (dd->irq < 0) {
2006 dev_err(dev, "no IRQ resource info\n");
2007 err = dd->irq;
2008 goto err;
2009 }
2010
2011 /* Only OMAP2/3 can be non-DT */
2012 dd->pdata = &omap_sham_pdata_omap2;
2013
2014 err:
2015 return err;
2016 }
2017
2018 static int omap_sham_probe(struct platform_device *pdev)
2019 {
2020 struct omap_sham_dev *dd;
2021 struct device *dev = &pdev->dev;
2022 struct resource res;
2023 dma_cap_mask_t mask;
2024 int err, i, j;
2025 u32 rev;
2026
2027 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2028 if (dd == NULL) {
2029 dev_err(dev, "unable to alloc data struct.\n");
2030 err = -ENOMEM;
2031 goto data_err;
2032 }
2033 dd->dev = dev;
2034 platform_set_drvdata(pdev, dd);
2035
2036 INIT_LIST_HEAD(&dd->list);
2037 spin_lock_init(&dd->lock);
2038 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2039 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2040
2041 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2042 omap_sham_get_res_pdev(dd, pdev, &res);
2043 if (err)
2044 goto data_err;
2045
2046 dd->io_base = devm_ioremap_resource(dev, &res);
2047 if (IS_ERR(dd->io_base)) {
2048 err = PTR_ERR(dd->io_base);
2049 goto data_err;
2050 }
2051 dd->phys_base = res.start;
2052
2053 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2054 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2055 if (err) {
2056 dev_err(dev, "unable to request irq %d, err = %d\n",
2057 dd->irq, err);
2058 goto data_err;
2059 }
2060
2061 dma_cap_zero(mask);
2062 dma_cap_set(DMA_SLAVE, mask);
2063
2064 dd->dma_lch = dma_request_chan(dev, "rx");
2065 if (IS_ERR(dd->dma_lch)) {
2066 err = PTR_ERR(dd->dma_lch);
2067 if (err == -EPROBE_DEFER)
2068 goto data_err;
2069
2070 dd->polling_mode = 1;
2071 dev_dbg(dev, "using polling mode instead of dma\n");
2072 }
2073
2074 dd->flags |= dd->pdata->flags;
2075
2076 pm_runtime_use_autosuspend(dev);
2077 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2078
2079 pm_runtime_enable(dev);
2080 pm_runtime_irq_safe(dev);
2081
2082 err = pm_runtime_get_sync(dev);
2083 if (err < 0) {
2084 dev_err(dev, "failed to get sync: %d\n", err);
2085 goto err_pm;
2086 }
2087
2088 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2089 pm_runtime_put_sync(&pdev->dev);
2090
2091 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2092 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2093 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2094
2095 spin_lock(&sham.lock);
2096 list_add_tail(&dd->list, &sham.dev_list);
2097 spin_unlock(&sham.lock);
2098
2099 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2100 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2101 struct ahash_alg *alg;
2102
2103 alg = &dd->pdata->algs_info[i].algs_list[j];
2104 alg->export = omap_sham_export;
2105 alg->import = omap_sham_import;
2106 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2107 BUFLEN;
2108 err = crypto_register_ahash(alg);
2109 if (err)
2110 goto err_algs;
2111
2112 dd->pdata->algs_info[i].registered++;
2113 }
2114 }
2115
2116 return 0;
2117
2118 err_algs:
2119 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2120 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2121 crypto_unregister_ahash(
2122 &dd->pdata->algs_info[i].algs_list[j]);
2123 err_pm:
2124 pm_runtime_disable(dev);
2125 if (!dd->polling_mode)
2126 dma_release_channel(dd->dma_lch);
2127 data_err:
2128 dev_err(dev, "initialization failed.\n");
2129
2130 return err;
2131 }
2132
2133 static int omap_sham_remove(struct platform_device *pdev)
2134 {
2135 static struct omap_sham_dev *dd;
2136 int i, j;
2137
2138 dd = platform_get_drvdata(pdev);
2139 if (!dd)
2140 return -ENODEV;
2141 spin_lock(&sham.lock);
2142 list_del(&dd->list);
2143 spin_unlock(&sham.lock);
2144 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2145 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2146 crypto_unregister_ahash(
2147 &dd->pdata->algs_info[i].algs_list[j]);
2148 tasklet_kill(&dd->done_task);
2149 pm_runtime_disable(&pdev->dev);
2150
2151 if (!dd->polling_mode)
2152 dma_release_channel(dd->dma_lch);
2153
2154 return 0;
2155 }
2156
2157 #ifdef CONFIG_PM_SLEEP
2158 static int omap_sham_suspend(struct device *dev)
2159 {
2160 pm_runtime_put_sync(dev);
2161 return 0;
2162 }
2163
2164 static int omap_sham_resume(struct device *dev)
2165 {
2166 int err = pm_runtime_get_sync(dev);
2167 if (err < 0) {
2168 dev_err(dev, "failed to get sync: %d\n", err);
2169 return err;
2170 }
2171 return 0;
2172 }
2173 #endif
2174
2175 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2176
2177 static struct platform_driver omap_sham_driver = {
2178 .probe = omap_sham_probe,
2179 .remove = omap_sham_remove,
2180 .driver = {
2181 .name = "omap-sham",
2182 .pm = &omap_sham_pm_ops,
2183 .of_match_table = omap_sham_of_match,
2184 },
2185 };
2186
2187 module_platform_driver(omap_sham_driver);
2188
2189 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2190 MODULE_LICENSE("GPL v2");
2191 MODULE_AUTHOR("Dmitry Kasatkin");
2192 MODULE_ALIAS("platform:omap-sham");
Linux with added FPC-III support