?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
bloba336754698f87682ab85dcb4eb346d1922392c1b
1 /*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/component.h>
18 #include <linux/fence.h>
19 #include <linux/moduleparam.h>
20 #include <linux/of_device.h>
21 #include "etnaviv_dump.h"
22 #include "etnaviv_gpu.h"
23 #include "etnaviv_gem.h"
24 #include "etnaviv_mmu.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33 };
34
35 static bool etnaviv_dump_core = true;
36 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
37
38 /*
39 * Driver functions:
40 */
41
42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
43 {
44 switch (param) {
45 case ETNAVIV_PARAM_GPU_MODEL:
46 *value = gpu->identity.model;
47 break;
48
49 case ETNAVIV_PARAM_GPU_REVISION:
50 *value = gpu->identity.revision;
51 break;
52
53 case ETNAVIV_PARAM_GPU_FEATURES_0:
54 *value = gpu->identity.features;
55 break;
56
57 case ETNAVIV_PARAM_GPU_FEATURES_1:
58 *value = gpu->identity.minor_features0;
59 break;
60
61 case ETNAVIV_PARAM_GPU_FEATURES_2:
62 *value = gpu->identity.minor_features1;
63 break;
64
65 case ETNAVIV_PARAM_GPU_FEATURES_3:
66 *value = gpu->identity.minor_features2;
67 break;
68
69 case ETNAVIV_PARAM_GPU_FEATURES_4:
70 *value = gpu->identity.minor_features3;
71 break;
72
73 case ETNAVIV_PARAM_GPU_FEATURES_5:
74 *value = gpu->identity.minor_features4;
75 break;
76
77 case ETNAVIV_PARAM_GPU_FEATURES_6:
78 *value = gpu->identity.minor_features5;
79 break;
80
81 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
82 *value = gpu->identity.stream_count;
83 break;
84
85 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
86 *value = gpu->identity.register_max;
87 break;
88
89 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
90 *value = gpu->identity.thread_count;
91 break;
92
93 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
94 *value = gpu->identity.vertex_cache_size;
95 break;
96
97 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
98 *value = gpu->identity.shader_core_count;
99 break;
100
101 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
102 *value = gpu->identity.pixel_pipes;
103 break;
104
105 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
106 *value = gpu->identity.vertex_output_buffer_size;
107 break;
108
109 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
110 *value = gpu->identity.buffer_size;
111 break;
112
113 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
114 *value = gpu->identity.instruction_count;
115 break;
116
117 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
118 *value = gpu->identity.num_constants;
119 break;
120
121 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
122 *value = gpu->identity.varyings_count;
123 break;
124
125 default:
126 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
127 return -EINVAL;
128 }
129
130 return 0;
131 }
132
133
134 #define etnaviv_is_model_rev(gpu, mod, rev) \
135 ((gpu)->identity.model == chipModel_##mod && \
136 (gpu)->identity.revision == rev)
137 #define etnaviv_field(val, field) \
138 (((val) & field##__MASK) >> field##__SHIFT)
139
140 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
141 {
142 if (gpu->identity.minor_features0 &
143 chipMinorFeatures0_MORE_MINOR_FEATURES) {
144 u32 specs[4];
145 unsigned int streams;
146
147 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
148 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
149 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
150 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
151
152 gpu->identity.stream_count = etnaviv_field(specs[0],
153 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
154 gpu->identity.register_max = etnaviv_field(specs[0],
155 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
156 gpu->identity.thread_count = etnaviv_field(specs[0],
157 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
158 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
159 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
160 gpu->identity.shader_core_count = etnaviv_field(specs[0],
161 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
162 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
163 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
164 gpu->identity.vertex_output_buffer_size =
165 etnaviv_field(specs[0],
166 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
167
168 gpu->identity.buffer_size = etnaviv_field(specs[1],
169 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
170 gpu->identity.instruction_count = etnaviv_field(specs[1],
171 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
172 gpu->identity.num_constants = etnaviv_field(specs[1],
173 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
174
175 gpu->identity.varyings_count = etnaviv_field(specs[2],
176 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
177
178 /* This overrides the value from older register if non-zero */
179 streams = etnaviv_field(specs[3],
180 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
181 if (streams)
182 gpu->identity.stream_count = streams;
183 }
184
185 /* Fill in the stream count if not specified */
186 if (gpu->identity.stream_count == 0) {
187 if (gpu->identity.model >= 0x1000)
188 gpu->identity.stream_count = 4;
189 else
190 gpu->identity.stream_count = 1;
191 }
192
193 /* Convert the register max value */
194 if (gpu->identity.register_max)
195 gpu->identity.register_max = 1 << gpu->identity.register_max;
196 else if (gpu->identity.model == chipModel_GC400)
197 gpu->identity.register_max = 32;
198 else
199 gpu->identity.register_max = 64;
200
201 /* Convert thread count */
202 if (gpu->identity.thread_count)
203 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
204 else if (gpu->identity.model == chipModel_GC400)
205 gpu->identity.thread_count = 64;
206 else if (gpu->identity.model == chipModel_GC500 ||
207 gpu->identity.model == chipModel_GC530)
208 gpu->identity.thread_count = 128;
209 else
210 gpu->identity.thread_count = 256;
211
212 if (gpu->identity.vertex_cache_size == 0)
213 gpu->identity.vertex_cache_size = 8;
214
215 if (gpu->identity.shader_core_count == 0) {
216 if (gpu->identity.model >= 0x1000)
217 gpu->identity.shader_core_count = 2;
218 else
219 gpu->identity.shader_core_count = 1;
220 }
221
222 if (gpu->identity.pixel_pipes == 0)
223 gpu->identity.pixel_pipes = 1;
224
225 /* Convert virtex buffer size */
226 if (gpu->identity.vertex_output_buffer_size) {
227 gpu->identity.vertex_output_buffer_size =
228 1 << gpu->identity.vertex_output_buffer_size;
229 } else if (gpu->identity.model == chipModel_GC400) {
230 if (gpu->identity.revision < 0x4000)
231 gpu->identity.vertex_output_buffer_size = 512;
232 else if (gpu->identity.revision < 0x4200)
233 gpu->identity.vertex_output_buffer_size = 256;
234 else
235 gpu->identity.vertex_output_buffer_size = 128;
236 } else {
237 gpu->identity.vertex_output_buffer_size = 512;
238 }
239
240 switch (gpu->identity.instruction_count) {
241 case 0:
242 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
243 gpu->identity.model == chipModel_GC880)
244 gpu->identity.instruction_count = 512;
245 else
246 gpu->identity.instruction_count = 256;
247 break;
248
249 case 1:
250 gpu->identity.instruction_count = 1024;
251 break;
252
253 case 2:
254 gpu->identity.instruction_count = 2048;
255 break;
256
257 default:
258 gpu->identity.instruction_count = 256;
259 break;
260 }
261
262 if (gpu->identity.num_constants == 0)
263 gpu->identity.num_constants = 168;
264
265 if (gpu->identity.varyings_count == 0) {
266 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
267 gpu->identity.varyings_count = 12;
268 else
269 gpu->identity.varyings_count = 8;
270 }
271
272 /*
273 * For some cores, two varyings are consumed for position, so the
274 * maximum varying count needs to be reduced by one.
275 */
276 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
277 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
278 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
279 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
280 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
281 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
282 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
283 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
284 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
285 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
286 etnaviv_is_model_rev(gpu, GC880, 0x5106))
287 gpu->identity.varyings_count -= 1;
288 }
289
290 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
291 {
292 u32 chipIdentity;
293
294 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
295
296 /* Special case for older graphic cores. */
297 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
298 gpu->identity.model = chipModel_GC500;
299 gpu->identity.revision = etnaviv_field(chipIdentity,
300 VIVS_HI_CHIP_IDENTITY_REVISION);
301 } else {
302
303 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
304 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
305
306 /*
307 * !!!! HACK ALERT !!!!
308 * Because people change device IDs without letting software
309 * know about it - here is the hack to make it all look the
310 * same. Only for GC400 family.
311 */
312 if ((gpu->identity.model & 0xff00) == 0x0400 &&
313 gpu->identity.model != chipModel_GC420) {
314 gpu->identity.model = gpu->identity.model & 0x0400;
315 }
316
317 /* Another special case */
318 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
319 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
320 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
321
322 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
323 /*
324 * This IP has an ECO; put the correct
325 * revision in it.
326 */
327 gpu->identity.revision = 0x1051;
328 }
329 }
330
331 /*
332 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
333 * reality it's just a re-branded GC3000. We can identify this
334 * core by the upper half of the revision register being all 1.
335 * Fix model/rev here, so all other places can refer to this
336 * core by its real identity.
337 */
338 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
339 gpu->identity.model = chipModel_GC3000;
340 gpu->identity.revision &= 0xffff;
341 }
342 }
343
344 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
345 gpu->identity.model, gpu->identity.revision);
346
347 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
348
349 /* Disable fast clear on GC700. */
350 if (gpu->identity.model == chipModel_GC700)
351 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
352
353 if ((gpu->identity.model == chipModel_GC500 &&
354 gpu->identity.revision < 2) ||
355 (gpu->identity.model == chipModel_GC300 &&
356 gpu->identity.revision < 0x2000)) {
357
358 /*
359 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
360 * registers.
361 */
362 gpu->identity.minor_features0 = 0;
363 gpu->identity.minor_features1 = 0;
364 gpu->identity.minor_features2 = 0;
365 gpu->identity.minor_features3 = 0;
366 gpu->identity.minor_features4 = 0;
367 gpu->identity.minor_features5 = 0;
368 } else
369 gpu->identity.minor_features0 =
370 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
371
372 if (gpu->identity.minor_features0 &
373 chipMinorFeatures0_MORE_MINOR_FEATURES) {
374 gpu->identity.minor_features1 =
375 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
376 gpu->identity.minor_features2 =
377 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
378 gpu->identity.minor_features3 =
379 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
380 gpu->identity.minor_features4 =
381 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
382 gpu->identity.minor_features5 =
383 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
384 }
385
386 /* GC600 idle register reports zero bits where modules aren't present */
387 if (gpu->identity.model == chipModel_GC600) {
388 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
389 VIVS_HI_IDLE_STATE_RA |
390 VIVS_HI_IDLE_STATE_SE |
391 VIVS_HI_IDLE_STATE_PA |
392 VIVS_HI_IDLE_STATE_SH |
393 VIVS_HI_IDLE_STATE_PE |
394 VIVS_HI_IDLE_STATE_DE |
395 VIVS_HI_IDLE_STATE_FE;
396 } else {
397 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
398 }
399
400 etnaviv_hw_specs(gpu);
401 }
402
403 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
404 {
405 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
406 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
407 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
408 }
409
410 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
411 {
412 u32 control, idle;
413 unsigned long timeout;
414 bool failed = true;
415
416 /* TODO
417 *
418 * - clock gating
419 * - puls eater
420 * - what about VG?
421 */
422
423 /* We hope that the GPU resets in under one second */
424 timeout = jiffies + msecs_to_jiffies(1000);
425
426 while (time_is_after_jiffies(timeout)) {
427 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
428 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
429
430 /* enable clock */
431 etnaviv_gpu_load_clock(gpu, control);
432
433 /* Wait for stable clock. Vivante's code waited for 1ms */
434 usleep_range(1000, 10000);
435
436 /* isolate the GPU. */
437 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
438 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
439
440 /* set soft reset. */
441 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
442 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
443
444 /* wait for reset. */
445 msleep(1);
446
447 /* reset soft reset bit. */
448 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
449 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
450
451 /* reset GPU isolation. */
452 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
453 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
454
455 /* read idle register. */
456 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
457
458 /* try reseting again if FE it not idle */
459 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
460 dev_dbg(gpu->dev, "FE is not idle\n");
461 continue;
462 }
463
464 /* read reset register. */
465 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
466
467 /* is the GPU idle? */
468 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
469 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
470 dev_dbg(gpu->dev, "GPU is not idle\n");
471 continue;
472 }
473
474 failed = false;
475 break;
476 }
477
478 if (failed) {
479 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
480 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
481
482 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
483 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
484 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
485 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
486
487 return -EBUSY;
488 }
489
490 /* We rely on the GPU running, so program the clock */
491 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
492 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
493
494 /* enable clock */
495 etnaviv_gpu_load_clock(gpu, control);
496
497 return 0;
498 }
499
500 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
501 {
502 u32 pmc, ppc;
503
504 /* enable clock gating */
505 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
506 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
507
508 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
509 if (gpu->identity.revision == 0x4301 ||
510 gpu->identity.revision == 0x4302)
511 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
512
513 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
514
515 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
516
517 /* Disable PA clock gating for GC400+ except for GC420 */
518 if (gpu->identity.model >= chipModel_GC400 &&
519 gpu->identity.model != chipModel_GC420)
520 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
521
522 /*
523 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
524 * present without a bug fix.
525 */
526 if (gpu->identity.revision < 0x5000 &&
527 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
528 !(gpu->identity.minor_features1 &
529 chipMinorFeatures1_DISABLE_PE_GATING))
530 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
531
532 if (gpu->identity.revision < 0x5422)
533 pmc |= BIT(15); /* Unknown bit */
534
535 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
536 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
537
538 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
539 }
540
541 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
542 {
543 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
544 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
545 VIVS_FE_COMMAND_CONTROL_ENABLE |
546 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
547 }
548
549 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
550 {
551 u16 prefetch;
552
553 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
554 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
555 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
556 u32 mc_memory_debug;
557
558 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
559
560 if (gpu->identity.revision == 0x5007)
561 mc_memory_debug |= 0x0c;
562 else
563 mc_memory_debug |= 0x08;
564
565 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
566 }
567
568 /* enable module-level clock gating */
569 etnaviv_gpu_enable_mlcg(gpu);
570
571 /*
572 * Update GPU AXI cache atttribute to "cacheable, no allocate".
573 * This is necessary to prevent the iMX6 SoC locking up.
574 */
575 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
576 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
577 VIVS_HI_AXI_CONFIG_ARCACHE(2));
578
579 /* GC2000 rev 5108 needs a special bus config */
580 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
581 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
582 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
583 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
584 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
585 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
586 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
587 }
588
589 /* setup the MMU */
590 etnaviv_iommu_restore(gpu);
591
592 /* Start command processor */
593 prefetch = etnaviv_buffer_init(gpu);
594
595 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
596 etnaviv_gpu_start_fe(gpu, etnaviv_iommu_get_cmdbuf_va(gpu, gpu->buffer),
597 prefetch);
598 }
599
600 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
601 {
602 int ret, i;
603
604 ret = pm_runtime_get_sync(gpu->dev);
605 if (ret < 0) {
606 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
607 return ret;
608 }
609
610 etnaviv_hw_identify(gpu);
611
612 if (gpu->identity.model == 0) {
613 dev_err(gpu->dev, "Unknown GPU model\n");
614 ret = -ENXIO;
615 goto fail;
616 }
617
618 /* Exclude VG cores with FE2.0 */
619 if (gpu->identity.features & chipFeatures_PIPE_VG &&
620 gpu->identity.features & chipFeatures_FE20) {
621 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
622 ret = -ENXIO;
623 goto fail;
624 }
625
626 /*
627 * Set the GPU linear window to be at the end of the DMA window, where
628 * the CMA area is likely to reside. This ensures that we are able to
629 * map the command buffers while having the linear window overlap as
630 * much RAM as possible, so we can optimize mappings for other buffers.
631 *
632 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
633 * to different views of the memory on the individual engines.
634 */
635 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
636 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
637 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
638 if (dma_mask < PHYS_OFFSET + SZ_2G)
639 gpu->memory_base = PHYS_OFFSET;
640 else
641 gpu->memory_base = dma_mask - SZ_2G + 1;
642 }
643
644 ret = etnaviv_hw_reset(gpu);
645 if (ret) {
646 dev_err(gpu->dev, "GPU reset failed\n");
647 goto fail;
648 }
649
650 gpu->mmu = etnaviv_iommu_new(gpu);
651 if (IS_ERR(gpu->mmu)) {
652 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
653 ret = PTR_ERR(gpu->mmu);
654 goto fail;
655 }
656
657 /* Create buffer: */
658 gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
659 if (!gpu->buffer) {
660 ret = -ENOMEM;
661 dev_err(gpu->dev, "could not create command buffer\n");
662 goto destroy_iommu;
663 }
664
665 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
666 gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
667 ret = -EINVAL;
668 dev_err(gpu->dev,
669 "command buffer outside valid memory window\n");
670 goto free_buffer;
671 }
672
673 /* Setup event management */
674 spin_lock_init(&gpu->event_spinlock);
675 init_completion(&gpu->event_free);
676 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
677 gpu->event[i].used = false;
678 complete(&gpu->event_free);
679 }
680
681 /* Now program the hardware */
682 mutex_lock(&gpu->lock);
683 etnaviv_gpu_hw_init(gpu);
684 gpu->exec_state = -1;
685 mutex_unlock(&gpu->lock);
686
687 pm_runtime_mark_last_busy(gpu->dev);
688 pm_runtime_put_autosuspend(gpu->dev);
689
690 return 0;
691
692 free_buffer:
693 etnaviv_gpu_cmdbuf_free(gpu->buffer);
694 gpu->buffer = NULL;
695 destroy_iommu:
696 etnaviv_iommu_destroy(gpu->mmu);
697 gpu->mmu = NULL;
698 fail:
699 pm_runtime_mark_last_busy(gpu->dev);
700 pm_runtime_put_autosuspend(gpu->dev);
701
702 return ret;
703 }
704
705 #ifdef CONFIG_DEBUG_FS
706 struct dma_debug {
707 u32 address[2];
708 u32 state[2];
709 };
710
711 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
712 {
713 u32 i;
714
715 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
716 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
717
718 for (i = 0; i < 500; i++) {
719 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
720 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
721
722 if (debug->address[0] != debug->address[1])
723 break;
724
725 if (debug->state[0] != debug->state[1])
726 break;
727 }
728 }
729
730 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
731 {
732 struct dma_debug debug;
733 u32 dma_lo, dma_hi, axi, idle;
734 int ret;
735
736 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
737
738 ret = pm_runtime_get_sync(gpu->dev);
739 if (ret < 0)
740 return ret;
741
742 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
743 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
744 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
745 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
746
747 verify_dma(gpu, &debug);
748
749 seq_puts(m, "\tfeatures\n");
750 seq_printf(m, "\t minor_features0: 0x%08x\n",
751 gpu->identity.minor_features0);
752 seq_printf(m, "\t minor_features1: 0x%08x\n",
753 gpu->identity.minor_features1);
754 seq_printf(m, "\t minor_features2: 0x%08x\n",
755 gpu->identity.minor_features2);
756 seq_printf(m, "\t minor_features3: 0x%08x\n",
757 gpu->identity.minor_features3);
758 seq_printf(m, "\t minor_features4: 0x%08x\n",
759 gpu->identity.minor_features4);
760 seq_printf(m, "\t minor_features5: 0x%08x\n",
761 gpu->identity.minor_features5);
762
763 seq_puts(m, "\tspecs\n");
764 seq_printf(m, "\t stream_count: %d\n",
765 gpu->identity.stream_count);
766 seq_printf(m, "\t register_max: %d\n",
767 gpu->identity.register_max);
768 seq_printf(m, "\t thread_count: %d\n",
769 gpu->identity.thread_count);
770 seq_printf(m, "\t vertex_cache_size: %d\n",
771 gpu->identity.vertex_cache_size);
772 seq_printf(m, "\t shader_core_count: %d\n",
773 gpu->identity.shader_core_count);
774 seq_printf(m, "\t pixel_pipes: %d\n",
775 gpu->identity.pixel_pipes);
776 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
777 gpu->identity.vertex_output_buffer_size);
778 seq_printf(m, "\t buffer_size: %d\n",
779 gpu->identity.buffer_size);
780 seq_printf(m, "\t instruction_count: %d\n",
781 gpu->identity.instruction_count);
782 seq_printf(m, "\t num_constants: %d\n",
783 gpu->identity.num_constants);
784 seq_printf(m, "\t varyings_count: %d\n",
785 gpu->identity.varyings_count);
786
787 seq_printf(m, "\taxi: 0x%08x\n", axi);
788 seq_printf(m, "\tidle: 0x%08x\n", idle);
789 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
790 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
791 seq_puts(m, "\t FE is not idle\n");
792 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
793 seq_puts(m, "\t DE is not idle\n");
794 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
795 seq_puts(m, "\t PE is not idle\n");
796 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
797 seq_puts(m, "\t SH is not idle\n");
798 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
799 seq_puts(m, "\t PA is not idle\n");
800 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
801 seq_puts(m, "\t SE is not idle\n");
802 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
803 seq_puts(m, "\t RA is not idle\n");
804 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
805 seq_puts(m, "\t TX is not idle\n");
806 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
807 seq_puts(m, "\t VG is not idle\n");
808 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
809 seq_puts(m, "\t IM is not idle\n");
810 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
811 seq_puts(m, "\t FP is not idle\n");
812 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
813 seq_puts(m, "\t TS is not idle\n");
814 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
815 seq_puts(m, "\t AXI low power mode\n");
816
817 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
818 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
819 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
820 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
821
822 seq_puts(m, "\tMC\n");
823 seq_printf(m, "\t read0: 0x%08x\n", read0);
824 seq_printf(m, "\t read1: 0x%08x\n", read1);
825 seq_printf(m, "\t write: 0x%08x\n", write);
826 }
827
828 seq_puts(m, "\tDMA ");
829
830 if (debug.address[0] == debug.address[1] &&
831 debug.state[0] == debug.state[1]) {
832 seq_puts(m, "seems to be stuck\n");
833 } else if (debug.address[0] == debug.address[1]) {
834 seq_puts(m, "address is constant\n");
835 } else {
836 seq_puts(m, "is running\n");
837 }
838
839 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
840 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
841 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
842 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
843 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
844 dma_lo, dma_hi);
845
846 ret = 0;
847
848 pm_runtime_mark_last_busy(gpu->dev);
849 pm_runtime_put_autosuspend(gpu->dev);
850
851 return ret;
852 }
853 #endif
854
855 /*
856 * Hangcheck detection for locked gpu:
857 */
858 static void recover_worker(struct work_struct *work)
859 {
860 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
861 recover_work);
862 unsigned long flags;
863 unsigned int i;
864
865 dev_err(gpu->dev, "hangcheck recover!\n");
866
867 if (pm_runtime_get_sync(gpu->dev) < 0)
868 return;
869
870 mutex_lock(&gpu->lock);
871
872 /* Only catch the first event, or when manually re-armed */
873 if (etnaviv_dump_core) {
874 etnaviv_core_dump(gpu);
875 etnaviv_dump_core = false;
876 }
877
878 etnaviv_hw_reset(gpu);
879
880 /* complete all events, the GPU won't do it after the reset */
881 spin_lock_irqsave(&gpu->event_spinlock, flags);
882 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
883 if (!gpu->event[i].used)
884 continue;
885 fence_signal(gpu->event[i].fence);
886 gpu->event[i].fence = NULL;
887 gpu->event[i].used = false;
888 complete(&gpu->event_free);
889 }
890 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
891 gpu->completed_fence = gpu->active_fence;
892
893 etnaviv_gpu_hw_init(gpu);
894 gpu->lastctx = NULL;
895 gpu->exec_state = -1;
896
897 mutex_unlock(&gpu->lock);
898 pm_runtime_mark_last_busy(gpu->dev);
899 pm_runtime_put_autosuspend(gpu->dev);
900
901 /* Retire the buffer objects in a work */
902 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
903 }
904
905 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
906 {
907 DBG("%s", dev_name(gpu->dev));
908 mod_timer(&gpu->hangcheck_timer,
909 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
910 }
911
912 static void hangcheck_handler(unsigned long data)
913 {
914 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
915 u32 fence = gpu->completed_fence;
916 bool progress = false;
917
918 if (fence != gpu->hangcheck_fence) {
919 gpu->hangcheck_fence = fence;
920 progress = true;
921 }
922
923 if (!progress) {
924 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
925 int change = dma_addr - gpu->hangcheck_dma_addr;
926
927 if (change < 0 || change > 16) {
928 gpu->hangcheck_dma_addr = dma_addr;
929 progress = true;
930 }
931 }
932
933 if (!progress && fence_after(gpu->active_fence, fence)) {
934 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
935 dev_err(gpu->dev, " completed fence: %u\n", fence);
936 dev_err(gpu->dev, " active fence: %u\n",
937 gpu->active_fence);
938 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
939 }
940
941 /* if still more pending work, reset the hangcheck timer: */
942 if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
943 hangcheck_timer_reset(gpu);
944 }
945
946 static void hangcheck_disable(struct etnaviv_gpu *gpu)
947 {
948 del_timer_sync(&gpu->hangcheck_timer);
949 cancel_work_sync(&gpu->recover_work);
950 }
951
952 /* fence object management */
953 struct etnaviv_fence {
954 struct etnaviv_gpu *gpu;
955 struct fence base;
956 };
957
958 static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
959 {
960 return container_of(fence, struct etnaviv_fence, base);
961 }
962
963 static const char *etnaviv_fence_get_driver_name(struct fence *fence)
964 {
965 return "etnaviv";
966 }
967
968 static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
969 {
970 struct etnaviv_fence *f = to_etnaviv_fence(fence);
971
972 return dev_name(f->gpu->dev);
973 }
974
975 static bool etnaviv_fence_enable_signaling(struct fence *fence)
976 {
977 return true;
978 }
979
980 static bool etnaviv_fence_signaled(struct fence *fence)
981 {
982 struct etnaviv_fence *f = to_etnaviv_fence(fence);
983
984 return fence_completed(f->gpu, f->base.seqno);
985 }
986
987 static void etnaviv_fence_release(struct fence *fence)
988 {
989 struct etnaviv_fence *f = to_etnaviv_fence(fence);
990
991 kfree_rcu(f, base.rcu);
992 }
993
994 static const struct fence_ops etnaviv_fence_ops = {
995 .get_driver_name = etnaviv_fence_get_driver_name,
996 .get_timeline_name = etnaviv_fence_get_timeline_name,
997 .enable_signaling = etnaviv_fence_enable_signaling,
998 .signaled = etnaviv_fence_signaled,
999 .wait = fence_default_wait,
1000 .release = etnaviv_fence_release,
1001 };
1002
1003 static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1004 {
1005 struct etnaviv_fence *f;
1006
1007 f = kzalloc(sizeof(*f), GFP_KERNEL);
1008 if (!f)
1009 return NULL;
1010
1011 f->gpu = gpu;
1012
1013 fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1014 gpu->fence_context, ++gpu->next_fence);
1015
1016 return &f->base;
1017 }
1018
1019 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1020 unsigned int context, bool exclusive)
1021 {
1022 struct reservation_object *robj = etnaviv_obj->resv;
1023 struct reservation_object_list *fobj;
1024 struct fence *fence;
1025 int i, ret;
1026
1027 if (!exclusive) {
1028 ret = reservation_object_reserve_shared(robj);
1029 if (ret)
1030 return ret;
1031 }
1032
1033 /*
1034 * If we have any shared fences, then the exclusive fence
1035 * should be ignored as it will already have been signalled.
1036 */
1037 fobj = reservation_object_get_list(robj);
1038 if (!fobj || fobj->shared_count == 0) {
1039 /* Wait on any existing exclusive fence which isn't our own */
1040 fence = reservation_object_get_excl(robj);
1041 if (fence && fence->context != context) {
1042 ret = fence_wait(fence, true);
1043 if (ret)
1044 return ret;
1045 }
1046 }
1047
1048 if (!exclusive || !fobj)
1049 return 0;
1050
1051 for (i = 0; i < fobj->shared_count; i++) {
1052 fence = rcu_dereference_protected(fobj->shared[i],
1053 reservation_object_held(robj));
1054 if (fence->context != context) {
1055 ret = fence_wait(fence, true);
1056 if (ret)
1057 return ret;
1058 }
1059 }
1060
1061 return 0;
1062 }
1063
1064 /*
1065 * event management:
1066 */
1067
1068 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1069 {
1070 unsigned long ret, flags;
1071 unsigned int i, event = ~0U;
1072
1073 ret = wait_for_completion_timeout(&gpu->event_free,
1074 msecs_to_jiffies(10 * 10000));
1075 if (!ret)
1076 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1077
1078 spin_lock_irqsave(&gpu->event_spinlock, flags);
1079
1080 /* find first free event */
1081 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1082 if (gpu->event[i].used == false) {
1083 gpu->event[i].used = true;
1084 event = i;
1085 break;
1086 }
1087 }
1088
1089 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1090
1091 return event;
1092 }
1093
1094 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1095 {
1096 unsigned long flags;
1097
1098 spin_lock_irqsave(&gpu->event_spinlock, flags);
1099
1100 if (gpu->event[event].used == false) {
1101 dev_warn(gpu->dev, "event %u is already marked as free",
1102 event);
1103 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1104 } else {
1105 gpu->event[event].used = false;
1106 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1107
1108 complete(&gpu->event_free);
1109 }
1110 }
1111
1112 /*
1113 * Cmdstream submission/retirement:
1114 */
1115
1116 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1117 size_t nr_bos)
1118 {
1119 struct etnaviv_cmdbuf *cmdbuf;
1120 size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]),
1121 sizeof(*cmdbuf));
1122
1123 cmdbuf = kzalloc(sz, GFP_KERNEL);
1124 if (!cmdbuf)
1125 return NULL;
1126
1127 if (gpu->mmu->version == ETNAVIV_IOMMU_V2)
1128 size = ALIGN(size, SZ_4K);
1129
1130 cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr,
1131 GFP_KERNEL);
1132 if (!cmdbuf->vaddr) {
1133 kfree(cmdbuf);
1134 return NULL;
1135 }
1136
1137 cmdbuf->gpu = gpu;
1138 cmdbuf->size = size;
1139
1140 return cmdbuf;
1141 }
1142
1143 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1144 {
1145 etnaviv_iommu_put_cmdbuf_va(cmdbuf->gpu, cmdbuf);
1146 dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr,
1147 cmdbuf->paddr);
1148 kfree(cmdbuf);
1149 }
1150
1151 static void retire_worker(struct work_struct *work)
1152 {
1153 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1154 retire_work);
1155 u32 fence = gpu->completed_fence;
1156 struct etnaviv_cmdbuf *cmdbuf, *tmp;
1157 unsigned int i;
1158
1159 mutex_lock(&gpu->lock);
1160 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1161 if (!fence_is_signaled(cmdbuf->fence))
1162 break;
1163
1164 list_del(&cmdbuf->node);
1165 fence_put(cmdbuf->fence);
1166
1167 for (i = 0; i < cmdbuf->nr_bos; i++) {
1168 struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i];
1169 struct etnaviv_gem_object *etnaviv_obj = mapping->object;
1170
1171 atomic_dec(&etnaviv_obj->gpu_active);
1172 /* drop the refcount taken in etnaviv_gpu_submit */
1173 etnaviv_gem_mapping_unreference(mapping);
1174 }
1175
1176 etnaviv_gpu_cmdbuf_free(cmdbuf);
1177 /*
1178 * We need to balance the runtime PM count caused by
1179 * each submission. Upon submission, we increment
1180 * the runtime PM counter, and allocate one event.
1181 * So here, we put the runtime PM count for each
1182 * completed event.
1183 */
1184 pm_runtime_put_autosuspend(gpu->dev);
1185 }
1186
1187 gpu->retired_fence = fence;
1188
1189 mutex_unlock(&gpu->lock);
1190
1191 wake_up_all(&gpu->fence_event);
1192 }
1193
1194 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1195 u32 fence, struct timespec *timeout)
1196 {
1197 int ret;
1198
1199 if (fence_after(fence, gpu->next_fence)) {
1200 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1201 fence, gpu->next_fence);
1202 return -EINVAL;
1203 }
1204
1205 if (!timeout) {
1206 /* No timeout was requested: just test for completion */
1207 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1208 } else {
1209 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1210
1211 ret = wait_event_interruptible_timeout(gpu->fence_event,
1212 fence_completed(gpu, fence),
1213 remaining);
1214 if (ret == 0) {
1215 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1216 fence, gpu->retired_fence,
1217 gpu->completed_fence);
1218 ret = -ETIMEDOUT;
1219 } else if (ret != -ERESTARTSYS) {
1220 ret = 0;
1221 }
1222 }
1223
1224 return ret;
1225 }
1226
1227 /*
1228 * Wait for an object to become inactive. This, on it's own, is not race
1229 * free: the object is moved by the retire worker off the active list, and
1230 * then the iova is put. Moreover, the object could be re-submitted just
1231 * after we notice that it's become inactive.
1232 *
1233 * Although the retirement happens under the gpu lock, we don't want to hold
1234 * that lock in this function while waiting.
1235 */
1236 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1237 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1238 {
1239 unsigned long remaining;
1240 long ret;
1241
1242 if (!timeout)
1243 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1244
1245 remaining = etnaviv_timeout_to_jiffies(timeout);
1246
1247 ret = wait_event_interruptible_timeout(gpu->fence_event,
1248 !is_active(etnaviv_obj),
1249 remaining);
1250 if (ret > 0) {
1251 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1252
1253 /* Synchronise with the retire worker */
1254 flush_workqueue(priv->wq);
1255 return 0;
1256 } else if (ret == -ERESTARTSYS) {
1257 return -ERESTARTSYS;
1258 } else {
1259 return -ETIMEDOUT;
1260 }
1261 }
1262
1263 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1264 {
1265 return pm_runtime_get_sync(gpu->dev);
1266 }
1267
1268 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1269 {
1270 pm_runtime_mark_last_busy(gpu->dev);
1271 pm_runtime_put_autosuspend(gpu->dev);
1272 }
1273
1274 /* add bo's to gpu's ring, and kick gpu: */
1275 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1276 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1277 {
1278 struct fence *fence;
1279 unsigned int event, i;
1280 int ret;
1281
1282 ret = etnaviv_gpu_pm_get_sync(gpu);
1283 if (ret < 0)
1284 return ret;
1285
1286 /*
1287 * TODO
1288 *
1289 * - flush
1290 * - data endian
1291 * - prefetch
1292 *
1293 */
1294
1295 event = event_alloc(gpu);
1296 if (unlikely(event == ~0U)) {
1297 DRM_ERROR("no free event\n");
1298 ret = -EBUSY;
1299 goto out_pm_put;
1300 }
1301
1302 mutex_lock(&gpu->lock);
1303
1304 fence = etnaviv_gpu_fence_alloc(gpu);
1305 if (!fence) {
1306 event_free(gpu, event);
1307 ret = -ENOMEM;
1308 goto out_unlock;
1309 }
1310
1311 gpu->event[event].fence = fence;
1312 submit->fence = fence->seqno;
1313 gpu->active_fence = submit->fence;
1314
1315 if (gpu->lastctx != cmdbuf->ctx) {
1316 gpu->mmu->need_flush = true;
1317 gpu->switch_context = true;
1318 gpu->lastctx = cmdbuf->ctx;
1319 }
1320
1321 etnaviv_buffer_queue(gpu, event, cmdbuf);
1322
1323 cmdbuf->fence = fence;
1324 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1325
1326 /* We're committed to adding this command buffer, hold a PM reference */
1327 pm_runtime_get_noresume(gpu->dev);
1328
1329 for (i = 0; i < submit->nr_bos; i++) {
1330 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1331
1332 /* Each cmdbuf takes a refcount on the mapping */
1333 etnaviv_gem_mapping_reference(submit->bos[i].mapping);
1334 cmdbuf->bo_map[i] = submit->bos[i].mapping;
1335 atomic_inc(&etnaviv_obj->gpu_active);
1336
1337 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1338 reservation_object_add_excl_fence(etnaviv_obj->resv,
1339 fence);
1340 else
1341 reservation_object_add_shared_fence(etnaviv_obj->resv,
1342 fence);
1343 }
1344 cmdbuf->nr_bos = submit->nr_bos;
1345 hangcheck_timer_reset(gpu);
1346 ret = 0;
1347
1348 out_unlock:
1349 mutex_unlock(&gpu->lock);
1350
1351 out_pm_put:
1352 etnaviv_gpu_pm_put(gpu);
1353
1354 return ret;
1355 }
1356
1357 /*
1358 * Init/Cleanup:
1359 */
1360 static irqreturn_t irq_handler(int irq, void *data)
1361 {
1362 struct etnaviv_gpu *gpu = data;
1363 irqreturn_t ret = IRQ_NONE;
1364
1365 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1366
1367 if (intr != 0) {
1368 int event;
1369
1370 pm_runtime_mark_last_busy(gpu->dev);
1371
1372 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1373
1374 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1375 dev_err(gpu->dev, "AXI bus error\n");
1376 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1377 }
1378
1379 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1380 int i;
1381
1382 dev_err_ratelimited(gpu->dev,
1383 "MMU fault status 0x%08x\n",
1384 gpu_read(gpu, VIVS_MMUv2_STATUS));
1385 for (i = 0; i < 4; i++) {
1386 dev_err_ratelimited(gpu->dev,
1387 "MMU %d fault addr 0x%08x\n",
1388 i, gpu_read(gpu,
1389 VIVS_MMUv2_EXCEPTION_ADDR(i)));
1390 }
1391 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1392 }
1393
1394 while ((event = ffs(intr)) != 0) {
1395 struct fence *fence;
1396
1397 event -= 1;
1398
1399 intr &= ~(1 << event);
1400
1401 dev_dbg(gpu->dev, "event %u\n", event);
1402
1403 fence = gpu->event[event].fence;
1404 gpu->event[event].fence = NULL;
1405 fence_signal(fence);
1406
1407 /*
1408 * Events can be processed out of order. Eg,
1409 * - allocate and queue event 0
1410 * - allocate event 1
1411 * - event 0 completes, we process it
1412 * - allocate and queue event 0
1413 * - event 1 and event 0 complete
1414 * we can end up processing event 0 first, then 1.
1415 */
1416 if (fence_after(fence->seqno, gpu->completed_fence))
1417 gpu->completed_fence = fence->seqno;
1418
1419 event_free(gpu, event);
1420 }
1421
1422 /* Retire the buffer objects in a work */
1423 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1424
1425 ret = IRQ_HANDLED;
1426 }
1427
1428 return ret;
1429 }
1430
1431 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1432 {
1433 int ret;
1434
1435 if (gpu->clk_bus) {
1436 ret = clk_prepare_enable(gpu->clk_bus);
1437 if (ret)
1438 return ret;
1439 }
1440
1441 if (gpu->clk_core) {
1442 ret = clk_prepare_enable(gpu->clk_core);
1443 if (ret)
1444 goto disable_clk_bus;
1445 }
1446
1447 if (gpu->clk_shader) {
1448 ret = clk_prepare_enable(gpu->clk_shader);
1449 if (ret)
1450 goto disable_clk_core;
1451 }
1452
1453 return 0;
1454
1455 disable_clk_core:
1456 if (gpu->clk_core)
1457 clk_disable_unprepare(gpu->clk_core);
1458 disable_clk_bus:
1459 if (gpu->clk_bus)
1460 clk_disable_unprepare(gpu->clk_bus);
1461
1462 return ret;
1463 }
1464
1465 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1466 {
1467 if (gpu->clk_shader)
1468 clk_disable_unprepare(gpu->clk_shader);
1469 if (gpu->clk_core)
1470 clk_disable_unprepare(gpu->clk_core);
1471 if (gpu->clk_bus)
1472 clk_disable_unprepare(gpu->clk_bus);
1473
1474 return 0;
1475 }
1476
1477 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1478 {
1479 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1480
1481 do {
1482 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1483
1484 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1485 return 0;
1486
1487 if (time_is_before_jiffies(timeout)) {
1488 dev_warn(gpu->dev,
1489 "timed out waiting for idle: idle=0x%x\n",
1490 idle);
1491 return -ETIMEDOUT;
1492 }
1493
1494 udelay(5);
1495 } while (1);
1496 }
1497
1498 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1499 {
1500 if (gpu->buffer) {
1501 /* Replace the last WAIT with END */
1502 etnaviv_buffer_end(gpu);
1503
1504 /*
1505 * We know that only the FE is busy here, this should
1506 * happen quickly (as the WAIT is only 200 cycles). If
1507 * we fail, just warn and continue.
1508 */
1509 etnaviv_gpu_wait_idle(gpu, 100);
1510 }
1511
1512 return etnaviv_gpu_clk_disable(gpu);
1513 }
1514
1515 #ifdef CONFIG_PM
1516 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1517 {
1518 u32 clock;
1519 int ret;
1520
1521 ret = mutex_lock_killable(&gpu->lock);
1522 if (ret)
1523 return ret;
1524
1525 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1526 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1527
1528 etnaviv_gpu_load_clock(gpu, clock);
1529 etnaviv_gpu_hw_init(gpu);
1530
1531 gpu->switch_context = true;
1532 gpu->exec_state = -1;
1533
1534 mutex_unlock(&gpu->lock);
1535
1536 return 0;
1537 }
1538 #endif
1539
1540 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1541 void *data)
1542 {
1543 struct drm_device *drm = data;
1544 struct etnaviv_drm_private *priv = drm->dev_private;
1545 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1546 int ret;
1547
1548 #ifdef CONFIG_PM
1549 ret = pm_runtime_get_sync(gpu->dev);
1550 #else
1551 ret = etnaviv_gpu_clk_enable(gpu);
1552 #endif
1553 if (ret < 0)
1554 return ret;
1555
1556 gpu->drm = drm;
1557 gpu->fence_context = fence_context_alloc(1);
1558 spin_lock_init(&gpu->fence_spinlock);
1559
1560 INIT_LIST_HEAD(&gpu->active_cmd_list);
1561 INIT_WORK(&gpu->retire_work, retire_worker);
1562 INIT_WORK(&gpu->recover_work, recover_worker);
1563 init_waitqueue_head(&gpu->fence_event);
1564
1565 setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
1566 (unsigned long)gpu);
1567
1568 priv->gpu[priv->num_gpus++] = gpu;
1569
1570 pm_runtime_mark_last_busy(gpu->dev);
1571 pm_runtime_put_autosuspend(gpu->dev);
1572
1573 return 0;
1574 }
1575
1576 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1577 void *data)
1578 {
1579 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1580
1581 DBG("%s", dev_name(gpu->dev));
1582
1583 hangcheck_disable(gpu);
1584
1585 #ifdef CONFIG_PM
1586 pm_runtime_get_sync(gpu->dev);
1587 pm_runtime_put_sync_suspend(gpu->dev);
1588 #else
1589 etnaviv_gpu_hw_suspend(gpu);
1590 #endif
1591
1592 if (gpu->buffer) {
1593 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1594 gpu->buffer = NULL;
1595 }
1596
1597 if (gpu->mmu) {
1598 etnaviv_iommu_destroy(gpu->mmu);
1599 gpu->mmu = NULL;
1600 }
1601
1602 gpu->drm = NULL;
1603 }
1604
1605 static const struct component_ops gpu_ops = {
1606 .bind = etnaviv_gpu_bind,
1607 .unbind = etnaviv_gpu_unbind,
1608 };
1609
1610 static const struct of_device_id etnaviv_gpu_match[] = {
1611 {
1612 .compatible = "vivante,gc"
1613 },
1614 { /* sentinel */ }
1615 };
1616
1617 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1618 {
1619 struct device *dev = &pdev->dev;
1620 struct etnaviv_gpu *gpu;
1621 int err;
1622
1623 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1624 if (!gpu)
1625 return -ENOMEM;
1626
1627 gpu->dev = &pdev->dev;
1628 mutex_init(&gpu->lock);
1629
1630 /* Map registers: */
1631 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1632 if (IS_ERR(gpu->mmio))
1633 return PTR_ERR(gpu->mmio);
1634
1635 /* Get Interrupt: */
1636 gpu->irq = platform_get_irq(pdev, 0);
1637 if (gpu->irq < 0) {
1638 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1639 return gpu->irq;
1640 }
1641
1642 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1643 dev_name(gpu->dev), gpu);
1644 if (err) {
1645 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1646 return err;
1647 }
1648
1649 /* Get Clocks: */
1650 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1651 DBG("clk_bus: %p", gpu->clk_bus);
1652 if (IS_ERR(gpu->clk_bus))
1653 gpu->clk_bus = NULL;
1654
1655 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1656 DBG("clk_core: %p", gpu->clk_core);
1657 if (IS_ERR(gpu->clk_core))
1658 gpu->clk_core = NULL;
1659
1660 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1661 DBG("clk_shader: %p", gpu->clk_shader);
1662 if (IS_ERR(gpu->clk_shader))
1663 gpu->clk_shader = NULL;
1664
1665 /* TODO: figure out max mapped size */
1666 dev_set_drvdata(dev, gpu);
1667
1668 /*
1669 * We treat the device as initially suspended. The runtime PM
1670 * autosuspend delay is rather arbitary: no measurements have
1671 * yet been performed to determine an appropriate value.
1672 */
1673 pm_runtime_use_autosuspend(gpu->dev);
1674 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1675 pm_runtime_enable(gpu->dev);
1676
1677 err = component_add(&pdev->dev, &gpu_ops);
1678 if (err < 0) {
1679 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1680 return err;
1681 }
1682
1683 return 0;
1684 }
1685
1686 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1687 {
1688 component_del(&pdev->dev, &gpu_ops);
1689 pm_runtime_disable(&pdev->dev);
1690 return 0;
1691 }
1692
1693 #ifdef CONFIG_PM
1694 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1695 {
1696 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1697 u32 idle, mask;
1698
1699 /* If we have outstanding fences, we're not idle */
1700 if (gpu->completed_fence != gpu->active_fence)
1701 return -EBUSY;
1702
1703 /* Check whether the hardware (except FE) is idle */
1704 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1705 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1706 if (idle != mask)
1707 return -EBUSY;
1708
1709 return etnaviv_gpu_hw_suspend(gpu);
1710 }
1711
1712 static int etnaviv_gpu_rpm_resume(struct device *dev)
1713 {
1714 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1715 int ret;
1716
1717 ret = etnaviv_gpu_clk_enable(gpu);
1718 if (ret)
1719 return ret;
1720
1721 /* Re-initialise the basic hardware state */
1722 if (gpu->drm && gpu->buffer) {
1723 ret = etnaviv_gpu_hw_resume(gpu);
1724 if (ret) {
1725 etnaviv_gpu_clk_disable(gpu);
1726 return ret;
1727 }
1728 }
1729
1730 return 0;
1731 }
1732 #endif
1733
1734 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1735 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1736 NULL)
1737 };
1738
1739 struct platform_driver etnaviv_gpu_driver = {
1740 .driver = {
1741 .name = "etnaviv-gpu",
1742 .owner = THIS_MODULE,
1743 .pm = &etnaviv_gpu_pm_ops,
1744 .of_match_table = etnaviv_gpu_match,
1745 },
1746 .probe = etnaviv_gpu_platform_probe,
1747 .remove = etnaviv_gpu_platform_remove,
1748 .id_table = gpu_ids,
1749 };
Linux with added FPC-III support