drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h

   1 /*
   2  * Copyright (c) 2016 Linaro Limited.
   3  * Copyright (c) 2014-2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #ifndef __DW_DSI_REG_H__
  12 #define __DW_DSI_REG_H__
  13
  14 #define MASK(x)                         (BIT(x) - 1)
  15
  16 /*
  17  * regs
  18  */
  19 #define PWR_UP                  0x04  /* Core power-up */
  20 #define RESET                   0
  21 #define POWERUP                 BIT(0)
  22 #define PHY_IF_CFG              0xA4  /* D-PHY interface configuration */
  23 #define CLKMGR_CFG              0x08  /* the internal clock dividers */
  24 #define PHY_RSTZ                0xA0  /* D-PHY reset control */
  25 #define PHY_ENABLECLK           BIT(2)
  26 #define PHY_UNRSTZ              BIT(1)
  27 #define PHY_UNSHUTDOWNZ         BIT(0)
  28 #define PHY_TST_CTRL0           0xB4  /* D-PHY test interface control 0 */
  29 #define PHY_TST_CTRL1           0xB8  /* D-PHY test interface control 1 */
  30 #define CLK_TLPX                0x10
  31 #define CLK_THS_PREPARE         0x11
  32 #define CLK_THS_ZERO            0x12
  33 #define CLK_THS_TRAIL           0x13
  34 #define CLK_TWAKEUP             0x14
  35 #define DATA_TLPX(x)            (0x20 + ((x) << 4))
  36 #define DATA_THS_PREPARE(x)     (0x21 + ((x) << 4))
  37 #define DATA_THS_ZERO(x)        (0x22 + ((x) << 4))
  38 #define DATA_THS_TRAIL(x)       (0x23 + ((x) << 4))
  39 #define DATA_TTA_GO(x)          (0x24 + ((x) << 4))
  40 #define DATA_TTA_GET(x)         (0x25 + ((x) << 4))
  41 #define DATA_TWAKEUP(x)         (0x26 + ((x) << 4))
  42 #define PHY_CFG_I               0x60
  43 #define PHY_CFG_PLL_I           0x63
  44 #define PHY_CFG_PLL_II          0x64
  45 #define PHY_CFG_PLL_III         0x65
  46 #define PHY_CFG_PLL_IV          0x66
  47 #define PHY_CFG_PLL_V           0x67
  48 #define DPI_COLOR_CODING        0x10  /* DPI color coding */
  49 #define DPI_CFG_POL             0x14  /* DPI polarity configuration */
  50 #define VID_HSA_TIME            0x48  /* Horizontal Sync Active time */
  51 #define VID_HBP_TIME            0x4C  /* Horizontal Back Porch time */
  52 #define VID_HLINE_TIME          0x50  /* Line time */
  53 #define VID_VSA_LINES           0x54  /* Vertical Sync Active period */
  54 #define VID_VBP_LINES           0x58  /* Vertical Back Porch period */
  55 #define VID_VFP_LINES           0x5C  /* Vertical Front Porch period */
  56 #define VID_VACTIVE_LINES       0x60  /* Vertical resolution */
  57 #define VID_PKT_SIZE            0x3C  /* Video packet size */
  58 #define VID_MODE_CFG            0x38  /* Video mode configuration */
  59 #define PHY_TMR_CFG             0x9C  /* Data lanes timing configuration */
  60 #define BTA_TO_CNT              0x8C  /* Response timeout definition */
  61 #define PHY_TMR_LPCLK_CFG       0x98  /* clock lane timing configuration */
  62 #define CLK_DATA_TMR_CFG        0xCC
  63 #define LPCLK_CTRL              0x94  /* Low-power in clock lane */
  64 #define PHY_TXREQUESTCLKHS      BIT(0)
  65 #define MODE_CFG                0x34  /* Video or Command mode selection */
  66 #define PHY_STATUS              0xB0  /* D-PHY PPI status interface */
  67
  68 #define PHY_STOP_WAIT_TIME      0x30
  69
  70 /*
  71  * regs relevant enum
  72  */
  73 enum dpi_color_coding {
  74         DSI_24BITS_1 = 5,
  75 };
  76
  77 enum dsi_video_mode_type {
  78         DSI_NON_BURST_SYNC_PULSES = 0,
  79         DSI_NON_BURST_SYNC_EVENTS,
  80         DSI_BURST_SYNC_PULSES_1,
  81         DSI_BURST_SYNC_PULSES_2
  82 };
  83
  84 enum dsi_work_mode {
  85         DSI_VIDEO_MODE = 0,
  86         DSI_COMMAND_MODE
  87 };
  88
  89 /*
  90  * Register Write/Read Helper functions
  91  */
  92 static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
  93                                   u32 mask, u32 val)
  94 {
  95         u32 tmp, orig;
  96
  97         orig = readl(addr);
  98         tmp = orig & ~(mask << bit_start);
  99         tmp |= (val & mask) << bit_start;
 100         writel(tmp, addr);
 101 }
 102
 103 #endif /* __DW_DRM_DSI_H__ */