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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / gpu / drm / sti / sti_gdp.c
blob7fd496f993855f2b6ef9554bb45ac0dbfea623f6
1 /*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8 #include <linux/seq_file.h>
9
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_fb_cma_helper.h>
12 #include <drm/drm_gem_cma_helper.h>
13
14 #include "sti_compositor.h"
15 #include "sti_gdp.h"
16 #include "sti_plane.h"
17 #include "sti_vtg.h"
18
19 #define ALPHASWITCH BIT(6)
20 #define ENA_COLOR_FILL BIT(8)
21 #define BIGNOTLITTLE BIT(23)
22 #define WAIT_NEXT_VSYNC BIT(31)
23
24 /* GDP color formats */
25 #define GDP_RGB565 0x00
26 #define GDP_RGB888 0x01
27 #define GDP_RGB888_32 0x02
28 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
29 #define GDP_ARGB8565 0x04
30 #define GDP_ARGB8888 0x05
31 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
32 #define GDP_ARGB1555 0x06
33 #define GDP_ARGB4444 0x07
34
35 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
36
37 static struct gdp_format_to_str {
38 int format;
39 char name[20];
40 } gdp_format_to_str[] = {
41 GDP2STR(RGB565),
42 GDP2STR(RGB888),
43 GDP2STR(RGB888_32),
44 GDP2STR(XBGR8888),
45 GDP2STR(ARGB8565),
46 GDP2STR(ARGB8888),
47 GDP2STR(ABGR8888),
48 GDP2STR(ARGB1555),
49 GDP2STR(ARGB4444)
50 };
51
52 #define GAM_GDP_CTL_OFFSET 0x00
53 #define GAM_GDP_AGC_OFFSET 0x04
54 #define GAM_GDP_VPO_OFFSET 0x0C
55 #define GAM_GDP_VPS_OFFSET 0x10
56 #define GAM_GDP_PML_OFFSET 0x14
57 #define GAM_GDP_PMP_OFFSET 0x18
58 #define GAM_GDP_SIZE_OFFSET 0x1C
59 #define GAM_GDP_NVN_OFFSET 0x24
60 #define GAM_GDP_KEY1_OFFSET 0x28
61 #define GAM_GDP_KEY2_OFFSET 0x2C
62 #define GAM_GDP_PPT_OFFSET 0x34
63 #define GAM_GDP_CML_OFFSET 0x3C
64 #define GAM_GDP_MST_OFFSET 0x68
65
66 #define GAM_GDP_ALPHARANGE_255 BIT(5)
67 #define GAM_GDP_AGC_FULL_RANGE 0x00808080
68 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
69
70 #define GAM_GDP_SIZE_MAX_WIDTH 3840
71 #define GAM_GDP_SIZE_MAX_HEIGHT 2160
72
73 #define GDP_NODE_NB_BANK 2
74 #define GDP_NODE_PER_FIELD 2
75
76 struct sti_gdp_node {
77 u32 gam_gdp_ctl;
78 u32 gam_gdp_agc;
79 u32 reserved1;
80 u32 gam_gdp_vpo;
81 u32 gam_gdp_vps;
82 u32 gam_gdp_pml;
83 u32 gam_gdp_pmp;
84 u32 gam_gdp_size;
85 u32 reserved2;
86 u32 gam_gdp_nvn;
87 u32 gam_gdp_key1;
88 u32 gam_gdp_key2;
89 u32 reserved3;
90 u32 gam_gdp_ppt;
91 u32 reserved4;
92 u32 gam_gdp_cml;
93 };
94
95 struct sti_gdp_node_list {
96 struct sti_gdp_node *top_field;
97 dma_addr_t top_field_paddr;
98 struct sti_gdp_node *btm_field;
99 dma_addr_t btm_field_paddr;
100 };
101
102 /**
103 * STI GDP structure
104 *
105 * @sti_plane: sti_plane structure
106 * @dev: driver device
107 * @regs: gdp registers
108 * @clk_pix: pixel clock for the current gdp
109 * @clk_main_parent: gdp parent clock if main path used
110 * @clk_aux_parent: gdp parent clock if aux path used
111 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
112 * @is_curr_top: true if the current node processed is the top field
113 * @node_list: array of node list
114 * @vtg: registered vtg
115 */
116 struct sti_gdp {
117 struct sti_plane plane;
118 struct device *dev;
119 void __iomem *regs;
120 struct clk *clk_pix;
121 struct clk *clk_main_parent;
122 struct clk *clk_aux_parent;
123 struct notifier_block vtg_field_nb;
124 bool is_curr_top;
125 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
126 struct sti_vtg *vtg;
127 };
128
129 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
130
131 static const uint32_t gdp_supported_formats[] = {
132 DRM_FORMAT_XRGB8888,
133 DRM_FORMAT_XBGR8888,
134 DRM_FORMAT_ARGB8888,
135 DRM_FORMAT_ABGR8888,
136 DRM_FORMAT_ARGB4444,
137 DRM_FORMAT_ARGB1555,
138 DRM_FORMAT_RGB565,
139 DRM_FORMAT_RGB888,
140 };
141
142 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
143 readl(gdp->regs + reg ## _OFFSET))
144
145 static void gdp_dbg_ctl(struct seq_file *s, int val)
146 {
147 int i;
148
149 seq_puts(s, "\tColor:");
150 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
151 if (gdp_format_to_str[i].format == (val & 0x1F)) {
152 seq_printf(s, gdp_format_to_str[i].name);
153 break;
154 }
155 }
156 if (i == ARRAY_SIZE(gdp_format_to_str))
157 seq_puts(s, "<UNKNOWN>");
158
159 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
160 }
161
162 static void gdp_dbg_vpo(struct seq_file *s, int val)
163 {
164 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
165 }
166
167 static void gdp_dbg_vps(struct seq_file *s, int val)
168 {
169 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
170 }
171
172 static void gdp_dbg_size(struct seq_file *s, int val)
173 {
174 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
175 }
176
177 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
178 {
179 void *base = NULL;
180 unsigned int i;
181
182 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
183 if (gdp->node_list[i].top_field_paddr == val) {
184 base = gdp->node_list[i].top_field;
185 break;
186 }
187 if (gdp->node_list[i].btm_field_paddr == val) {
188 base = gdp->node_list[i].btm_field;
189 break;
190 }
191 }
192
193 if (base)
194 seq_printf(s, "\tVirt @: %p", base);
195 }
196
197 static void gdp_dbg_ppt(struct seq_file *s, int val)
198 {
199 if (val & GAM_GDP_PPT_IGNORE)
200 seq_puts(s, "\tNot displayed on mixer!");
201 }
202
203 static void gdp_dbg_mst(struct seq_file *s, int val)
204 {
205 if (val & 1)
206 seq_puts(s, "\tBUFFER UNDERFLOW!");
207 }
208
209 static int gdp_dbg_show(struct seq_file *s, void *data)
210 {
211 struct drm_info_node *node = s->private;
212 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
213 struct drm_plane *drm_plane = &gdp->plane.drm_plane;
214 struct drm_crtc *crtc = drm_plane->crtc;
215
216 seq_printf(s, "%s: (vaddr = 0x%p)",
217 sti_plane_to_str(&gdp->plane), gdp->regs);
218
219 DBGFS_DUMP(GAM_GDP_CTL);
220 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
221 DBGFS_DUMP(GAM_GDP_AGC);
222 DBGFS_DUMP(GAM_GDP_VPO);
223 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
224 DBGFS_DUMP(GAM_GDP_VPS);
225 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
226 DBGFS_DUMP(GAM_GDP_PML);
227 DBGFS_DUMP(GAM_GDP_PMP);
228 DBGFS_DUMP(GAM_GDP_SIZE);
229 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
230 DBGFS_DUMP(GAM_GDP_NVN);
231 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
232 DBGFS_DUMP(GAM_GDP_KEY1);
233 DBGFS_DUMP(GAM_GDP_KEY2);
234 DBGFS_DUMP(GAM_GDP_PPT);
235 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
236 DBGFS_DUMP(GAM_GDP_CML);
237 DBGFS_DUMP(GAM_GDP_MST);
238 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
239
240 seq_puts(s, "\n\n");
241 if (!crtc)
242 seq_puts(s, " Not connected to any DRM CRTC\n");
243 else
244 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
245 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
246
247 return 0;
248 }
249
250 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
251 {
252 seq_printf(s, "\t@:0x%p", node);
253 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
254 gdp_dbg_ctl(s, node->gam_gdp_ctl);
255 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
256 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
257 gdp_dbg_vpo(s, node->gam_gdp_vpo);
258 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
259 gdp_dbg_vps(s, node->gam_gdp_vps);
260 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
261 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
262 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
263 gdp_dbg_size(s, node->gam_gdp_size);
264 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
265 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
266 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
267 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
268 gdp_dbg_ppt(s, node->gam_gdp_ppt);
269 seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml);
270 seq_puts(s, "\n");
271 }
272
273 static int gdp_node_dbg_show(struct seq_file *s, void *arg)
274 {
275 struct drm_info_node *node = s->private;
276 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
277 unsigned int b;
278
279 for (b = 0; b < GDP_NODE_NB_BANK; b++) {
280 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
281 gdp_node_dump_node(s, gdp->node_list[b].top_field);
282 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
283 gdp_node_dump_node(s, gdp->node_list[b].btm_field);
284 }
285
286 return 0;
287 }
288
289 static struct drm_info_list gdp0_debugfs_files[] = {
290 { "gdp0", gdp_dbg_show, 0, NULL },
291 { "gdp0_node", gdp_node_dbg_show, 0, NULL },
292 };
293
294 static struct drm_info_list gdp1_debugfs_files[] = {
295 { "gdp1", gdp_dbg_show, 0, NULL },
296 { "gdp1_node", gdp_node_dbg_show, 0, NULL },
297 };
298
299 static struct drm_info_list gdp2_debugfs_files[] = {
300 { "gdp2", gdp_dbg_show, 0, NULL },
301 { "gdp2_node", gdp_node_dbg_show, 0, NULL },
302 };
303
304 static struct drm_info_list gdp3_debugfs_files[] = {
305 { "gdp3", gdp_dbg_show, 0, NULL },
306 { "gdp3_node", gdp_node_dbg_show, 0, NULL },
307 };
308
309 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
310 {
311 unsigned int i;
312 struct drm_info_list *gdp_debugfs_files;
313 int nb_files;
314
315 switch (gdp->plane.desc) {
316 case STI_GDP_0:
317 gdp_debugfs_files = gdp0_debugfs_files;
318 nb_files = ARRAY_SIZE(gdp0_debugfs_files);
319 break;
320 case STI_GDP_1:
321 gdp_debugfs_files = gdp1_debugfs_files;
322 nb_files = ARRAY_SIZE(gdp1_debugfs_files);
323 break;
324 case STI_GDP_2:
325 gdp_debugfs_files = gdp2_debugfs_files;
326 nb_files = ARRAY_SIZE(gdp2_debugfs_files);
327 break;
328 case STI_GDP_3:
329 gdp_debugfs_files = gdp3_debugfs_files;
330 nb_files = ARRAY_SIZE(gdp3_debugfs_files);
331 break;
332 default:
333 return -EINVAL;
334 }
335
336 for (i = 0; i < nb_files; i++)
337 gdp_debugfs_files[i].data = gdp;
338
339 return drm_debugfs_create_files(gdp_debugfs_files,
340 nb_files,
341 minor->debugfs_root, minor);
342 }
343
344 static int sti_gdp_fourcc2format(int fourcc)
345 {
346 switch (fourcc) {
347 case DRM_FORMAT_XRGB8888:
348 return GDP_RGB888_32;
349 case DRM_FORMAT_XBGR8888:
350 return GDP_XBGR8888;
351 case DRM_FORMAT_ARGB8888:
352 return GDP_ARGB8888;
353 case DRM_FORMAT_ABGR8888:
354 return GDP_ABGR8888;
355 case DRM_FORMAT_ARGB4444:
356 return GDP_ARGB4444;
357 case DRM_FORMAT_ARGB1555:
358 return GDP_ARGB1555;
359 case DRM_FORMAT_RGB565:
360 return GDP_RGB565;
361 case DRM_FORMAT_RGB888:
362 return GDP_RGB888;
363 }
364 return -1;
365 }
366
367 static int sti_gdp_get_alpharange(int format)
368 {
369 switch (format) {
370 case GDP_ARGB8565:
371 case GDP_ARGB8888:
372 case GDP_ABGR8888:
373 return GAM_GDP_ALPHARANGE_255;
374 }
375 return 0;
376 }
377
378 /**
379 * sti_gdp_get_free_nodes
380 * @gdp: gdp pointer
381 *
382 * Look for a GDP node list that is not currently read by the HW.
383 *
384 * RETURNS:
385 * Pointer to the free GDP node list
386 */
387 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
388 {
389 int hw_nvn;
390 unsigned int i;
391
392 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
393 if (!hw_nvn)
394 goto end;
395
396 for (i = 0; i < GDP_NODE_NB_BANK; i++)
397 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
398 (hw_nvn != gdp->node_list[i].top_field_paddr))
399 return &gdp->node_list[i];
400
401 /* in hazardious cases restart with the first node */
402 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
403 sti_plane_to_str(&gdp->plane), hw_nvn);
404
405 end:
406 return &gdp->node_list[0];
407 }
408
409 /**
410 * sti_gdp_get_current_nodes
411 * @gdp: gdp pointer
412 *
413 * Look for GDP nodes that are currently read by the HW.
414 *
415 * RETURNS:
416 * Pointer to the current GDP node list
417 */
418 static
419 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
420 {
421 int hw_nvn;
422 unsigned int i;
423
424 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
425 if (!hw_nvn)
426 goto end;
427
428 for (i = 0; i < GDP_NODE_NB_BANK; i++)
429 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
430 (hw_nvn == gdp->node_list[i].top_field_paddr))
431 return &gdp->node_list[i];
432
433 end:
434 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
435 hw_nvn, sti_plane_to_str(&gdp->plane));
436
437 return NULL;
438 }
439
440 /**
441 * sti_gdp_disable
442 * @gdp: gdp pointer
443 *
444 * Disable a GDP.
445 */
446 static void sti_gdp_disable(struct sti_gdp *gdp)
447 {
448 unsigned int i;
449
450 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
451
452 /* Set the nodes as 'to be ignored on mixer' */
453 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
454 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
455 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
456 }
457
458 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
459 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
460
461 if (gdp->clk_pix)
462 clk_disable_unprepare(gdp->clk_pix);
463
464 gdp->plane.status = STI_PLANE_DISABLED;
465 gdp->vtg = NULL;
466 }
467
468 /**
469 * sti_gdp_field_cb
470 * @nb: notifier block
471 * @event: event message
472 * @data: private data
473 *
474 * Handle VTG top field and bottom field event.
475 *
476 * RETURNS:
477 * 0 on success.
478 */
479 static int sti_gdp_field_cb(struct notifier_block *nb,
480 unsigned long event, void *data)
481 {
482 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
483
484 if (gdp->plane.status == STI_PLANE_FLUSHING) {
485 /* disable need to be synchronize on vsync event */
486 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
487 sti_plane_to_str(&gdp->plane));
488
489 sti_gdp_disable(gdp);
490 }
491
492 switch (event) {
493 case VTG_TOP_FIELD_EVENT:
494 gdp->is_curr_top = true;
495 break;
496 case VTG_BOTTOM_FIELD_EVENT:
497 gdp->is_curr_top = false;
498 break;
499 default:
500 DRM_ERROR("unsupported event: %lu\n", event);
501 break;
502 }
503
504 return 0;
505 }
506
507 static void sti_gdp_init(struct sti_gdp *gdp)
508 {
509 struct device_node *np = gdp->dev->of_node;
510 dma_addr_t dma_addr;
511 void *base;
512 unsigned int i, size;
513
514 /* Allocate all the nodes within a single memory page */
515 size = sizeof(struct sti_gdp_node) *
516 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
517 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA);
518
519 if (!base) {
520 DRM_ERROR("Failed to allocate memory for GDP node\n");
521 return;
522 }
523 memset(base, 0, size);
524
525 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
526 if (dma_addr & 0xF) {
527 DRM_ERROR("Mem alignment failed\n");
528 return;
529 }
530 gdp->node_list[i].top_field = base;
531 gdp->node_list[i].top_field_paddr = dma_addr;
532
533 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
534 base += sizeof(struct sti_gdp_node);
535 dma_addr += sizeof(struct sti_gdp_node);
536
537 if (dma_addr & 0xF) {
538 DRM_ERROR("Mem alignment failed\n");
539 return;
540 }
541 gdp->node_list[i].btm_field = base;
542 gdp->node_list[i].btm_field_paddr = dma_addr;
543 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
544 base += sizeof(struct sti_gdp_node);
545 dma_addr += sizeof(struct sti_gdp_node);
546 }
547
548 if (of_device_is_compatible(np, "st,stih407-compositor")) {
549 /* GDP of STiH407 chip have its own pixel clock */
550 char *clk_name;
551
552 switch (gdp->plane.desc) {
553 case STI_GDP_0:
554 clk_name = "pix_gdp1";
555 break;
556 case STI_GDP_1:
557 clk_name = "pix_gdp2";
558 break;
559 case STI_GDP_2:
560 clk_name = "pix_gdp3";
561 break;
562 case STI_GDP_3:
563 clk_name = "pix_gdp4";
564 break;
565 default:
566 DRM_ERROR("GDP id not recognized\n");
567 return;
568 }
569
570 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
571 if (IS_ERR(gdp->clk_pix))
572 DRM_ERROR("Cannot get %s clock\n", clk_name);
573
574 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
575 if (IS_ERR(gdp->clk_main_parent))
576 DRM_ERROR("Cannot get main_parent clock\n");
577
578 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
579 if (IS_ERR(gdp->clk_aux_parent))
580 DRM_ERROR("Cannot get aux_parent clock\n");
581 }
582 }
583
584 /**
585 * sti_gdp_get_dst
586 * @dev: device
587 * @dst: requested destination size
588 * @src: source size
589 *
590 * Return the cropped / clamped destination size
591 *
592 * RETURNS:
593 * cropped / clamped destination size
594 */
595 static int sti_gdp_get_dst(struct device *dev, int dst, int src)
596 {
597 if (dst == src)
598 return dst;
599
600 if (dst < src) {
601 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
602 return dst;
603 }
604
605 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
606 return src;
607 }
608
609 static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
610 struct drm_plane_state *state)
611 {
612 struct sti_plane *plane = to_sti_plane(drm_plane);
613 struct sti_gdp *gdp = to_sti_gdp(plane);
614 struct drm_crtc *crtc = state->crtc;
615 struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
616 struct drm_framebuffer *fb = state->fb;
617 struct drm_crtc_state *crtc_state;
618 struct sti_mixer *mixer;
619 struct drm_display_mode *mode;
620 int dst_x, dst_y, dst_w, dst_h;
621 int src_x, src_y, src_w, src_h;
622 int format;
623
624 /* no need for further checks if the plane is being disabled */
625 if (!crtc || !fb)
626 return 0;
627
628 mixer = to_sti_mixer(crtc);
629 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
630 mode = &crtc_state->mode;
631 dst_x = state->crtc_x;
632 dst_y = state->crtc_y;
633 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
634 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
635 /* src_x are in 16.16 format */
636 src_x = state->src_x >> 16;
637 src_y = state->src_y >> 16;
638 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
639 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
640
641 format = sti_gdp_fourcc2format(fb->pixel_format);
642 if (format == -1) {
643 DRM_ERROR("Format not supported by GDP %.4s\n",
644 (char *)&fb->pixel_format);
645 return -EINVAL;
646 }
647
648 if (!drm_fb_cma_get_gem_obj(fb, 0)) {
649 DRM_ERROR("Can't get CMA GEM object for fb\n");
650 return -EINVAL;
651 }
652
653 if (!gdp->vtg) {
654 /* Register gdp callback */
655 gdp->vtg = compo->vtg[mixer->id];
656 if (sti_vtg_register_client(gdp->vtg,
657 &gdp->vtg_field_nb, crtc)) {
658 DRM_ERROR("Cannot register VTG notifier\n");
659 return -EINVAL;
660 }
661
662 /* Set and enable gdp clock */
663 if (gdp->clk_pix) {
664 struct clk *clkp;
665 int rate = mode->clock * 1000;
666 int res;
667
668 /*
669 * According to the mixer used, the gdp pixel clock
670 * should have a different parent clock.
671 */
672 if (mixer->id == STI_MIXER_MAIN)
673 clkp = gdp->clk_main_parent;
674 else
675 clkp = gdp->clk_aux_parent;
676
677 if (clkp)
678 clk_set_parent(gdp->clk_pix, clkp);
679
680 res = clk_set_rate(gdp->clk_pix, rate);
681 if (res < 0) {
682 DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
683 rate);
684 return -EINVAL;
685 }
686
687 if (clk_prepare_enable(gdp->clk_pix)) {
688 DRM_ERROR("Failed to prepare/enable gdp\n");
689 return -EINVAL;
690 }
691 }
692 }
693
694 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
695 crtc->base.id, sti_mixer_to_str(mixer),
696 drm_plane->base.id, sti_plane_to_str(plane));
697 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
698 sti_plane_to_str(plane),
699 dst_w, dst_h, dst_x, dst_y,
700 src_w, src_h, src_x, src_y);
701
702 return 0;
703 }
704
705 static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
706 struct drm_plane_state *oldstate)
707 {
708 struct drm_plane_state *state = drm_plane->state;
709 struct sti_plane *plane = to_sti_plane(drm_plane);
710 struct sti_gdp *gdp = to_sti_gdp(plane);
711 struct drm_crtc *crtc = state->crtc;
712 struct drm_framebuffer *fb = state->fb;
713 struct drm_display_mode *mode;
714 int dst_x, dst_y, dst_w, dst_h;
715 int src_x, src_y, src_w, src_h;
716 struct drm_gem_cma_object *cma_obj;
717 struct sti_gdp_node_list *list;
718 struct sti_gdp_node_list *curr_list;
719 struct sti_gdp_node *top_field, *btm_field;
720 u32 dma_updated_top;
721 u32 dma_updated_btm;
722 int format;
723 unsigned int bpp;
724 u32 ydo, xdo, yds, xds;
725
726 if (!crtc || !fb)
727 return;
728
729 mode = &crtc->mode;
730 dst_x = state->crtc_x;
731 dst_y = state->crtc_y;
732 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
733 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
734 /* src_x are in 16.16 format */
735 src_x = state->src_x >> 16;
736 src_y = state->src_y >> 16;
737 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
738 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
739
740 list = sti_gdp_get_free_nodes(gdp);
741 top_field = list->top_field;
742 btm_field = list->btm_field;
743
744 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
745 sti_plane_to_str(plane), top_field, btm_field);
746
747 /* build the top field */
748 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
749 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
750 format = sti_gdp_fourcc2format(fb->pixel_format);
751 top_field->gam_gdp_ctl |= format;
752 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
753 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
754
755 cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
756
757 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
758 (char *)&fb->pixel_format,
759 (unsigned long)cma_obj->paddr);
760
761 /* pixel memory location */
762 bpp = drm_format_plane_cpp(fb->pixel_format, 0);
763 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
764 top_field->gam_gdp_pml += src_x * bpp;
765 top_field->gam_gdp_pml += src_y * fb->pitches[0];
766
767 /* output parameters (clamped / cropped) */
768 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
769 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
770 ydo = sti_vtg_get_line_number(*mode, dst_y);
771 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
772 xdo = sti_vtg_get_pixel_number(*mode, dst_x);
773 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
774 top_field->gam_gdp_vpo = (ydo << 16) | xdo;
775 top_field->gam_gdp_vps = (yds << 16) | xds;
776
777 /* input parameters */
778 src_w = dst_w;
779 top_field->gam_gdp_pmp = fb->pitches[0];
780 top_field->gam_gdp_size = src_h << 16 | src_w;
781
782 /* Same content and chained together */
783 memcpy(btm_field, top_field, sizeof(*btm_field));
784 top_field->gam_gdp_nvn = list->btm_field_paddr;
785 btm_field->gam_gdp_nvn = list->top_field_paddr;
786
787 /* Interlaced mode */
788 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
789 btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
790 fb->pitches[0];
791
792 /* Update the NVN field of the 'right' field of the current GDP node
793 * (being used by the HW) with the address of the updated ('free') top
794 * field GDP node.
795 * - In interlaced mode the 'right' field is the bottom field as we
796 * update frames starting from their top field
797 * - In progressive mode, we update both bottom and top fields which
798 * are equal nodes.
799 * At the next VSYNC, the updated node list will be used by the HW.
800 */
801 curr_list = sti_gdp_get_current_nodes(gdp);
802 dma_updated_top = list->top_field_paddr;
803 dma_updated_btm = list->btm_field_paddr;
804
805 dev_dbg(gdp->dev, "Current NVN:0x%X\n",
806 readl(gdp->regs + GAM_GDP_NVN_OFFSET));
807 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
808 (unsigned long)cma_obj->paddr,
809 readl(gdp->regs + GAM_GDP_PML_OFFSET));
810
811 if (!curr_list) {
812 /* First update or invalid node should directly write in the
813 * hw register */
814 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
815 sti_plane_to_str(plane));
816
817 writel(gdp->is_curr_top ?
818 dma_updated_btm : dma_updated_top,
819 gdp->regs + GAM_GDP_NVN_OFFSET);
820 goto end;
821 }
822
823 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
824 if (gdp->is_curr_top) {
825 /* Do not update in the middle of the frame, but
826 * postpone the update after the bottom field has
827 * been displayed */
828 curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
829 } else {
830 /* Direct update to avoid one frame delay */
831 writel(dma_updated_top,
832 gdp->regs + GAM_GDP_NVN_OFFSET);
833 }
834 } else {
835 /* Direct update for progressive to avoid one frame delay */
836 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
837 }
838
839 end:
840 sti_plane_update_fps(plane, true, false);
841
842 plane->status = STI_PLANE_UPDATED;
843 }
844
845 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
846 struct drm_plane_state *oldstate)
847 {
848 struct sti_plane *plane = to_sti_plane(drm_plane);
849
850 if (!oldstate->crtc) {
851 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
852 drm_plane->base.id);
853 return;
854 }
855
856 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
857 oldstate->crtc->base.id,
858 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
859 drm_plane->base.id, sti_plane_to_str(plane));
860
861 plane->status = STI_PLANE_DISABLING;
862 }
863
864 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
865 .atomic_check = sti_gdp_atomic_check,
866 .atomic_update = sti_gdp_atomic_update,
867 .atomic_disable = sti_gdp_atomic_disable,
868 };
869
870 static void sti_gdp_destroy(struct drm_plane *drm_plane)
871 {
872 DRM_DEBUG_DRIVER("\n");
873
874 drm_plane_helper_disable(drm_plane);
875 drm_plane_cleanup(drm_plane);
876 }
877
878 static int sti_gdp_late_register(struct drm_plane *drm_plane)
879 {
880 struct sti_plane *plane = to_sti_plane(drm_plane);
881 struct sti_gdp *gdp = to_sti_gdp(plane);
882
883 return gdp_debugfs_init(gdp, drm_plane->dev->primary);
884 }
885
886 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
887 .update_plane = drm_atomic_helper_update_plane,
888 .disable_plane = drm_atomic_helper_disable_plane,
889 .destroy = sti_gdp_destroy,
890 .set_property = drm_atomic_helper_plane_set_property,
891 .reset = sti_plane_reset,
892 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
893 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
894 .late_register = sti_gdp_late_register,
895 };
896
897 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
898 struct device *dev, int desc,
899 void __iomem *baseaddr,
900 unsigned int possible_crtcs,
901 enum drm_plane_type type)
902 {
903 struct sti_gdp *gdp;
904 int res;
905
906 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
907 if (!gdp) {
908 DRM_ERROR("Failed to allocate memory for GDP\n");
909 return NULL;
910 }
911
912 gdp->dev = dev;
913 gdp->regs = baseaddr;
914 gdp->plane.desc = desc;
915 gdp->plane.status = STI_PLANE_DISABLED;
916
917 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
918
919 sti_gdp_init(gdp);
920
921 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
922 possible_crtcs,
923 &sti_gdp_plane_helpers_funcs,
924 gdp_supported_formats,
925 ARRAY_SIZE(gdp_supported_formats),
926 type, NULL);
927 if (res) {
928 DRM_ERROR("Failed to initialize universal plane\n");
929 goto err;
930 }
931
932 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
933
934 sti_plane_init_property(&gdp->plane, type);
935
936 return &gdp->plane.drm_plane;
937
938 err:
939 devm_kfree(dev, gdp);
940 return NULL;
941 }
Linux with added FPC-III support