drivers/gpu/drm/sti/sti_vtg.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          Vincent Abriou <vincent.abriou@st.com>
   6  *          for STMicroelectronics.
   7  * License terms:  GNU General Public License (GPL), version 2
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/notifier.h>
  12 #include <linux/platform_device.h>
  13
  14 #include <drm/drmP.h>
  15
  16 #include "sti_drv.h"
  17 #include "sti_vtg.h"
  18
  19 #define VTG_MODE_MASTER         0
  20 #define VTG_MODE_SLAVE_BY_EXT0  1
  21
  22 /* registers offset */
  23 #define VTG_MODE            0x0000
  24 #define VTG_CLKLN           0x0008
  25 #define VTG_HLFLN           0x000C
  26 #define VTG_DRST_AUTOC      0x0010
  27 #define VTG_VID_TFO         0x0040
  28 #define VTG_VID_TFS         0x0044
  29 #define VTG_VID_BFO         0x0048
  30 #define VTG_VID_BFS         0x004C
  31
  32 #define VTG_HOST_ITS        0x0078
  33 #define VTG_HOST_ITS_BCLR   0x007C
  34 #define VTG_HOST_ITM_BCLR   0x0088
  35 #define VTG_HOST_ITM_BSET   0x008C
  36
  37 #define VTG_H_HD_1          0x00C0
  38 #define VTG_TOP_V_VD_1      0x00C4
  39 #define VTG_BOT_V_VD_1      0x00C8
  40 #define VTG_TOP_V_HD_1      0x00CC
  41 #define VTG_BOT_V_HD_1      0x00D0
  42
  43 #define VTG_H_HD_2          0x00E0
  44 #define VTG_TOP_V_VD_2      0x00E4
  45 #define VTG_BOT_V_VD_2      0x00E8
  46 #define VTG_TOP_V_HD_2      0x00EC
  47 #define VTG_BOT_V_HD_2      0x00F0
  48
  49 #define VTG_H_HD_3          0x0100
  50 #define VTG_TOP_V_VD_3      0x0104
  51 #define VTG_BOT_V_VD_3      0x0108
  52 #define VTG_TOP_V_HD_3      0x010C
  53 #define VTG_BOT_V_HD_3      0x0110
  54
  55 #define VTG_H_HD_4          0x0120
  56 #define VTG_TOP_V_VD_4      0x0124
  57 #define VTG_BOT_V_VD_4      0x0128
  58 #define VTG_TOP_V_HD_4      0x012c
  59 #define VTG_BOT_V_HD_4      0x0130
  60
  61 #define VTG_IRQ_BOTTOM      BIT(0)
  62 #define VTG_IRQ_TOP         BIT(1)
  63 #define VTG_IRQ_MASK        (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
  64
  65 /* Delay introduced by the HDMI in nb of pixel */
  66 #define HDMI_DELAY          (5)
  67
  68 /* Delay introduced by the DVO in nb of pixel */
  69 #define DVO_DELAY           (7)
  70
  71 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
  72 #define AWG_DELAY_HD        (-9)
  73 #define AWG_DELAY_ED        (-8)
  74 #define AWG_DELAY_SD        (-7)
  75
  76 static LIST_HEAD(vtg_lookup);
  77
  78 /*
  79  * STI VTG register offset structure
  80  *
  81  *@h_hd:     stores the VTG_H_HD_x     register offset
  82  *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
  83  *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
  84  *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
  85  *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
  86  */
  87 struct sti_vtg_regs_offs {
  88         u32 h_hd;
  89         u32 top_v_vd;
  90         u32 bot_v_vd;
  91         u32 top_v_hd;
  92         u32 bot_v_hd;
  93 };
  94
  95 #define VTG_MAX_SYNC_OUTPUT 4
  96 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
  97         { VTG_H_HD_1,
  98           VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
  99         { VTG_H_HD_2,
 100           VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
 101         { VTG_H_HD_3,
 102           VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
 103         { VTG_H_HD_4,
 104           VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
 105 };
 106
 107 /*
 108  * STI VTG synchronisation parameters structure
 109  *
 110  *@hsync: sample number falling and rising edge
 111  *@vsync_line_top: vertical top field line number falling and rising edge
 112  *@vsync_line_bot: vertical bottom field line number falling and rising edge
 113  *@vsync_off_top: vertical top field sample number rising and falling edge
 114  *@vsync_off_bot: vertical bottom field sample number rising and falling edge
 115  */
 116 struct sti_vtg_sync_params {
 117         u32 hsync;
 118         u32 vsync_line_top;
 119         u32 vsync_line_bot;
 120         u32 vsync_off_top;
 121         u32 vsync_off_bot;
 122 };
 123
 124 /**
 125  * STI VTG structure
 126  *
 127  * @dev: pointer to device driver
 128  * @np: device node
 129  * @regs: register mapping
 130  * @sync_params: synchronisation parameters used to generate timings
 131  * @irq: VTG irq
 132  * @irq_status: store the IRQ status value
 133  * @notifier_list: notifier callback
 134  * @crtc: the CRTC for vblank event
 135  * @slave: slave vtg
 136  * @link: List node to link the structure in lookup list
 137  */
 138 struct sti_vtg {
 139         struct device *dev;
 140         struct device_node *np;
 141         void __iomem *regs;
 142         struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
 143         int irq;
 144         u32 irq_status;
 145         struct raw_notifier_head notifier_list;
 146         struct drm_crtc *crtc;
 147         struct sti_vtg *slave;
 148         struct list_head link;
 149 };
 150
 151 static void vtg_register(struct sti_vtg *vtg)
 152 {
 153         list_add_tail(&vtg->link, &vtg_lookup);
 154 }
 155
 156 struct sti_vtg *of_vtg_find(struct device_node *np)
 157 {
 158         struct sti_vtg *vtg;
 159
 160         list_for_each_entry(vtg, &vtg_lookup, link) {
 161                 if (vtg->np == np)
 162                         return vtg;
 163         }
 164         return NULL;
 165 }
 166
 167 static void vtg_reset(struct sti_vtg *vtg)
 168 {
 169         /* reset slave and then master */
 170         if (vtg->slave)
 171                 vtg_reset(vtg->slave);
 172
 173         writel(1, vtg->regs + VTG_DRST_AUTOC);
 174 }
 175
 176 static void vtg_set_output_window(void __iomem *regs,
 177                                   const struct drm_display_mode *mode)
 178 {
 179         u32 video_top_field_start;
 180         u32 video_top_field_stop;
 181         u32 video_bottom_field_start;
 182         u32 video_bottom_field_stop;
 183         u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
 184         u32 ystart = sti_vtg_get_line_number(*mode, 0);
 185         u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 186         u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 187
 188         /* Set output window to fit the display mode selected */
 189         video_top_field_start = (ystart << 16) | xstart;
 190         video_top_field_stop = (ystop << 16) | xstop;
 191
 192         /* Only progressive supported for now */
 193         video_bottom_field_start = video_top_field_start;
 194         video_bottom_field_stop = video_top_field_stop;
 195
 196         writel(video_top_field_start, regs + VTG_VID_TFO);
 197         writel(video_top_field_stop, regs + VTG_VID_TFS);
 198         writel(video_bottom_field_start, regs + VTG_VID_BFO);
 199         writel(video_bottom_field_stop, regs + VTG_VID_BFS);
 200 }
 201
 202 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
 203                                     int delay,
 204                                     const struct drm_display_mode *mode)
 205 {
 206         long clocksperline, start, stop;
 207         u32 risesync_top, fallsync_top;
 208         u32 risesync_offs_top, fallsync_offs_top;
 209
 210         clocksperline = mode->htotal;
 211
 212         /* Get the hsync position */
 213         start = 0;
 214         stop = mode->hsync_end - mode->hsync_start;
 215
 216         start += delay;
 217         stop  += delay;
 218
 219         if (start < 0)
 220                 start += clocksperline;
 221         else if (start >= clocksperline)
 222                 start -= clocksperline;
 223
 224         if (stop < 0)
 225                 stop += clocksperline;
 226         else if (stop >= clocksperline)
 227                 stop -= clocksperline;
 228
 229         sync->hsync = (stop << 16) | start;
 230
 231         /* Get the vsync position */
 232         if (delay >= 0) {
 233                 risesync_top = 1;
 234                 fallsync_top = risesync_top;
 235                 fallsync_top += mode->vsync_end - mode->vsync_start;
 236
 237                 fallsync_offs_top = (u32)delay;
 238                 risesync_offs_top = (u32)delay;
 239         } else {
 240                 risesync_top = mode->vtotal;
 241                 fallsync_top = mode->vsync_end - mode->vsync_start;
 242
 243                 fallsync_offs_top = clocksperline + delay;
 244                 risesync_offs_top = clocksperline + delay;
 245         }
 246
 247         sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
 248         sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
 249
 250         /* Only progressive supported for now */
 251         sync->vsync_line_bot = sync->vsync_line_top;
 252         sync->vsync_off_bot = sync->vsync_off_top;
 253 }
 254
 255 static void vtg_set_mode(struct sti_vtg *vtg,
 256                          int type,
 257                          struct sti_vtg_sync_params *sync,
 258                          const struct drm_display_mode *mode)
 259 {
 260         unsigned int i;
 261
 262         if (vtg->slave)
 263                 vtg_set_mode(vtg->slave, VTG_MODE_SLAVE_BY_EXT0,
 264                              vtg->sync_params, mode);
 265
 266         /* Set the number of clock cycles per line */
 267         writel(mode->htotal, vtg->regs + VTG_CLKLN);
 268
 269         /* Set Half Line Per Field (only progressive supported for now) */
 270         writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
 271
 272         /* Program output window */
 273         vtg_set_output_window(vtg->regs, mode);
 274
 275         /* Set hsync and vsync position for HDMI */
 276         vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
 277
 278         /* Set hsync and vsync position for HD DCS */
 279         vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
 280
 281         /* Set hsync and vsync position for HDF */
 282         vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
 283
 284         /* Set hsync and vsync position for DVO */
 285         vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode);
 286
 287         /* Progam the syncs outputs */
 288         for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
 289                 writel(sync[i].hsync,
 290                        vtg->regs + vtg_regs_offs[i].h_hd);
 291                 writel(sync[i].vsync_line_top,
 292                        vtg->regs + vtg_regs_offs[i].top_v_vd);
 293                 writel(sync[i].vsync_line_bot,
 294                        vtg->regs + vtg_regs_offs[i].bot_v_vd);
 295                 writel(sync[i].vsync_off_top,
 296                        vtg->regs + vtg_regs_offs[i].top_v_hd);
 297                 writel(sync[i].vsync_off_bot,
 298                        vtg->regs + vtg_regs_offs[i].bot_v_hd);
 299         }
 300
 301         /* mode */
 302         writel(type, vtg->regs + VTG_MODE);
 303 }
 304
 305 static void vtg_enable_irq(struct sti_vtg *vtg)
 306 {
 307         /* clear interrupt status and mask */
 308         writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
 309         writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
 310         writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
 311 }
 312
 313 void sti_vtg_set_config(struct sti_vtg *vtg,
 314                 const struct drm_display_mode *mode)
 315 {
 316         /* write configuration */
 317         vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
 318
 319         vtg_reset(vtg);
 320
 321         /* enable irq for the vtg vblank synchro */
 322         if (vtg->slave)
 323                 vtg_enable_irq(vtg->slave);
 324         else
 325                 vtg_enable_irq(vtg);
 326 }
 327
 328 /**
 329  * sti_vtg_get_line_number
 330  *
 331  * @mode: display mode to be used
 332  * @y:    line
 333  *
 334  * Return the line number according to the display mode taking
 335  * into account the Sync and Back Porch information.
 336  * Video frame line numbers start at 1, y starts at 0.
 337  * In interlaced modes the start line is the field line number of the odd
 338  * field, but y is still defined as a progressive frame.
 339  */
 340 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
 341 {
 342         u32 start_line = mode.vtotal - mode.vsync_start + 1;
 343
 344         if (mode.flags & DRM_MODE_FLAG_INTERLACE)
 345                 start_line *= 2;
 346
 347         return start_line + y;
 348 }
 349
 350 /**
 351  * sti_vtg_get_pixel_number
 352  *
 353  * @mode: display mode to be used
 354  * @x:    row
 355  *
 356  * Return the pixel number according to the display mode taking
 357  * into account the Sync and Back Porch information.
 358  * Pixels are counted from 0.
 359  */
 360 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
 361 {
 362         return mode.htotal - mode.hsync_start + x;
 363 }
 364
 365 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
 366                             struct drm_crtc *crtc)
 367 {
 368         if (vtg->slave)
 369                 return sti_vtg_register_client(vtg->slave, nb, crtc);
 370
 371         vtg->crtc = crtc;
 372         return raw_notifier_chain_register(&vtg->notifier_list, nb);
 373 }
 374
 375 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
 376 {
 377         if (vtg->slave)
 378                 return sti_vtg_unregister_client(vtg->slave, nb);
 379
 380         return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
 381 }
 382
 383 static irqreturn_t vtg_irq_thread(int irq, void *arg)
 384 {
 385         struct sti_vtg *vtg = arg;
 386         u32 event;
 387
 388         event = (vtg->irq_status & VTG_IRQ_TOP) ?
 389                 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
 390
 391         raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
 392
 393         return IRQ_HANDLED;
 394 }
 395
 396 static irqreturn_t vtg_irq(int irq, void *arg)
 397 {
 398         struct sti_vtg *vtg = arg;
 399
 400         vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
 401
 402         writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
 403
 404         /* force sync bus write */
 405         readl(vtg->regs + VTG_HOST_ITS);
 406
 407         return IRQ_WAKE_THREAD;
 408 }
 409
 410 static int vtg_probe(struct platform_device *pdev)
 411 {
 412         struct device *dev = &pdev->dev;
 413         struct device_node *np;
 414         struct sti_vtg *vtg;
 415         struct resource *res;
 416         int ret;
 417
 418         vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
 419         if (!vtg)
 420                 return -ENOMEM;
 421
 422         vtg->dev = dev;
 423         vtg->np = pdev->dev.of_node;
 424
 425         /* Get Memory ressources */
 426         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 427         if (!res) {
 428                 DRM_ERROR("Get memory resource failed\n");
 429                 return -ENOMEM;
 430         }
 431         vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 432         if (!vtg->regs) {
 433                 DRM_ERROR("failed to remap I/O memory\n");
 434                 return -ENOMEM;
 435         }
 436
 437         np = of_parse_phandle(pdev->dev.of_node, "st,slave", 0);
 438         if (np) {
 439                 vtg->slave = of_vtg_find(np);
 440                 of_node_put(np);
 441
 442                 if (!vtg->slave)
 443                         return -EPROBE_DEFER;
 444         } else {
 445                 vtg->irq = platform_get_irq(pdev, 0);
 446                 if (vtg->irq < 0) {
 447                         DRM_ERROR("Failed to get VTG interrupt\n");
 448                         return vtg->irq;
 449                 }
 450
 451                 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
 452
 453                 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
 454                                 vtg_irq_thread, IRQF_ONESHOT,
 455                                 dev_name(dev), vtg);
 456                 if (ret < 0) {
 457                         DRM_ERROR("Failed to register VTG interrupt\n");
 458                         return ret;
 459                 }
 460         }
 461
 462         vtg_register(vtg);
 463         platform_set_drvdata(pdev, vtg);
 464
 465         DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev));
 466
 467         return 0;
 468 }
 469
 470 static int vtg_remove(struct platform_device *pdev)
 471 {
 472         return 0;
 473 }
 474
 475 static const struct of_device_id vtg_of_match[] = {
 476         { .compatible = "st,vtg", },
 477         { /* sentinel */ }
 478 };
 479 MODULE_DEVICE_TABLE(of, vtg_of_match);
 480
 481 struct platform_driver sti_vtg_driver = {
 482         .driver = {
 483                 .name = "sti-vtg",
 484                 .owner = THIS_MODULE,
 485                 .of_match_table = vtg_of_match,
 486         },
 487         .probe  = vtg_probe,
 488         .remove = vtg_remove,
 489 };
 490
 491 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 492 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
 493 MODULE_LICENSE("GPL");