drivers/gpu/drm/vc4/vc4_drv.h

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include "drmP.h"
  10 #include "drm_gem_cma_helper.h"
  11
  12 struct vc4_dev {
  13         struct drm_device *dev;
  14
  15         struct vc4_hdmi *hdmi;
  16         struct vc4_hvs *hvs;
  17         struct vc4_crtc *crtc[3];
  18         struct vc4_v3d *v3d;
  19         struct vc4_dpi *dpi;
  20
  21         struct drm_fbdev_cma *fbdev;
  22
  23         struct vc4_hang_state *hang_state;
  24
  25         /* The kernel-space BO cache.  Tracks buffers that have been
  26          * unreferenced by all other users (refcounts of 0!) but not
  27          * yet freed, so we can do cheap allocations.
  28          */
  29         struct vc4_bo_cache {
  30                 /* Array of list heads for entries in the BO cache,
  31                  * based on number of pages, so we can do O(1) lookups
  32                  * in the cache when allocating.
  33                  */
  34                 struct list_head *size_list;
  35                 uint32_t size_list_size;
  36
  37                 /* List of all BOs in the cache, ordered by age, so we
  38                  * can do O(1) lookups when trying to free old
  39                  * buffers.
  40                  */
  41                 struct list_head time_list;
  42                 struct work_struct time_work;
  43                 struct timer_list time_timer;
  44         } bo_cache;
  45
  46         struct vc4_bo_stats {
  47                 u32 num_allocated;
  48                 u32 size_allocated;
  49                 u32 num_cached;
  50                 u32 size_cached;
  51         } bo_stats;
  52
  53         /* Protects bo_cache and the BO stats. */
  54         struct mutex bo_lock;
  55
  56         /* Sequence number for the last job queued in bin_job_list.
  57          * Starts at 0 (no jobs emitted).
  58          */
  59         uint64_t emit_seqno;
  60
  61         /* Sequence number for the last completed job on the GPU.
  62          * Starts at 0 (no jobs completed).
  63          */
  64         uint64_t finished_seqno;
  65
  66         /* List of all struct vc4_exec_info for jobs to be executed in
  67          * the binner.  The first job in the list is the one currently
  68          * programmed into ct0ca for execution.
  69          */
  70         struct list_head bin_job_list;
  71
  72         /* List of all struct vc4_exec_info for jobs that have
  73          * completed binning and are ready for rendering.  The first
  74          * job in the list is the one currently programmed into ct1ca
  75          * for execution.
  76          */
  77         struct list_head render_job_list;
  78
  79         /* List of the finished vc4_exec_infos waiting to be freed by
  80          * job_done_work.
  81          */
  82         struct list_head job_done_list;
  83         /* Spinlock used to synchronize the job_list and seqno
  84          * accesses between the IRQ handler and GEM ioctls.
  85          */
  86         spinlock_t job_lock;
  87         wait_queue_head_t job_wait_queue;
  88         struct work_struct job_done_work;
  89
  90         /* List of struct vc4_seqno_cb for callbacks to be made from a
  91          * workqueue when the given seqno is passed.
  92          */
  93         struct list_head seqno_cb_list;
  94
  95         /* The binner overflow memory that's currently set up in
  96          * BPOA/BPOS registers.  When overflow occurs and a new one is
  97          * allocated, the previous one will be moved to
  98          * vc4->current_exec's free list.
  99          */
 100         struct vc4_bo *overflow_mem;
 101         struct work_struct overflow_mem_work;
 102
 103         int power_refcount;
 104
 105         /* Mutex controlling the power refcount. */
 106         struct mutex power_lock;
 107
 108         struct {
 109                 struct timer_list timer;
 110                 struct work_struct reset_work;
 111         } hangcheck;
 112
 113         struct semaphore async_modeset;
 114 };
 115
 116 static inline struct vc4_dev *
 117 to_vc4_dev(struct drm_device *dev)
 118 {
 119         return (struct vc4_dev *)dev->dev_private;
 120 }
 121
 122 struct vc4_bo {
 123         struct drm_gem_cma_object base;
 124
 125         /* seqno of the last job to render using this BO. */
 126         uint64_t seqno;
 127
 128         /* seqno of the last job to use the RCL to write to this BO.
 129          *
 130          * Note that this doesn't include binner overflow memory
 131          * writes.
 132          */
 133         uint64_t write_seqno;
 134
 135         /* List entry for the BO's position in either
 136          * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
 137          */
 138         struct list_head unref_head;
 139
 140         /* Time in jiffies when the BO was put in vc4->bo_cache. */
 141         unsigned long free_time;
 142
 143         /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
 144         struct list_head size_head;
 145
 146         /* Struct for shader validation state, if created by
 147          * DRM_IOCTL_VC4_CREATE_SHADER_BO.
 148          */
 149         struct vc4_validated_shader_info *validated_shader;
 150 };
 151
 152 static inline struct vc4_bo *
 153 to_vc4_bo(struct drm_gem_object *bo)
 154 {
 155         return (struct vc4_bo *)bo;
 156 }
 157
 158 struct vc4_seqno_cb {
 159         struct work_struct work;
 160         uint64_t seqno;
 161         void (*func)(struct vc4_seqno_cb *cb);
 162 };
 163
 164 struct vc4_v3d {
 165         struct vc4_dev *vc4;
 166         struct platform_device *pdev;
 167         void __iomem *regs;
 168 };
 169
 170 struct vc4_hvs {
 171         struct platform_device *pdev;
 172         void __iomem *regs;
 173         u32 __iomem *dlist;
 174
 175         /* Memory manager for CRTCs to allocate space in the display
 176          * list.  Units are dwords.
 177          */
 178         struct drm_mm dlist_mm;
 179         /* Memory manager for the LBM memory used by HVS scaling. */
 180         struct drm_mm lbm_mm;
 181         spinlock_t mm_lock;
 182
 183         struct drm_mm_node mitchell_netravali_filter;
 184 };
 185
 186 struct vc4_plane {
 187         struct drm_plane base;
 188 };
 189
 190 static inline struct vc4_plane *
 191 to_vc4_plane(struct drm_plane *plane)
 192 {
 193         return (struct vc4_plane *)plane;
 194 }
 195
 196 enum vc4_encoder_type {
 197         VC4_ENCODER_TYPE_NONE,
 198         VC4_ENCODER_TYPE_HDMI,
 199         VC4_ENCODER_TYPE_VEC,
 200         VC4_ENCODER_TYPE_DSI0,
 201         VC4_ENCODER_TYPE_DSI1,
 202         VC4_ENCODER_TYPE_SMI,
 203         VC4_ENCODER_TYPE_DPI,
 204 };
 205
 206 struct vc4_encoder {
 207         struct drm_encoder base;
 208         enum vc4_encoder_type type;
 209         u32 clock_select;
 210 };
 211
 212 static inline struct vc4_encoder *
 213 to_vc4_encoder(struct drm_encoder *encoder)
 214 {
 215         return container_of(encoder, struct vc4_encoder, base);
 216 }
 217
 218 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
 219 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
 220 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
 221 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
 222
 223 struct vc4_exec_info {
 224         /* Sequence number for this bin/render job. */
 225         uint64_t seqno;
 226
 227         /* Latest write_seqno of any BO that binning depends on. */
 228         uint64_t bin_dep_seqno;
 229
 230         /* Last current addresses the hardware was processing when the
 231          * hangcheck timer checked on us.
 232          */
 233         uint32_t last_ct0ca, last_ct1ca;
 234
 235         /* Kernel-space copy of the ioctl arguments */
 236         struct drm_vc4_submit_cl *args;
 237
 238         /* This is the array of BOs that were looked up at the start of exec.
 239          * Command validation will use indices into this array.
 240          */
 241         struct drm_gem_cma_object **bo;
 242         uint32_t bo_count;
 243
 244         /* List of BOs that are being written by the RCL.  Other than
 245          * the binner temporary storage, this is all the BOs written
 246          * by the job.
 247          */
 248         struct drm_gem_cma_object *rcl_write_bo[4];
 249         uint32_t rcl_write_bo_count;
 250
 251         /* Pointers for our position in vc4->job_list */
 252         struct list_head head;
 253
 254         /* List of other BOs used in the job that need to be released
 255          * once the job is complete.
 256          */
 257         struct list_head unref_list;
 258
 259         /* Current unvalidated indices into @bo loaded by the non-hardware
 260          * VC4_PACKET_GEM_HANDLES.
 261          */
 262         uint32_t bo_index[2];
 263
 264         /* This is the BO where we store the validated command lists, shader
 265          * records, and uniforms.
 266          */
 267         struct drm_gem_cma_object *exec_bo;
 268
 269         /**
 270          * This tracks the per-shader-record state (packet 64) that
 271          * determines the length of the shader record and the offset
 272          * it's expected to be found at.  It gets read in from the
 273          * command lists.
 274          */
 275         struct vc4_shader_state {
 276                 uint32_t addr;
 277                 /* Maximum vertex index referenced by any primitive using this
 278                  * shader state.
 279                  */
 280                 uint32_t max_index;
 281         } *shader_state;
 282
 283         /** How many shader states the user declared they were using. */
 284         uint32_t shader_state_size;
 285         /** How many shader state records the validator has seen. */
 286         uint32_t shader_state_count;
 287
 288         bool found_tile_binning_mode_config_packet;
 289         bool found_start_tile_binning_packet;
 290         bool found_increment_semaphore_packet;
 291         bool found_flush;
 292         uint8_t bin_tiles_x, bin_tiles_y;
 293         struct drm_gem_cma_object *tile_bo;
 294         uint32_t tile_alloc_offset;
 295
 296         /**
 297          * Computed addresses pointing into exec_bo where we start the
 298          * bin thread (ct0) and render thread (ct1).
 299          */
 300         uint32_t ct0ca, ct0ea;
 301         uint32_t ct1ca, ct1ea;
 302
 303         /* Pointer to the unvalidated bin CL (if present). */
 304         void *bin_u;
 305
 306         /* Pointers to the shader recs.  These paddr gets incremented as CL
 307          * packets are relocated in validate_gl_shader_state, and the vaddrs
 308          * (u and v) get incremented and size decremented as the shader recs
 309          * themselves are validated.
 310          */
 311         void *shader_rec_u;
 312         void *shader_rec_v;
 313         uint32_t shader_rec_p;
 314         uint32_t shader_rec_size;
 315
 316         /* Pointers to the uniform data.  These pointers are incremented, and
 317          * size decremented, as each batch of uniforms is uploaded.
 318          */
 319         void *uniforms_u;
 320         void *uniforms_v;
 321         uint32_t uniforms_p;
 322         uint32_t uniforms_size;
 323 };
 324
 325 static inline struct vc4_exec_info *
 326 vc4_first_bin_job(struct vc4_dev *vc4)
 327 {
 328         return list_first_entry_or_null(&vc4->bin_job_list,
 329                                         struct vc4_exec_info, head);
 330 }
 331
 332 static inline struct vc4_exec_info *
 333 vc4_first_render_job(struct vc4_dev *vc4)
 334 {
 335         return list_first_entry_or_null(&vc4->render_job_list,
 336                                         struct vc4_exec_info, head);
 337 }
 338
 339 static inline struct vc4_exec_info *
 340 vc4_last_render_job(struct vc4_dev *vc4)
 341 {
 342         if (list_empty(&vc4->render_job_list))
 343                 return NULL;
 344         return list_last_entry(&vc4->render_job_list,
 345                                struct vc4_exec_info, head);
 346 }
 347
 348 /**
 349  * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
 350  * setup parameters.
 351  *
 352  * This will be used at draw time to relocate the reference to the texture
 353  * contents in p0, and validate that the offset combined with
 354  * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
 355  * Note that the hardware treats unprovided config parameters as 0, so not all
 356  * of them need to be set up for every texure sample, and we'll store ~0 as
 357  * the offset to mark the unused ones.
 358  *
 359  * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
 360  * Setup") for definitions of the texture parameters.
 361  */
 362 struct vc4_texture_sample_info {
 363         bool is_direct;
 364         uint32_t p_offset[4];
 365 };
 366
 367 /**
 368  * struct vc4_validated_shader_info - information about validated shaders that
 369  * needs to be used from command list validation.
 370  *
 371  * For a given shader, each time a shader state record references it, we need
 372  * to verify that the shader doesn't read more uniforms than the shader state
 373  * record's uniform BO pointer can provide, and we need to apply relocations
 374  * and validate the shader state record's uniforms that define the texture
 375  * samples.
 376  */
 377 struct vc4_validated_shader_info {
 378         uint32_t uniforms_size;
 379         uint32_t uniforms_src_size;
 380         uint32_t num_texture_samples;
 381         struct vc4_texture_sample_info *texture_samples;
 382
 383         uint32_t num_uniform_addr_offsets;
 384         uint32_t *uniform_addr_offsets;
 385 };
 386
 387 /**
 388  * _wait_for - magic (register) wait macro
 389  *
 390  * Does the right thing for modeset paths when run under kdgb or similar atomic
 391  * contexts. Note that it's important that we check the condition again after
 392  * having timed out, since the timeout could be due to preemption or similar and
 393  * we've never had a chance to check the condition before the timeout.
 394  */
 395 #define _wait_for(COND, MS, W) ({ \
 396         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
 397         int ret__ = 0;                                                  \
 398         while (!(COND)) {                                               \
 399                 if (time_after(jiffies, timeout__)) {                   \
 400                         if (!(COND))                                    \
 401                                 ret__ = -ETIMEDOUT;                     \
 402                         break;                                          \
 403                 }                                                       \
 404                 if (W && drm_can_sleep())  {                            \
 405                         msleep(W);                                      \
 406                 } else {                                                \
 407                         cpu_relax();                                    \
 408                 }                                                       \
 409         }                                                               \
 410         ret__;                                                          \
 411 })
 412
 413 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 414
 415 /* vc4_bo.c */
 416 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 417 void vc4_free_object(struct drm_gem_object *gem_obj);
 418 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 419                              bool from_cache);
 420 int vc4_dumb_create(struct drm_file *file_priv,
 421                     struct drm_device *dev,
 422                     struct drm_mode_create_dumb *args);
 423 struct dma_buf *vc4_prime_export(struct drm_device *dev,
 424                                  struct drm_gem_object *obj, int flags);
 425 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 426                         struct drm_file *file_priv);
 427 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 428                                struct drm_file *file_priv);
 429 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 430                       struct drm_file *file_priv);
 431 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 432                              struct drm_file *file_priv);
 433 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
 434 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 435 void *vc4_prime_vmap(struct drm_gem_object *obj);
 436 void vc4_bo_cache_init(struct drm_device *dev);
 437 void vc4_bo_cache_destroy(struct drm_device *dev);
 438 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
 439
 440 /* vc4_crtc.c */
 441 extern struct platform_driver vc4_crtc_driver;
 442 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
 443 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
 444 bool vc4_event_pending(struct drm_crtc *crtc);
 445 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
 446 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 447                             unsigned int flags, int *vpos, int *hpos,
 448                             ktime_t *stime, ktime_t *etime,
 449                             const struct drm_display_mode *mode);
 450 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 451                                   int *max_error, struct timeval *vblank_time,
 452                                   unsigned flags);
 453
 454 /* vc4_debugfs.c */
 455 int vc4_debugfs_init(struct drm_minor *minor);
 456 void vc4_debugfs_cleanup(struct drm_minor *minor);
 457
 458 /* vc4_drv.c */
 459 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
 460
 461 /* vc4_dpi.c */
 462 extern struct platform_driver vc4_dpi_driver;
 463 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
 464
 465 /* vc4_gem.c */
 466 void vc4_gem_init(struct drm_device *dev);
 467 void vc4_gem_destroy(struct drm_device *dev);
 468 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 469                         struct drm_file *file_priv);
 470 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 471                          struct drm_file *file_priv);
 472 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 473                       struct drm_file *file_priv);
 474 void vc4_submit_next_bin_job(struct drm_device *dev);
 475 void vc4_submit_next_render_job(struct drm_device *dev);
 476 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
 477 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
 478                        uint64_t timeout_ns, bool interruptible);
 479 void vc4_job_handle_completed(struct vc4_dev *vc4);
 480 int vc4_queue_seqno_cb(struct drm_device *dev,
 481                        struct vc4_seqno_cb *cb, uint64_t seqno,
 482                        void (*func)(struct vc4_seqno_cb *cb));
 483
 484 /* vc4_hdmi.c */
 485 extern struct platform_driver vc4_hdmi_driver;
 486 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
 487
 488 /* vc4_irq.c */
 489 irqreturn_t vc4_irq(int irq, void *arg);
 490 void vc4_irq_preinstall(struct drm_device *dev);
 491 int vc4_irq_postinstall(struct drm_device *dev);
 492 void vc4_irq_uninstall(struct drm_device *dev);
 493 void vc4_irq_reset(struct drm_device *dev);
 494
 495 /* vc4_hvs.c */
 496 extern struct platform_driver vc4_hvs_driver;
 497 void vc4_hvs_dump_state(struct drm_device *dev);
 498 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
 499
 500 /* vc4_kms.c */
 501 int vc4_kms_load(struct drm_device *dev);
 502
 503 /* vc4_plane.c */
 504 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 505                                  enum drm_plane_type type);
 506 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
 507 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
 508 void vc4_plane_async_set_fb(struct drm_plane *plane,
 509                             struct drm_framebuffer *fb);
 510
 511 /* vc4_v3d.c */
 512 extern struct platform_driver vc4_v3d_driver;
 513 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
 514 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
 515
 516 /* vc4_validate.c */
 517 int
 518 vc4_validate_bin_cl(struct drm_device *dev,
 519                     void *validated,
 520                     void *unvalidated,
 521                     struct vc4_exec_info *exec);
 522
 523 int
 524 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 525
 526 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
 527                                       uint32_t hindex);
 528
 529 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
 530
 531 bool vc4_check_tex_size(struct vc4_exec_info *exec,
 532                         struct drm_gem_cma_object *fbo,
 533                         uint32_t offset, uint8_t tiling_format,
 534                         uint32_t width, uint32_t height, uint8_t cpp);
 535
 536 /* vc4_validate_shader.c */
 537 struct vc4_validated_shader_info *
 538 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);