drivers/media/platform/davinci/vpss.c

   1 /*
   2  * Copyright (C) 2009 Texas Instruments.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  * common vpss system module platform driver for all video drivers.
  19  */
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/err.h>
  25
  26 #include <media/davinci/vpss.h>
  27
  28 MODULE_LICENSE("GPL");
  29 MODULE_DESCRIPTION("VPSS Driver");
  30 MODULE_AUTHOR("Texas Instruments");
  31
  32 /* DM644x defines */
  33 #define DM644X_SBL_PCR_VPSS             (4)
  34
  35 #define DM355_VPSSBL_INTSEL             0x10
  36 #define DM355_VPSSBL_EVTSEL             0x14
  37 /* vpss BL register offsets */
  38 #define DM355_VPSSBL_CCDCMUX            0x1c
  39 /* vpss CLK register offsets */
  40 #define DM355_VPSSCLK_CLKCTRL           0x04
  41 /* masks and shifts */
  42 #define VPSS_HSSISEL_SHIFT              4
  43 /*
  44  * VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
  45  * IPIPE_INT1_SDR - vpss_int5
  46  */
  47 #define DM355_VPSSBL_INTSEL_DEFAULT     0xff83ff10
  48 /* VENCINT - vpss_int8 */
  49 #define DM355_VPSSBL_EVTSEL_DEFAULT     0x4
  50
  51 #define DM365_ISP5_PCCR                         0x04
  52 #define DM365_ISP5_PCCR_BL_CLK_ENABLE           BIT(0)
  53 #define DM365_ISP5_PCCR_ISIF_CLK_ENABLE         BIT(1)
  54 #define DM365_ISP5_PCCR_H3A_CLK_ENABLE          BIT(2)
  55 #define DM365_ISP5_PCCR_RSZ_CLK_ENABLE          BIT(3)
  56 #define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE        BIT(4)
  57 #define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE      BIT(5)
  58 #define DM365_ISP5_PCCR_RSV                     BIT(6)
  59
  60 #define DM365_ISP5_BCR                  0x08
  61 #define DM365_ISP5_BCR_ISIF_OUT_ENABLE  BIT(1)
  62
  63 #define DM365_ISP5_INTSEL1              0x10
  64 #define DM365_ISP5_INTSEL2              0x14
  65 #define DM365_ISP5_INTSEL3              0x18
  66 #define DM365_ISP5_CCDCMUX              0x20
  67 #define DM365_ISP5_PG_FRAME_SIZE        0x28
  68 #define DM365_VPBE_CLK_CTRL             0x00
  69
  70 #define VPSS_CLK_CTRL                   0x01c40044
  71 #define VPSS_CLK_CTRL_VENCCLKEN         BIT(3)
  72 #define VPSS_CLK_CTRL_DACCLKEN          BIT(4)
  73
  74 /*
  75  * vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
  76  * AF - vpss_int3
  77  */
  78 #define DM365_ISP5_INTSEL1_DEFAULT      0x0b1f0100
  79 /* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
  80 #define DM365_ISP5_INTSEL2_DEFAULT      0x1f0a0f1f
  81 /* VENC - vpss_int8 */
  82 #define DM365_ISP5_INTSEL3_DEFAULT      0x00000015
  83
  84 /* masks and shifts for DM365*/
  85 #define DM365_CCDC_PG_VD_POL_SHIFT      0
  86 #define DM365_CCDC_PG_HD_POL_SHIFT      1
  87
  88 #define CCD_SRC_SEL_MASK                (BIT_MASK(5) | BIT_MASK(4))
  89 #define CCD_SRC_SEL_SHIFT               4
  90
  91 /* Different SoC platforms supported by this driver */
  92 enum vpss_platform_type {
  93         DM644X,
  94         DM355,
  95         DM365,
  96 };
  97
  98 /*
  99  * vpss operations. Depends on platform. Not all functions are available
 100  * on all platforms. The api, first check if a function is available before
 101  * invoking it. In the probe, the function ptrs are initialized based on
 102  * vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
 103  */
 104 struct vpss_hw_ops {
 105         /* enable clock */
 106         int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
 107         /* select input to ccdc */
 108         void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
 109         /* clear wbl overflow bit */
 110         int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
 111         /* set sync polarity */
 112         void (*set_sync_pol)(struct vpss_sync_pol);
 113         /* set the PG_FRAME_SIZE register*/
 114         void (*set_pg_frame_size)(struct vpss_pg_frame_size);
 115         /* check and clear interrupt if occurred */
 116         int (*dma_complete_interrupt)(void);
 117 };
 118
 119 /* vpss configuration */
 120 struct vpss_oper_config {
 121         __iomem void *vpss_regs_base0;
 122         __iomem void *vpss_regs_base1;
 123         resource_size_t *vpss_regs_base2;
 124         enum vpss_platform_type platform;
 125         spinlock_t vpss_lock;
 126         struct vpss_hw_ops hw_ops;
 127 };
 128
 129 static struct vpss_oper_config oper_cfg;
 130
 131 /* register access routines */
 132 static inline u32 bl_regr(u32 offset)
 133 {
 134         return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
 135 }
 136
 137 static inline void bl_regw(u32 val, u32 offset)
 138 {
 139         __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
 140 }
 141
 142 static inline u32 vpss_regr(u32 offset)
 143 {
 144         return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
 145 }
 146
 147 static inline void vpss_regw(u32 val, u32 offset)
 148 {
 149         __raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
 150 }
 151
 152 /* For DM365 only */
 153 static inline u32 isp5_read(u32 offset)
 154 {
 155         return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
 156 }
 157
 158 /* For DM365 only */
 159 static inline void isp5_write(u32 val, u32 offset)
 160 {
 161         __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
 162 }
 163
 164 static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
 165 {
 166         u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
 167
 168         /* if we are using pattern generator, enable it */
 169         if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
 170                 temp |= 0x08;
 171
 172         temp |= (src_sel << CCD_SRC_SEL_SHIFT);
 173         isp5_write(temp, DM365_ISP5_CCDCMUX);
 174 }
 175
 176 static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
 177 {
 178         bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
 179 }
 180
 181 int vpss_dma_complete_interrupt(void)
 182 {
 183         if (!oper_cfg.hw_ops.dma_complete_interrupt)
 184                 return 2;
 185         return oper_cfg.hw_ops.dma_complete_interrupt();
 186 }
 187 EXPORT_SYMBOL(vpss_dma_complete_interrupt);
 188
 189 int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
 190 {
 191         if (!oper_cfg.hw_ops.select_ccdc_source)
 192                 return -EINVAL;
 193
 194         oper_cfg.hw_ops.select_ccdc_source(src_sel);
 195         return 0;
 196 }
 197 EXPORT_SYMBOL(vpss_select_ccdc_source);
 198
 199 static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
 200 {
 201         u32 mask = 1, val;
 202
 203         if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
 204             wbl_sel > VPSS_PCR_CCDC_WBL_O)
 205                 return -EINVAL;
 206
 207         /* writing a 0 clear the overflow */
 208         mask = ~(mask << wbl_sel);
 209         val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
 210         bl_regw(val, DM644X_SBL_PCR_VPSS);
 211         return 0;
 212 }
 213
 214 void vpss_set_sync_pol(struct vpss_sync_pol sync)
 215 {
 216         if (!oper_cfg.hw_ops.set_sync_pol)
 217                 return;
 218
 219         oper_cfg.hw_ops.set_sync_pol(sync);
 220 }
 221 EXPORT_SYMBOL(vpss_set_sync_pol);
 222
 223 int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
 224 {
 225         if (!oper_cfg.hw_ops.clear_wbl_overflow)
 226                 return -EINVAL;
 227
 228         return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
 229 }
 230 EXPORT_SYMBOL(vpss_clear_wbl_overflow);
 231
 232 /*
 233  *  dm355_enable_clock - Enable VPSS Clock
 234  *  @clock_sel: Clock to be enabled/disabled
 235  *  @en: enable/disable flag
 236  *
 237  *  This is called to enable or disable a vpss clock
 238  */
 239 static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
 240 {
 241         unsigned long flags;
 242         u32 utemp, mask = 0x1, shift = 0;
 243
 244         switch (clock_sel) {
 245         case VPSS_VPBE_CLOCK:
 246                 /* nothing since lsb */
 247                 break;
 248         case VPSS_VENC_CLOCK_SEL:
 249                 shift = 2;
 250                 break;
 251         case VPSS_CFALD_CLOCK:
 252                 shift = 3;
 253                 break;
 254         case VPSS_H3A_CLOCK:
 255                 shift = 4;
 256                 break;
 257         case VPSS_IPIPE_CLOCK:
 258                 shift = 5;
 259                 break;
 260         case VPSS_CCDC_CLOCK:
 261                 shift = 6;
 262                 break;
 263         default:
 264                 printk(KERN_ERR "dm355_enable_clock:"
 265                                 " Invalid selector: %d\n", clock_sel);
 266                 return -EINVAL;
 267         }
 268
 269         spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
 270         utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
 271         if (!en)
 272                 utemp &= ~(mask << shift);
 273         else
 274                 utemp |= (mask << shift);
 275
 276         vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
 277         spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
 278         return 0;
 279 }
 280
 281 static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
 282 {
 283         unsigned long flags;
 284         u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
 285         u32 (*read)(u32 offset) = isp5_read;
 286         void(*write)(u32 val, u32 offset) = isp5_write;
 287
 288         switch (clock_sel) {
 289         case VPSS_BL_CLOCK:
 290                 break;
 291         case VPSS_CCDC_CLOCK:
 292                 shift = 1;
 293                 break;
 294         case VPSS_H3A_CLOCK:
 295                 shift = 2;
 296                 break;
 297         case VPSS_RSZ_CLOCK:
 298                 shift = 3;
 299                 break;
 300         case VPSS_IPIPE_CLOCK:
 301                 shift = 4;
 302                 break;
 303         case VPSS_IPIPEIF_CLOCK:
 304                 shift = 5;
 305                 break;
 306         case VPSS_PCLK_INTERNAL:
 307                 shift = 6;
 308                 break;
 309         case VPSS_PSYNC_CLOCK_SEL:
 310                 shift = 7;
 311                 break;
 312         case VPSS_VPBE_CLOCK:
 313                 read = vpss_regr;
 314                 write = vpss_regw;
 315                 offset = DM365_VPBE_CLK_CTRL;
 316                 break;
 317         case VPSS_VENC_CLOCK_SEL:
 318                 shift = 2;
 319                 read = vpss_regr;
 320                 write = vpss_regw;
 321                 offset = DM365_VPBE_CLK_CTRL;
 322                 break;
 323         case VPSS_LDC_CLOCK:
 324                 shift = 3;
 325                 read = vpss_regr;
 326                 write = vpss_regw;
 327                 offset = DM365_VPBE_CLK_CTRL;
 328                 break;
 329         case VPSS_FDIF_CLOCK:
 330                 shift = 4;
 331                 read = vpss_regr;
 332                 write = vpss_regw;
 333                 offset = DM365_VPBE_CLK_CTRL;
 334                 break;
 335         case VPSS_OSD_CLOCK_SEL:
 336                 shift = 6;
 337                 read = vpss_regr;
 338                 write = vpss_regw;
 339                 offset = DM365_VPBE_CLK_CTRL;
 340                 break;
 341         case VPSS_LDC_CLOCK_SEL:
 342                 shift = 7;
 343                 read = vpss_regr;
 344                 write = vpss_regw;
 345                 offset = DM365_VPBE_CLK_CTRL;
 346                 break;
 347         default:
 348                 printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
 349                        clock_sel);
 350                 return -1;
 351         }
 352
 353         spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
 354         utemp = read(offset);
 355         if (!en) {
 356                 mask = ~mask;
 357                 utemp &= (mask << shift);
 358         } else
 359                 utemp |= (mask << shift);
 360
 361         write(utemp, offset);
 362         spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
 363
 364         return 0;
 365 }
 366
 367 int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
 368 {
 369         if (!oper_cfg.hw_ops.enable_clock)
 370                 return -EINVAL;
 371
 372         return oper_cfg.hw_ops.enable_clock(clock_sel, en);
 373 }
 374 EXPORT_SYMBOL(vpss_enable_clock);
 375
 376 void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
 377 {
 378         int val = 0;
 379         val = isp5_read(DM365_ISP5_CCDCMUX);
 380
 381         val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
 382         val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
 383
 384         isp5_write(val, DM365_ISP5_CCDCMUX);
 385 }
 386 EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
 387
 388 void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
 389 {
 390         if (!oper_cfg.hw_ops.set_pg_frame_size)
 391                 return;
 392
 393         oper_cfg.hw_ops.set_pg_frame_size(frame_size);
 394 }
 395 EXPORT_SYMBOL(vpss_set_pg_frame_size);
 396
 397 void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
 398 {
 399         int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
 400
 401         current_reg |= (frame_size.pplen - 1);
 402         isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
 403 }
 404 EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
 405
 406 static int vpss_probe(struct platform_device *pdev)
 407 {
 408         struct resource *res;
 409         char *platform_name;
 410
 411         if (!pdev->dev.platform_data) {
 412                 dev_err(&pdev->dev, "no platform data\n");
 413                 return -ENOENT;
 414         }
 415
 416         platform_name = pdev->dev.platform_data;
 417         if (!strcmp(platform_name, "dm355_vpss"))
 418                 oper_cfg.platform = DM355;
 419         else if (!strcmp(platform_name, "dm365_vpss"))
 420                 oper_cfg.platform = DM365;
 421         else if (!strcmp(platform_name, "dm644x_vpss"))
 422                 oper_cfg.platform = DM644X;
 423         else {
 424                 dev_err(&pdev->dev, "vpss driver not supported on"
 425                         " this platform\n");
 426                 return -ENODEV;
 427         }
 428
 429         dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
 430         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 431
 432         oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res);
 433         if (IS_ERR(oper_cfg.vpss_regs_base0))
 434                 return PTR_ERR(oper_cfg.vpss_regs_base0);
 435
 436         if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
 437                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 438
 439                 oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev,
 440                                                                  res);
 441                 if (IS_ERR(oper_cfg.vpss_regs_base1))
 442                         return PTR_ERR(oper_cfg.vpss_regs_base1);
 443         }
 444
 445         if (oper_cfg.platform == DM355) {
 446                 oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
 447                 oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
 448                 /* Setup vpss interrupts */
 449                 bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
 450                 bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
 451         } else if (oper_cfg.platform == DM365) {
 452                 oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
 453                 oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
 454                 /* Setup vpss interrupts */
 455                 isp5_write((isp5_read(DM365_ISP5_PCCR) |
 456                                       DM365_ISP5_PCCR_BL_CLK_ENABLE |
 457                                       DM365_ISP5_PCCR_ISIF_CLK_ENABLE |
 458                                       DM365_ISP5_PCCR_H3A_CLK_ENABLE |
 459                                       DM365_ISP5_PCCR_RSZ_CLK_ENABLE |
 460                                       DM365_ISP5_PCCR_IPIPE_CLK_ENABLE |
 461                                       DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE |
 462                                       DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
 463                 isp5_write((isp5_read(DM365_ISP5_BCR) |
 464                             DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
 465                 isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
 466                 isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
 467                 isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
 468         } else
 469                 oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
 470
 471         pm_runtime_enable(&pdev->dev);
 472
 473         pm_runtime_get(&pdev->dev);
 474
 475         spin_lock_init(&oper_cfg.vpss_lock);
 476         dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
 477
 478         return 0;
 479 }
 480
 481 static int vpss_remove(struct platform_device *pdev)
 482 {
 483         pm_runtime_disable(&pdev->dev);
 484         return 0;
 485 }
 486
 487 static int vpss_suspend(struct device *dev)
 488 {
 489         pm_runtime_put(dev);
 490         return 0;
 491 }
 492
 493 static int vpss_resume(struct device *dev)
 494 {
 495         pm_runtime_get(dev);
 496         return 0;
 497 }
 498
 499 static const struct dev_pm_ops vpss_pm_ops = {
 500         .suspend = vpss_suspend,
 501         .resume = vpss_resume,
 502 };
 503
 504 static struct platform_driver vpss_driver = {
 505         .driver = {
 506                 .name   = "vpss",
 507                 .pm = &vpss_pm_ops,
 508         },
 509         .remove = vpss_remove,
 510         .probe = vpss_probe,
 511 };
 512
 513 static void vpss_exit(void)
 514 {
 515         iounmap(oper_cfg.vpss_regs_base2);
 516         release_mem_region(VPSS_CLK_CTRL, 4);
 517         platform_driver_unregister(&vpss_driver);
 518 }
 519
 520 static int __init vpss_init(void)
 521 {
 522         if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
 523                 return -EBUSY;
 524
 525         oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
 526         writel(VPSS_CLK_CTRL_VENCCLKEN |
 527                      VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);
 528
 529         return platform_driver_register(&vpss_driver);
 530 }
 531 subsys_initcall(vpss_init);
 532 module_exit(vpss_exit);