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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blob8051c13456922242e69d702d9e4b249919003e5d
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
37
38 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40
41 int mfc_debug_level;
42 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44
45 /* Helper functions for interrupt processing */
46
47 /* Remove from hw execution round robin */
48 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 {
50 struct s5p_mfc_dev *dev = ctx->dev;
51
52 spin_lock(&dev->condlock);
53 __clear_bit(ctx->num, &dev->ctx_work_bits);
54 spin_unlock(&dev->condlock);
55 }
56
57 /* Add to hw execution round robin */
58 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 {
60 struct s5p_mfc_dev *dev = ctx->dev;
61
62 spin_lock(&dev->condlock);
63 __set_bit(ctx->num, &dev->ctx_work_bits);
64 spin_unlock(&dev->condlock);
65 }
66
67 /* Remove from hw execution round robin */
68 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 {
70 struct s5p_mfc_dev *dev = ctx->dev;
71 unsigned long flags;
72
73 spin_lock_irqsave(&dev->condlock, flags);
74 __clear_bit(ctx->num, &dev->ctx_work_bits);
75 spin_unlock_irqrestore(&dev->condlock, flags);
76 }
77
78 /* Add to hw execution round robin */
79 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 {
81 struct s5p_mfc_dev *dev = ctx->dev;
82 unsigned long flags;
83
84 spin_lock_irqsave(&dev->condlock, flags);
85 __set_bit(ctx->num, &dev->ctx_work_bits);
86 spin_unlock_irqrestore(&dev->condlock, flags);
87 }
88
89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
90 {
91 unsigned long flags;
92 int ctx;
93
94 spin_lock_irqsave(&dev->condlock, flags);
95 ctx = dev->curr_ctx;
96 do {
97 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
98 if (ctx == dev->curr_ctx) {
99 if (!test_bit(ctx, &dev->ctx_work_bits))
100 ctx = -EAGAIN;
101 break;
102 }
103 } while (!test_bit(ctx, &dev->ctx_work_bits));
104 spin_unlock_irqrestore(&dev->condlock, flags);
105
106 return ctx;
107 }
108
109 /* Wake up context wait_queue */
110 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
111 unsigned int err)
112 {
113 ctx->int_cond = 1;
114 ctx->int_type = reason;
115 ctx->int_err = err;
116 wake_up(&ctx->queue);
117 }
118
119 /* Wake up device wait_queue */
120 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
121 unsigned int err)
122 {
123 dev->int_cond = 1;
124 dev->int_type = reason;
125 dev->int_err = err;
126 wake_up(&dev->queue);
127 }
128
129 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
130 {
131 struct s5p_mfc_buf *b;
132 int i;
133
134 while (!list_empty(lh)) {
135 b = list_entry(lh->next, struct s5p_mfc_buf, list);
136 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
137 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
138 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
139 list_del(&b->list);
140 }
141 }
142
143 static void s5p_mfc_watchdog(unsigned long arg)
144 {
145 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
146
147 if (test_bit(0, &dev->hw_lock))
148 atomic_inc(&dev->watchdog_cnt);
149 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
150 /* This means that hw is busy and no interrupts were
151 * generated by hw for the Nth time of running this
152 * watchdog timer. This usually means a serious hw
153 * error. Now it is time to kill all instances and
154 * reset the MFC. */
155 mfc_err("Time out during waiting for HW\n");
156 schedule_work(&dev->watchdog_work);
157 }
158 dev->watchdog_timer.expires = jiffies +
159 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
160 add_timer(&dev->watchdog_timer);
161 }
162
163 static void s5p_mfc_watchdog_worker(struct work_struct *work)
164 {
165 struct s5p_mfc_dev *dev;
166 struct s5p_mfc_ctx *ctx;
167 unsigned long flags;
168 int mutex_locked;
169 int i, ret;
170
171 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
172
173 mfc_err("Driver timeout error handling\n");
174 /* Lock the mutex that protects open and release.
175 * This is necessary as they may load and unload firmware. */
176 mutex_locked = mutex_trylock(&dev->mfc_mutex);
177 if (!mutex_locked)
178 mfc_err("Error: some instance may be closing/opening\n");
179 spin_lock_irqsave(&dev->irqlock, flags);
180
181 s5p_mfc_clock_off();
182
183 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
184 ctx = dev->ctx[i];
185 if (!ctx)
186 continue;
187 ctx->state = MFCINST_ERROR;
188 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
189 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
190 clear_work_bit(ctx);
191 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
192 }
193 clear_bit(0, &dev->hw_lock);
194 spin_unlock_irqrestore(&dev->irqlock, flags);
195
196 /* De-init MFC */
197 s5p_mfc_deinit_hw(dev);
198
199 /* Double check if there is at least one instance running.
200 * If no instance is in memory than no firmware should be present */
201 if (dev->num_inst > 0) {
202 ret = s5p_mfc_load_firmware(dev);
203 if (ret) {
204 mfc_err("Failed to reload FW\n");
205 goto unlock;
206 }
207 s5p_mfc_clock_on();
208 ret = s5p_mfc_init_hw(dev);
209 s5p_mfc_clock_off();
210 if (ret)
211 mfc_err("Failed to reinit FW\n");
212 }
213 unlock:
214 if (mutex_locked)
215 mutex_unlock(&dev->mfc_mutex);
216 }
217
218 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
219 {
220 struct s5p_mfc_buf *dst_buf;
221 struct s5p_mfc_dev *dev = ctx->dev;
222
223 ctx->state = MFCINST_FINISHED;
224 ctx->sequence++;
225 while (!list_empty(&ctx->dst_queue)) {
226 dst_buf = list_entry(ctx->dst_queue.next,
227 struct s5p_mfc_buf, list);
228 mfc_debug(2, "Cleaning up buffer: %d\n",
229 dst_buf->b->vb2_buf.index);
230 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
231 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
232 list_del(&dst_buf->list);
233 dst_buf->flags |= MFC_BUF_FLAG_EOS;
234 ctx->dst_queue_cnt--;
235 dst_buf->b->sequence = (ctx->sequence++);
236
237 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
238 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
239 dst_buf->b->field = V4L2_FIELD_NONE;
240 else
241 dst_buf->b->field = V4L2_FIELD_INTERLACED;
242 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
243
244 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
245 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
246 }
247 }
248
249 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
250 {
251 struct s5p_mfc_dev *dev = ctx->dev;
252 struct s5p_mfc_buf *dst_buf, *src_buf;
253 u32 dec_y_addr;
254 unsigned int frame_type;
255
256 /* Make sure we actually have a new frame before continuing. */
257 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
258 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
259 return;
260 dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
261
262 /* Copy timestamp / timecode from decoded src to dst and set
263 appropriate flags. */
264 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
265 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
266 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
267
268 if (addr == dec_y_addr) {
269 dst_buf->b->timecode = src_buf->b->timecode;
270 dst_buf->b->vb2_buf.timestamp =
271 src_buf->b->vb2_buf.timestamp;
272 dst_buf->b->flags &=
273 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
274 dst_buf->b->flags |=
275 src_buf->b->flags
276 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
277 switch (frame_type) {
278 case S5P_FIMV_DECODE_FRAME_I_FRAME:
279 dst_buf->b->flags |=
280 V4L2_BUF_FLAG_KEYFRAME;
281 break;
282 case S5P_FIMV_DECODE_FRAME_P_FRAME:
283 dst_buf->b->flags |=
284 V4L2_BUF_FLAG_PFRAME;
285 break;
286 case S5P_FIMV_DECODE_FRAME_B_FRAME:
287 dst_buf->b->flags |=
288 V4L2_BUF_FLAG_BFRAME;
289 break;
290 default:
291 /* Don't know how to handle
292 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
293 mfc_debug(2, "Unexpected frame type: %d\n",
294 frame_type);
295 }
296 break;
297 }
298 }
299 }
300
301 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
302 {
303 struct s5p_mfc_dev *dev = ctx->dev;
304 struct s5p_mfc_buf *dst_buf;
305 u32 dspl_y_addr;
306 unsigned int frame_type;
307
308 dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
309 if (IS_MFCV6_PLUS(dev))
310 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
311 get_disp_frame_type, ctx);
312 else
313 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
314 get_dec_frame_type, dev);
315
316 /* If frame is same as previous then skip and do not dequeue */
317 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
318 if (!ctx->after_packed_pb)
319 ctx->sequence++;
320 ctx->after_packed_pb = 0;
321 return;
322 }
323 ctx->sequence++;
324 /* The MFC returns address of the buffer, now we have to
325 * check which videobuf does it correspond to */
326 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
327 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
328
329 /* Check if this is the buffer we're looking for */
330 if (addr == dspl_y_addr) {
331 list_del(&dst_buf->list);
332 ctx->dst_queue_cnt--;
333 dst_buf->b->sequence = ctx->sequence;
334 if (s5p_mfc_hw_call(dev->mfc_ops,
335 get_pic_type_top, ctx) ==
336 s5p_mfc_hw_call(dev->mfc_ops,
337 get_pic_type_bot, ctx))
338 dst_buf->b->field = V4L2_FIELD_NONE;
339 else
340 dst_buf->b->field =
341 V4L2_FIELD_INTERLACED;
342 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
343 ctx->luma_size);
344 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
345 ctx->chroma_size);
346 clear_bit(dst_buf->b->vb2_buf.index,
347 &ctx->dec_dst_flag);
348
349 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
350 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
351
352 break;
353 }
354 }
355 }
356
357 /* Handle frame decoding interrupt */
358 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
359 unsigned int reason, unsigned int err)
360 {
361 struct s5p_mfc_dev *dev = ctx->dev;
362 unsigned int dst_frame_status;
363 unsigned int dec_frame_status;
364 struct s5p_mfc_buf *src_buf;
365 unsigned int res_change;
366
367 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
368 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
369 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
370 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
371 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
372 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
373 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
374 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
375 if (ctx->state == MFCINST_RES_CHANGE_INIT)
376 ctx->state = MFCINST_RES_CHANGE_FLUSH;
377 if (res_change == S5P_FIMV_RES_INCREASE ||
378 res_change == S5P_FIMV_RES_DECREASE) {
379 ctx->state = MFCINST_RES_CHANGE_INIT;
380 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
381 wake_up_ctx(ctx, reason, err);
382 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
383 s5p_mfc_clock_off();
384 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
385 return;
386 }
387 if (ctx->dpb_flush_flag)
388 ctx->dpb_flush_flag = 0;
389
390 /* All frames remaining in the buffer have been extracted */
391 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
392 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
393 static const struct v4l2_event ev_src_ch = {
394 .type = V4L2_EVENT_SOURCE_CHANGE,
395 .u.src_change.changes =
396 V4L2_EVENT_SRC_CH_RESOLUTION,
397 };
398
399 s5p_mfc_handle_frame_all_extracted(ctx);
400 ctx->state = MFCINST_RES_CHANGE_END;
401 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
402
403 goto leave_handle_frame;
404 } else {
405 s5p_mfc_handle_frame_all_extracted(ctx);
406 }
407 }
408
409 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
410 s5p_mfc_handle_frame_copy_time(ctx);
411
412 /* A frame has been decoded and is in the buffer */
413 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
414 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
415 s5p_mfc_handle_frame_new(ctx, err);
416 } else {
417 mfc_debug(2, "No frame decode\n");
418 }
419 /* Mark source buffer as complete */
420 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
421 && !list_empty(&ctx->src_queue)) {
422 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
423 list);
424 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
425 get_consumed_stream, dev);
426 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
427 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
428 ctx->consumed_stream + STUFF_BYTE <
429 src_buf->b->vb2_buf.planes[0].bytesused) {
430 /* Run MFC again on the same buffer */
431 mfc_debug(2, "Running again the same buffer\n");
432 ctx->after_packed_pb = 1;
433 } else {
434 mfc_debug(2, "MFC needs next buffer\n");
435 ctx->consumed_stream = 0;
436 if (src_buf->flags & MFC_BUF_FLAG_EOS)
437 ctx->state = MFCINST_FINISHING;
438 list_del(&src_buf->list);
439 ctx->src_queue_cnt--;
440 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
441 vb2_buffer_done(&src_buf->b->vb2_buf,
442 VB2_BUF_STATE_ERROR);
443 else
444 vb2_buffer_done(&src_buf->b->vb2_buf,
445 VB2_BUF_STATE_DONE);
446 }
447 }
448 leave_handle_frame:
449 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
450 || ctx->dst_queue_cnt < ctx->pb_count)
451 clear_work_bit(ctx);
452 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
453 wake_up_ctx(ctx, reason, err);
454 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
455 s5p_mfc_clock_off();
456 /* if suspending, wake up device and do not try_run again*/
457 if (test_bit(0, &dev->enter_suspend))
458 wake_up_dev(dev, reason, err);
459 else
460 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
461 }
462
463 /* Error handling for interrupt */
464 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
465 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
466 {
467 mfc_err("Interrupt Error: %08x\n", err);
468
469 if (ctx != NULL) {
470 /* Error recovery is dependent on the state of context */
471 switch (ctx->state) {
472 case MFCINST_RES_CHANGE_INIT:
473 case MFCINST_RES_CHANGE_FLUSH:
474 case MFCINST_RES_CHANGE_END:
475 case MFCINST_FINISHING:
476 case MFCINST_FINISHED:
477 case MFCINST_RUNNING:
478 /* It is highly probable that an error occurred
479 * while decoding a frame */
480 clear_work_bit(ctx);
481 ctx->state = MFCINST_ERROR;
482 /* Mark all dst buffers as having an error */
483 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
484 /* Mark all src buffers as having an error */
485 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
486 wake_up_ctx(ctx, reason, err);
487 break;
488 default:
489 clear_work_bit(ctx);
490 ctx->state = MFCINST_ERROR;
491 wake_up_ctx(ctx, reason, err);
492 break;
493 }
494 }
495 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
496 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
497 s5p_mfc_clock_off();
498 wake_up_dev(dev, reason, err);
499 }
500
501 /* Header parsing interrupt handling */
502 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
503 unsigned int reason, unsigned int err)
504 {
505 struct s5p_mfc_dev *dev;
506
507 if (ctx == NULL)
508 return;
509 dev = ctx->dev;
510 if (ctx->c_ops->post_seq_start) {
511 if (ctx->c_ops->post_seq_start(ctx))
512 mfc_err("post_seq_start() failed\n");
513 } else {
514 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
515 dev);
516 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
517 dev);
518
519 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
520
521 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
522 dev);
523 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
524 dev);
525 if (ctx->img_width == 0 || ctx->img_height == 0)
526 ctx->state = MFCINST_ERROR;
527 else
528 ctx->state = MFCINST_HEAD_PARSED;
529
530 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
531 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
532 !list_empty(&ctx->src_queue)) {
533 struct s5p_mfc_buf *src_buf;
534 src_buf = list_entry(ctx->src_queue.next,
535 struct s5p_mfc_buf, list);
536 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
537 dev) <
538 src_buf->b->vb2_buf.planes[0].bytesused)
539 ctx->head_processed = 0;
540 else
541 ctx->head_processed = 1;
542 } else {
543 ctx->head_processed = 1;
544 }
545 }
546 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
547 clear_work_bit(ctx);
548 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
549 s5p_mfc_clock_off();
550 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
551 wake_up_ctx(ctx, reason, err);
552 }
553
554 /* Header parsing interrupt handling */
555 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
556 unsigned int reason, unsigned int err)
557 {
558 struct s5p_mfc_buf *src_buf;
559 struct s5p_mfc_dev *dev;
560
561 if (ctx == NULL)
562 return;
563 dev = ctx->dev;
564 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
565 ctx->int_type = reason;
566 ctx->int_err = err;
567 ctx->int_cond = 1;
568 clear_work_bit(ctx);
569 if (err == 0) {
570 ctx->state = MFCINST_RUNNING;
571 if (!ctx->dpb_flush_flag && ctx->head_processed) {
572 if (!list_empty(&ctx->src_queue)) {
573 src_buf = list_entry(ctx->src_queue.next,
574 struct s5p_mfc_buf, list);
575 list_del(&src_buf->list);
576 ctx->src_queue_cnt--;
577 vb2_buffer_done(&src_buf->b->vb2_buf,
578 VB2_BUF_STATE_DONE);
579 }
580 } else {
581 ctx->dpb_flush_flag = 0;
582 }
583 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
584
585 s5p_mfc_clock_off();
586
587 wake_up(&ctx->queue);
588 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
589 } else {
590 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
591
592 s5p_mfc_clock_off();
593
594 wake_up(&ctx->queue);
595 }
596 }
597
598 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
599 {
600 struct s5p_mfc_dev *dev = ctx->dev;
601 struct s5p_mfc_buf *mb_entry;
602
603 mfc_debug(2, "Stream completed\n");
604
605 ctx->state = MFCINST_FINISHED;
606
607 if (!list_empty(&ctx->dst_queue)) {
608 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
609 list);
610 list_del(&mb_entry->list);
611 ctx->dst_queue_cnt--;
612 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
613 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
614 }
615
616 clear_work_bit(ctx);
617
618 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
619
620 s5p_mfc_clock_off();
621 wake_up(&ctx->queue);
622 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
623 }
624
625 /* Interrupt processing */
626 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
627 {
628 struct s5p_mfc_dev *dev = priv;
629 struct s5p_mfc_ctx *ctx;
630 unsigned int reason;
631 unsigned int err;
632
633 mfc_debug_enter();
634 /* Reset the timeout watchdog */
635 atomic_set(&dev->watchdog_cnt, 0);
636 spin_lock(&dev->irqlock);
637 ctx = dev->ctx[dev->curr_ctx];
638 /* Get the reason of interrupt and the error code */
639 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
640 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
641 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
642 switch (reason) {
643 case S5P_MFC_R2H_CMD_ERR_RET:
644 /* An error has occurred */
645 if (ctx->state == MFCINST_RUNNING &&
646 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
647 dev->warn_start)
648 s5p_mfc_handle_frame(ctx, reason, err);
649 else
650 s5p_mfc_handle_error(dev, ctx, reason, err);
651 clear_bit(0, &dev->enter_suspend);
652 break;
653
654 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
655 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
656 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
657 if (ctx->c_ops->post_frame_start) {
658 if (ctx->c_ops->post_frame_start(ctx))
659 mfc_err("post_frame_start() failed\n");
660
661 if (ctx->state == MFCINST_FINISHING &&
662 list_empty(&ctx->ref_queue)) {
663 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
664 s5p_mfc_handle_stream_complete(ctx);
665 break;
666 }
667 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
668 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
669 s5p_mfc_clock_off();
670 wake_up_ctx(ctx, reason, err);
671 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
672 } else {
673 s5p_mfc_handle_frame(ctx, reason, err);
674 }
675 break;
676
677 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
678 s5p_mfc_handle_seq_done(ctx, reason, err);
679 break;
680
681 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
682 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
683 ctx->state = MFCINST_GOT_INST;
684 goto irq_cleanup_hw;
685
686 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
687 ctx->inst_no = MFC_NO_INSTANCE_SET;
688 ctx->state = MFCINST_FREE;
689 goto irq_cleanup_hw;
690
691 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
692 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
693 case S5P_MFC_R2H_CMD_SLEEP_RET:
694 case S5P_MFC_R2H_CMD_WAKEUP_RET:
695 if (ctx)
696 clear_work_bit(ctx);
697 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
698 clear_bit(0, &dev->hw_lock);
699 clear_bit(0, &dev->enter_suspend);
700 wake_up_dev(dev, reason, err);
701 break;
702
703 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
704 s5p_mfc_handle_init_buffers(ctx, reason, err);
705 break;
706
707 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
708 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
709 ctx->int_type = reason;
710 ctx->int_err = err;
711 s5p_mfc_handle_stream_complete(ctx);
712 break;
713
714 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
715 ctx->state = MFCINST_RUNNING;
716 goto irq_cleanup_hw;
717
718 default:
719 mfc_debug(2, "Unknown int reason\n");
720 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
721 }
722 spin_unlock(&dev->irqlock);
723 mfc_debug_leave();
724 return IRQ_HANDLED;
725 irq_cleanup_hw:
726 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
727 ctx->int_type = reason;
728 ctx->int_err = err;
729 ctx->int_cond = 1;
730 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
731 mfc_err("Failed to unlock hw\n");
732
733 s5p_mfc_clock_off();
734 clear_work_bit(ctx);
735 wake_up(&ctx->queue);
736
737 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
738 spin_unlock(&dev->irqlock);
739 mfc_debug(2, "Exit via irq_cleanup_hw\n");
740 return IRQ_HANDLED;
741 }
742
743 /* Open an MFC node */
744 static int s5p_mfc_open(struct file *file)
745 {
746 struct video_device *vdev = video_devdata(file);
747 struct s5p_mfc_dev *dev = video_drvdata(file);
748 struct s5p_mfc_ctx *ctx = NULL;
749 struct vb2_queue *q;
750 int ret = 0;
751
752 mfc_debug_enter();
753 if (mutex_lock_interruptible(&dev->mfc_mutex))
754 return -ERESTARTSYS;
755 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
756 /* Allocate memory for context */
757 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
758 if (!ctx) {
759 ret = -ENOMEM;
760 goto err_alloc;
761 }
762 v4l2_fh_init(&ctx->fh, vdev);
763 file->private_data = &ctx->fh;
764 v4l2_fh_add(&ctx->fh);
765 ctx->dev = dev;
766 INIT_LIST_HEAD(&ctx->src_queue);
767 INIT_LIST_HEAD(&ctx->dst_queue);
768 ctx->src_queue_cnt = 0;
769 ctx->dst_queue_cnt = 0;
770 /* Get context number */
771 ctx->num = 0;
772 while (dev->ctx[ctx->num]) {
773 ctx->num++;
774 if (ctx->num >= MFC_NUM_CONTEXTS) {
775 mfc_debug(2, "Too many open contexts\n");
776 ret = -EBUSY;
777 goto err_no_ctx;
778 }
779 }
780 /* Mark context as idle */
781 clear_work_bit_irqsave(ctx);
782 dev->ctx[ctx->num] = ctx;
783 if (vdev == dev->vfd_dec) {
784 ctx->type = MFCINST_DECODER;
785 ctx->c_ops = get_dec_codec_ops();
786 s5p_mfc_dec_init(ctx);
787 /* Setup ctrl handler */
788 ret = s5p_mfc_dec_ctrls_setup(ctx);
789 if (ret) {
790 mfc_err("Failed to setup mfc controls\n");
791 goto err_ctrls_setup;
792 }
793 } else if (vdev == dev->vfd_enc) {
794 ctx->type = MFCINST_ENCODER;
795 ctx->c_ops = get_enc_codec_ops();
796 /* only for encoder */
797 INIT_LIST_HEAD(&ctx->ref_queue);
798 ctx->ref_queue_cnt = 0;
799 s5p_mfc_enc_init(ctx);
800 /* Setup ctrl handler */
801 ret = s5p_mfc_enc_ctrls_setup(ctx);
802 if (ret) {
803 mfc_err("Failed to setup mfc controls\n");
804 goto err_ctrls_setup;
805 }
806 } else {
807 ret = -ENOENT;
808 goto err_bad_node;
809 }
810 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
811 ctx->inst_no = MFC_NO_INSTANCE_SET;
812 /* Load firmware if this is the first instance */
813 if (dev->num_inst == 1) {
814 dev->watchdog_timer.expires = jiffies +
815 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
816 add_timer(&dev->watchdog_timer);
817 ret = s5p_mfc_power_on();
818 if (ret < 0) {
819 mfc_err("power on failed\n");
820 goto err_pwr_enable;
821 }
822 s5p_mfc_clock_on();
823 ret = s5p_mfc_load_firmware(dev);
824 if (ret) {
825 s5p_mfc_clock_off();
826 goto err_load_fw;
827 }
828 /* Init the FW */
829 ret = s5p_mfc_init_hw(dev);
830 s5p_mfc_clock_off();
831 if (ret)
832 goto err_init_hw;
833 }
834 /* Init videobuf2 queue for CAPTURE */
835 q = &ctx->vq_dst;
836 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
837 q->drv_priv = &ctx->fh;
838 q->lock = &dev->mfc_mutex;
839 if (vdev == dev->vfd_dec) {
840 q->io_modes = VB2_MMAP;
841 q->ops = get_dec_queue_ops();
842 } else if (vdev == dev->vfd_enc) {
843 q->io_modes = VB2_MMAP | VB2_USERPTR;
844 q->ops = get_enc_queue_ops();
845 } else {
846 ret = -ENOENT;
847 goto err_queue_init;
848 }
849 q->mem_ops = &vb2_dma_contig_memops;
850 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
851 ret = vb2_queue_init(q);
852 if (ret) {
853 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
854 goto err_queue_init;
855 }
856 /* Init videobuf2 queue for OUTPUT */
857 q = &ctx->vq_src;
858 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
859 q->io_modes = VB2_MMAP;
860 q->drv_priv = &ctx->fh;
861 q->lock = &dev->mfc_mutex;
862 if (vdev == dev->vfd_dec) {
863 q->io_modes = VB2_MMAP;
864 q->ops = get_dec_queue_ops();
865 } else if (vdev == dev->vfd_enc) {
866 q->io_modes = VB2_MMAP | VB2_USERPTR;
867 q->ops = get_enc_queue_ops();
868 } else {
869 ret = -ENOENT;
870 goto err_queue_init;
871 }
872 /* One way to indicate end-of-stream for MFC is to set the
873 * bytesused == 0. However by default videobuf2 handles bytesused
874 * equal to 0 as a special case and changes its value to the size
875 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
876 * will keep the value of bytesused intact.
877 */
878 q->allow_zero_bytesused = 1;
879 q->mem_ops = &vb2_dma_contig_memops;
880 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
881 ret = vb2_queue_init(q);
882 if (ret) {
883 mfc_err("Failed to initialize videobuf2 queue(output)\n");
884 goto err_queue_init;
885 }
886 init_waitqueue_head(&ctx->queue);
887 mutex_unlock(&dev->mfc_mutex);
888 mfc_debug_leave();
889 return ret;
890 /* Deinit when failure occurred */
891 err_queue_init:
892 if (dev->num_inst == 1)
893 s5p_mfc_deinit_hw(dev);
894 err_init_hw:
895 err_load_fw:
896 err_pwr_enable:
897 if (dev->num_inst == 1) {
898 if (s5p_mfc_power_off() < 0)
899 mfc_err("power off failed\n");
900 del_timer_sync(&dev->watchdog_timer);
901 }
902 err_ctrls_setup:
903 s5p_mfc_dec_ctrls_delete(ctx);
904 err_bad_node:
905 dev->ctx[ctx->num] = NULL;
906 err_no_ctx:
907 v4l2_fh_del(&ctx->fh);
908 v4l2_fh_exit(&ctx->fh);
909 kfree(ctx);
910 err_alloc:
911 dev->num_inst--;
912 mutex_unlock(&dev->mfc_mutex);
913 mfc_debug_leave();
914 return ret;
915 }
916
917 /* Release MFC context */
918 static int s5p_mfc_release(struct file *file)
919 {
920 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
921 struct s5p_mfc_dev *dev = ctx->dev;
922
923 /* if dev is null, do cleanup that doesn't need dev */
924 mfc_debug_enter();
925 if (dev)
926 mutex_lock(&dev->mfc_mutex);
927 vb2_queue_release(&ctx->vq_src);
928 vb2_queue_release(&ctx->vq_dst);
929 if (dev) {
930 s5p_mfc_clock_on();
931
932 /* Mark context as idle */
933 clear_work_bit_irqsave(ctx);
934 /*
935 * If instance was initialised and not yet freed,
936 * return instance and free resources
937 */
938 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
939 mfc_debug(2, "Has to free instance\n");
940 s5p_mfc_close_mfc_inst(dev, ctx);
941 }
942 /* hardware locking scheme */
943 if (dev->curr_ctx == ctx->num)
944 clear_bit(0, &dev->hw_lock);
945 dev->num_inst--;
946 if (dev->num_inst == 0) {
947 mfc_debug(2, "Last instance\n");
948 s5p_mfc_deinit_hw(dev);
949 del_timer_sync(&dev->watchdog_timer);
950 if (s5p_mfc_power_off() < 0)
951 mfc_err("Power off failed\n");
952 }
953 mfc_debug(2, "Shutting down clock\n");
954 s5p_mfc_clock_off();
955 }
956 if (dev)
957 dev->ctx[ctx->num] = NULL;
958 s5p_mfc_dec_ctrls_delete(ctx);
959 v4l2_fh_del(&ctx->fh);
960 /* vdev is gone if dev is null */
961 if (dev)
962 v4l2_fh_exit(&ctx->fh);
963 kfree(ctx);
964 mfc_debug_leave();
965 if (dev)
966 mutex_unlock(&dev->mfc_mutex);
967
968 return 0;
969 }
970
971 /* Poll */
972 static unsigned int s5p_mfc_poll(struct file *file,
973 struct poll_table_struct *wait)
974 {
975 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
976 struct s5p_mfc_dev *dev = ctx->dev;
977 struct vb2_queue *src_q, *dst_q;
978 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
979 unsigned int rc = 0;
980 unsigned long flags;
981
982 mutex_lock(&dev->mfc_mutex);
983 src_q = &ctx->vq_src;
984 dst_q = &ctx->vq_dst;
985 /*
986 * There has to be at least one buffer queued on each queued_list, which
987 * means either in driver already or waiting for driver to claim it
988 * and start processing.
989 */
990 if ((!src_q->streaming || list_empty(&src_q->queued_list))
991 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
992 rc = POLLERR;
993 goto end;
994 }
995 mutex_unlock(&dev->mfc_mutex);
996 poll_wait(file, &ctx->fh.wait, wait);
997 poll_wait(file, &src_q->done_wq, wait);
998 poll_wait(file, &dst_q->done_wq, wait);
999 mutex_lock(&dev->mfc_mutex);
1000 if (v4l2_event_pending(&ctx->fh))
1001 rc |= POLLPRI;
1002 spin_lock_irqsave(&src_q->done_lock, flags);
1003 if (!list_empty(&src_q->done_list))
1004 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1005 done_entry);
1006 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1007 || src_vb->state == VB2_BUF_STATE_ERROR))
1008 rc |= POLLOUT | POLLWRNORM;
1009 spin_unlock_irqrestore(&src_q->done_lock, flags);
1010 spin_lock_irqsave(&dst_q->done_lock, flags);
1011 if (!list_empty(&dst_q->done_list))
1012 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1013 done_entry);
1014 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1015 || dst_vb->state == VB2_BUF_STATE_ERROR))
1016 rc |= POLLIN | POLLRDNORM;
1017 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1018 end:
1019 mutex_unlock(&dev->mfc_mutex);
1020 return rc;
1021 }
1022
1023 /* Mmap */
1024 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1025 {
1026 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1027 struct s5p_mfc_dev *dev = ctx->dev;
1028 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1029 int ret;
1030
1031 if (mutex_lock_interruptible(&dev->mfc_mutex))
1032 return -ERESTARTSYS;
1033 if (offset < DST_QUEUE_OFF_BASE) {
1034 mfc_debug(2, "mmaping source\n");
1035 ret = vb2_mmap(&ctx->vq_src, vma);
1036 } else { /* capture */
1037 mfc_debug(2, "mmaping destination\n");
1038 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1039 ret = vb2_mmap(&ctx->vq_dst, vma);
1040 }
1041 mutex_unlock(&dev->mfc_mutex);
1042 return ret;
1043 }
1044
1045 /* v4l2 ops */
1046 static const struct v4l2_file_operations s5p_mfc_fops = {
1047 .owner = THIS_MODULE,
1048 .open = s5p_mfc_open,
1049 .release = s5p_mfc_release,
1050 .poll = s5p_mfc_poll,
1051 .unlocked_ioctl = video_ioctl2,
1052 .mmap = s5p_mfc_mmap,
1053 };
1054
1055 /* DMA memory related helper functions */
1056 static void s5p_mfc_memdev_release(struct device *dev)
1057 {
1058 of_reserved_mem_device_release(dev);
1059 }
1060
1061 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1062 const char *name, unsigned int idx)
1063 {
1064 struct device *child;
1065 int ret;
1066
1067 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1068 if (!child)
1069 return NULL;
1070
1071 device_initialize(child);
1072 dev_set_name(child, "%s:%s", dev_name(dev), name);
1073 child->parent = dev;
1074 child->bus = dev->bus;
1075 child->coherent_dma_mask = dev->coherent_dma_mask;
1076 child->dma_mask = dev->dma_mask;
1077 child->release = s5p_mfc_memdev_release;
1078
1079 if (device_add(child) == 0) {
1080 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1081 idx);
1082 if (ret == 0)
1083 return child;
1084 device_del(child);
1085 }
1086
1087 put_device(child);
1088 return NULL;
1089 }
1090
1091 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1092 {
1093 struct device *dev = &mfc_dev->plat_dev->dev;
1094
1095 /*
1096 * When IOMMU is available, we cannot use the default configuration,
1097 * because of MFC firmware requirements: address space limited to
1098 * 256M and non-zero default start address.
1099 * This is still simplified, not optimal configuration, but for now
1100 * IOMMU core doesn't allow to configure device's IOMMUs channel
1101 * separately.
1102 */
1103 if (exynos_is_iommu_available(dev)) {
1104 int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1105 S5P_MFC_IOMMU_DMA_SIZE);
1106 if (ret == 0)
1107 mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1108 return ret;
1109 }
1110
1111 /*
1112 * Create and initialize virtual devices for accessing
1113 * reserved memory regions.
1114 */
1115 mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1116 MFC_BANK1_ALLOC_CTX);
1117 if (!mfc_dev->mem_dev_l)
1118 return -ENODEV;
1119 mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1120 MFC_BANK2_ALLOC_CTX);
1121 if (!mfc_dev->mem_dev_r) {
1122 device_unregister(mfc_dev->mem_dev_l);
1123 return -ENODEV;
1124 }
1125
1126 return 0;
1127 }
1128
1129 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1130 {
1131 struct device *dev = &mfc_dev->plat_dev->dev;
1132
1133 if (exynos_is_iommu_available(dev)) {
1134 exynos_unconfigure_iommu(dev);
1135 return;
1136 }
1137
1138 device_unregister(mfc_dev->mem_dev_l);
1139 device_unregister(mfc_dev->mem_dev_r);
1140 }
1141
1142 static void *mfc_get_drv_data(struct platform_device *pdev);
1143
1144 /* MFC probe function */
1145 static int s5p_mfc_probe(struct platform_device *pdev)
1146 {
1147 struct s5p_mfc_dev *dev;
1148 struct video_device *vfd;
1149 struct resource *res;
1150 int ret;
1151
1152 pr_debug("%s++\n", __func__);
1153 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1154 if (!dev) {
1155 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1156 return -ENOMEM;
1157 }
1158
1159 spin_lock_init(&dev->irqlock);
1160 spin_lock_init(&dev->condlock);
1161 dev->plat_dev = pdev;
1162 if (!dev->plat_dev) {
1163 dev_err(&pdev->dev, "No platform data specified\n");
1164 return -ENODEV;
1165 }
1166
1167 dev->variant = mfc_get_drv_data(pdev);
1168
1169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1170 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1171 if (IS_ERR(dev->regs_base))
1172 return PTR_ERR(dev->regs_base);
1173
1174 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1175 if (res == NULL) {
1176 dev_err(&pdev->dev, "failed to get irq resource\n");
1177 return -ENOENT;
1178 }
1179 dev->irq = res->start;
1180 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1181 0, pdev->name, dev);
1182 if (ret) {
1183 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1184 return ret;
1185 }
1186
1187 ret = s5p_mfc_configure_dma_memory(dev);
1188 if (ret < 0) {
1189 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1190 return ret;
1191 }
1192
1193 ret = s5p_mfc_init_pm(dev);
1194 if (ret < 0) {
1195 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1196 goto err_dma;
1197 }
1198
1199 vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1200 vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1201
1202 mutex_init(&dev->mfc_mutex);
1203
1204 ret = s5p_mfc_alloc_firmware(dev);
1205 if (ret)
1206 goto err_res;
1207
1208 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1209 if (ret)
1210 goto err_v4l2_dev_reg;
1211 init_waitqueue_head(&dev->queue);
1212
1213 /* decoder */
1214 vfd = video_device_alloc();
1215 if (!vfd) {
1216 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1217 ret = -ENOMEM;
1218 goto err_dec_alloc;
1219 }
1220 vfd->fops = &s5p_mfc_fops;
1221 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1222 vfd->release = video_device_release;
1223 vfd->lock = &dev->mfc_mutex;
1224 vfd->v4l2_dev = &dev->v4l2_dev;
1225 vfd->vfl_dir = VFL_DIR_M2M;
1226 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1227 dev->vfd_dec = vfd;
1228 video_set_drvdata(vfd, dev);
1229
1230 /* encoder */
1231 vfd = video_device_alloc();
1232 if (!vfd) {
1233 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1234 ret = -ENOMEM;
1235 goto err_enc_alloc;
1236 }
1237 vfd->fops = &s5p_mfc_fops;
1238 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1239 vfd->release = video_device_release;
1240 vfd->lock = &dev->mfc_mutex;
1241 vfd->v4l2_dev = &dev->v4l2_dev;
1242 vfd->vfl_dir = VFL_DIR_M2M;
1243 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1244 dev->vfd_enc = vfd;
1245 video_set_drvdata(vfd, dev);
1246 platform_set_drvdata(pdev, dev);
1247
1248 dev->hw_lock = 0;
1249 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1250 atomic_set(&dev->watchdog_cnt, 0);
1251 init_timer(&dev->watchdog_timer);
1252 dev->watchdog_timer.data = (unsigned long)dev;
1253 dev->watchdog_timer.function = s5p_mfc_watchdog;
1254
1255 /* Initialize HW ops and commands based on MFC version */
1256 s5p_mfc_init_hw_ops(dev);
1257 s5p_mfc_init_hw_cmds(dev);
1258 s5p_mfc_init_regs(dev);
1259
1260 /* Register decoder and encoder */
1261 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1262 if (ret) {
1263 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1264 goto err_dec_reg;
1265 }
1266 v4l2_info(&dev->v4l2_dev,
1267 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1268
1269 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1270 if (ret) {
1271 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1272 goto err_enc_reg;
1273 }
1274 v4l2_info(&dev->v4l2_dev,
1275 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1276
1277 pr_debug("%s--\n", __func__);
1278 return 0;
1279
1280 /* Deinit MFC if probe had failed */
1281 err_enc_reg:
1282 video_unregister_device(dev->vfd_dec);
1283 err_dec_reg:
1284 video_device_release(dev->vfd_enc);
1285 err_enc_alloc:
1286 video_device_release(dev->vfd_dec);
1287 err_dec_alloc:
1288 v4l2_device_unregister(&dev->v4l2_dev);
1289 err_v4l2_dev_reg:
1290 s5p_mfc_release_firmware(dev);
1291 err_res:
1292 s5p_mfc_final_pm(dev);
1293 err_dma:
1294 s5p_mfc_unconfigure_dma_memory(dev);
1295
1296 pr_debug("%s-- with error\n", __func__);
1297 return ret;
1298
1299 }
1300
1301 /* Remove the driver */
1302 static int s5p_mfc_remove(struct platform_device *pdev)
1303 {
1304 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1305 struct s5p_mfc_ctx *ctx;
1306 int i;
1307
1308 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1309
1310 /*
1311 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1312 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1313 * after s5p_mfc_remove() is run during unbind.
1314 */
1315 mutex_lock(&dev->mfc_mutex);
1316 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1317 ctx = dev->ctx[i];
1318 if (!ctx)
1319 continue;
1320 /* clear ctx->dev */
1321 ctx->dev = NULL;
1322 }
1323 mutex_unlock(&dev->mfc_mutex);
1324
1325 del_timer_sync(&dev->watchdog_timer);
1326 flush_work(&dev->watchdog_work);
1327
1328 video_unregister_device(dev->vfd_enc);
1329 video_unregister_device(dev->vfd_dec);
1330 video_device_release(dev->vfd_enc);
1331 video_device_release(dev->vfd_dec);
1332 v4l2_device_unregister(&dev->v4l2_dev);
1333 s5p_mfc_release_firmware(dev);
1334 s5p_mfc_unconfigure_dma_memory(dev);
1335 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1336 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1337
1338 s5p_mfc_final_pm(dev);
1339 return 0;
1340 }
1341
1342 #ifdef CONFIG_PM_SLEEP
1343
1344 static int s5p_mfc_suspend(struct device *dev)
1345 {
1346 struct platform_device *pdev = to_platform_device(dev);
1347 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1348 int ret;
1349
1350 if (m_dev->num_inst == 0)
1351 return 0;
1352
1353 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1354 mfc_err("Error: going to suspend for a second time\n");
1355 return -EIO;
1356 }
1357
1358 /* Check if we're processing then wait if it necessary. */
1359 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1360 /* Try and lock the HW */
1361 /* Wait on the interrupt waitqueue */
1362 ret = wait_event_interruptible_timeout(m_dev->queue,
1363 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1364 if (ret == 0) {
1365 mfc_err("Waiting for hardware to finish timed out\n");
1366 clear_bit(0, &m_dev->enter_suspend);
1367 return -EIO;
1368 }
1369 }
1370
1371 ret = s5p_mfc_sleep(m_dev);
1372 if (ret) {
1373 clear_bit(0, &m_dev->enter_suspend);
1374 clear_bit(0, &m_dev->hw_lock);
1375 }
1376 return ret;
1377 }
1378
1379 static int s5p_mfc_resume(struct device *dev)
1380 {
1381 struct platform_device *pdev = to_platform_device(dev);
1382 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1383
1384 if (m_dev->num_inst == 0)
1385 return 0;
1386 return s5p_mfc_wakeup(m_dev);
1387 }
1388 #endif
1389
1390 #ifdef CONFIG_PM
1391 static int s5p_mfc_runtime_suspend(struct device *dev)
1392 {
1393 struct platform_device *pdev = to_platform_device(dev);
1394 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1395
1396 atomic_set(&m_dev->pm.power, 0);
1397 return 0;
1398 }
1399
1400 static int s5p_mfc_runtime_resume(struct device *dev)
1401 {
1402 struct platform_device *pdev = to_platform_device(dev);
1403 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1404
1405 atomic_set(&m_dev->pm.power, 1);
1406 return 0;
1407 }
1408 #endif
1409
1410 /* Power management */
1411 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1412 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1413 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1414 NULL)
1415 };
1416
1417 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1418 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1419 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1420 .dsc = DESC_BUF_SIZE,
1421 .shm = SHARED_BUF_SIZE,
1422 };
1423
1424 static struct s5p_mfc_buf_size buf_size_v5 = {
1425 .fw = MAX_FW_SIZE,
1426 .cpb = MAX_CPB_SIZE,
1427 .priv = &mfc_buf_size_v5,
1428 };
1429
1430 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1431 .base = MFC_BASE_ALIGN_ORDER,
1432 };
1433
1434 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1435 .version = MFC_VERSION,
1436 .version_bit = MFC_V5_BIT,
1437 .port_num = MFC_NUM_PORTS,
1438 .buf_size = &buf_size_v5,
1439 .buf_align = &mfc_buf_align_v5,
1440 .fw_name[0] = "s5p-mfc.fw",
1441 };
1442
1443 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1444 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1445 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1446 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1447 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1448 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1449 };
1450
1451 static struct s5p_mfc_buf_size buf_size_v6 = {
1452 .fw = MAX_FW_SIZE_V6,
1453 .cpb = MAX_CPB_SIZE_V6,
1454 .priv = &mfc_buf_size_v6,
1455 };
1456
1457 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1458 .base = 0,
1459 };
1460
1461 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1462 .version = MFC_VERSION_V6,
1463 .version_bit = MFC_V6_BIT,
1464 .port_num = MFC_NUM_PORTS_V6,
1465 .buf_size = &buf_size_v6,
1466 .buf_align = &mfc_buf_align_v6,
1467 .fw_name[0] = "s5p-mfc-v6.fw",
1468 /*
1469 * v6-v2 firmware contains bug fixes and interface change
1470 * for init buffer command
1471 */
1472 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1473 };
1474
1475 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1476 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1477 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1478 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1479 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1480 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1481 };
1482
1483 static struct s5p_mfc_buf_size buf_size_v7 = {
1484 .fw = MAX_FW_SIZE_V7,
1485 .cpb = MAX_CPB_SIZE_V7,
1486 .priv = &mfc_buf_size_v7,
1487 };
1488
1489 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1490 .base = 0,
1491 };
1492
1493 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1494 .version = MFC_VERSION_V7,
1495 .version_bit = MFC_V7_BIT,
1496 .port_num = MFC_NUM_PORTS_V7,
1497 .buf_size = &buf_size_v7,
1498 .buf_align = &mfc_buf_align_v7,
1499 .fw_name[0] = "s5p-mfc-v7.fw",
1500 };
1501
1502 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1503 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1504 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1505 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1506 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1507 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1508 };
1509
1510 static struct s5p_mfc_buf_size buf_size_v8 = {
1511 .fw = MAX_FW_SIZE_V8,
1512 .cpb = MAX_CPB_SIZE_V8,
1513 .priv = &mfc_buf_size_v8,
1514 };
1515
1516 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1517 .base = 0,
1518 };
1519
1520 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1521 .version = MFC_VERSION_V8,
1522 .version_bit = MFC_V8_BIT,
1523 .port_num = MFC_NUM_PORTS_V8,
1524 .buf_size = &buf_size_v8,
1525 .buf_align = &mfc_buf_align_v8,
1526 .fw_name[0] = "s5p-mfc-v8.fw",
1527 };
1528
1529 static const struct of_device_id exynos_mfc_match[] = {
1530 {
1531 .compatible = "samsung,mfc-v5",
1532 .data = &mfc_drvdata_v5,
1533 }, {
1534 .compatible = "samsung,mfc-v6",
1535 .data = &mfc_drvdata_v6,
1536 }, {
1537 .compatible = "samsung,mfc-v7",
1538 .data = &mfc_drvdata_v7,
1539 }, {
1540 .compatible = "samsung,mfc-v8",
1541 .data = &mfc_drvdata_v8,
1542 },
1543 {},
1544 };
1545 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1546
1547 static void *mfc_get_drv_data(struct platform_device *pdev)
1548 {
1549 struct s5p_mfc_variant *driver_data = NULL;
1550 const struct of_device_id *match;
1551
1552 match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1553 if (match)
1554 driver_data = (struct s5p_mfc_variant *)match->data;
1555
1556 return driver_data;
1557 }
1558
1559 static struct platform_driver s5p_mfc_driver = {
1560 .probe = s5p_mfc_probe,
1561 .remove = s5p_mfc_remove,
1562 .driver = {
1563 .name = S5P_MFC_NAME,
1564 .pm = &s5p_mfc_pm_ops,
1565 .of_match_table = exynos_mfc_match,
1566 },
1567 };
1568
1569 module_platform_driver(s5p_mfc_driver);
1570
1571 MODULE_LICENSE("GPL");
1572 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1573 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1574
Linux with added FPC-III support