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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v5.c
blob81e1e4ce6c2452dd76a24d4490a60257f4059e26
1 /*
2 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Kamil Debski, Copyright (c) 2011 Samsung Electronics
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include "s5p_mfc_common.h"
16 #include "s5p_mfc_cmd.h"
17 #include "s5p_mfc_ctrl.h"
18 #include "s5p_mfc_debug.h"
19 #include "s5p_mfc_intr.h"
20 #include "s5p_mfc_pm.h"
21 #include "s5p_mfc_opr.h"
22 #include "s5p_mfc_opr_v5.h"
23 #include <asm/cacheflush.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/firmware.h>
28 #include <linux/io.h>
29 #include <linux/jiffies.h>
30 #include <linux/mm.h>
31 #include <linux/sched.h>
32
33 #define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT)
34 #define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT)
35
36 /* Allocate temporary buffers for decoding */
37 static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx)
38 {
39 struct s5p_mfc_dev *dev = ctx->dev;
40 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
41 int ret;
42
43 ctx->dsc.size = buf_size->dsc;
44 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->dsc);
45 if (ret) {
46 mfc_err("Failed to allocate temporary buffer\n");
47 return ret;
48 }
49
50 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
51 memset(ctx->dsc.virt, 0, ctx->dsc.size);
52 wmb();
53 return 0;
54 }
55
56
57 /* Release temporary buffers for decoding */
58 static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx)
59 {
60 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc);
61 }
62
63 /* Allocate codec buffers */
64 static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx)
65 {
66 struct s5p_mfc_dev *dev = ctx->dev;
67 unsigned int enc_ref_y_size = 0;
68 unsigned int enc_ref_c_size = 0;
69 unsigned int guard_width, guard_height;
70 int ret;
71
72 if (ctx->type == MFCINST_DECODER) {
73 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
74 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
76 } else if (ctx->type == MFCINST_ENCODER) {
77 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
78 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
79 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
80
81 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) {
82 enc_ref_c_size = ALIGN(ctx->img_width,
83 S5P_FIMV_NV12MT_HALIGN)
84 * ALIGN(ctx->img_height >> 1,
85 S5P_FIMV_NV12MT_VALIGN);
86 enc_ref_c_size = ALIGN(enc_ref_c_size,
87 S5P_FIMV_NV12MT_SALIGN);
88 } else {
89 guard_width = ALIGN(ctx->img_width + 16,
90 S5P_FIMV_NV12MT_HALIGN);
91 guard_height = ALIGN((ctx->img_height >> 1) + 4,
92 S5P_FIMV_NV12MT_VALIGN);
93 enc_ref_c_size = ALIGN(guard_width * guard_height,
94 S5P_FIMV_NV12MT_SALIGN);
95 }
96 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
97 enc_ref_y_size, enc_ref_c_size);
98 } else {
99 return -EINVAL;
100 }
101 /* Codecs have different memory requirements */
102 switch (ctx->codec_mode) {
103 case S5P_MFC_CODEC_H264_DEC:
104 ctx->bank1.size =
105 ALIGN(S5P_FIMV_DEC_NB_IP_SIZE +
106 S5P_FIMV_DEC_VERT_NB_MV_SIZE,
107 S5P_FIMV_DEC_BUF_ALIGN);
108 ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size;
109 break;
110 case S5P_MFC_CODEC_MPEG4_DEC:
111 ctx->bank1.size =
112 ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE +
113 S5P_FIMV_DEC_UPNB_MV_SIZE +
114 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
115 S5P_FIMV_DEC_STX_PARSER_SIZE +
116 S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE,
117 S5P_FIMV_DEC_BUF_ALIGN);
118 ctx->bank2.size = 0;
119 break;
120 case S5P_MFC_CODEC_VC1RCV_DEC:
121 case S5P_MFC_CODEC_VC1_DEC:
122 ctx->bank1.size =
123 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
124 S5P_FIMV_DEC_UPNB_MV_SIZE +
125 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
126 S5P_FIMV_DEC_NB_DCAC_SIZE +
127 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE,
128 S5P_FIMV_DEC_BUF_ALIGN);
129 ctx->bank2.size = 0;
130 break;
131 case S5P_MFC_CODEC_MPEG2_DEC:
132 ctx->bank1.size = 0;
133 ctx->bank2.size = 0;
134 break;
135 case S5P_MFC_CODEC_H263_DEC:
136 ctx->bank1.size =
137 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
138 S5P_FIMV_DEC_UPNB_MV_SIZE +
139 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
140 S5P_FIMV_DEC_NB_DCAC_SIZE,
141 S5P_FIMV_DEC_BUF_ALIGN);
142 ctx->bank2.size = 0;
143 break;
144 case S5P_MFC_CODEC_H264_ENC:
145 ctx->bank1.size = (enc_ref_y_size * 2) +
146 S5P_FIMV_ENC_UPMV_SIZE +
147 S5P_FIMV_ENC_COLFLG_SIZE +
148 S5P_FIMV_ENC_INTRAMD_SIZE +
149 S5P_FIMV_ENC_NBORINFO_SIZE;
150 ctx->bank2.size = (enc_ref_y_size * 2) +
151 (enc_ref_c_size * 4) +
152 S5P_FIMV_ENC_INTRAPRED_SIZE;
153 break;
154 case S5P_MFC_CODEC_MPEG4_ENC:
155 ctx->bank1.size = (enc_ref_y_size * 2) +
156 S5P_FIMV_ENC_UPMV_SIZE +
157 S5P_FIMV_ENC_COLFLG_SIZE +
158 S5P_FIMV_ENC_ACDCCOEF_SIZE;
159 ctx->bank2.size = (enc_ref_y_size * 2) +
160 (enc_ref_c_size * 4);
161 break;
162 case S5P_MFC_CODEC_H263_ENC:
163 ctx->bank1.size = (enc_ref_y_size * 2) +
164 S5P_FIMV_ENC_UPMV_SIZE +
165 S5P_FIMV_ENC_ACDCCOEF_SIZE;
166 ctx->bank2.size = (enc_ref_y_size * 2) +
167 (enc_ref_c_size * 4);
168 break;
169 default:
170 break;
171 }
172 /* Allocate only if memory from bank 1 is necessary */
173 if (ctx->bank1.size > 0) {
174
175 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1,
176 &ctx->bank1);
177 if (ret) {
178 mfc_err("Failed to allocate Bank1 temporary buffer\n");
179 return ret;
180 }
181 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
182 }
183 /* Allocate only if memory from bank 2 is necessary */
184 if (ctx->bank2.size > 0) {
185 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, dev->bank2,
186 &ctx->bank2);
187 if (ret) {
188 mfc_err("Failed to allocate Bank2 temporary buffer\n");
189 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
190 return ret;
191 }
192 BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1));
193 }
194 return 0;
195 }
196
197 /* Release buffers allocated for codec */
198 static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx)
199 {
200 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
201 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2);
202 }
203
204 /* Allocate memory for instance data buffer */
205 static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
206 {
207 struct s5p_mfc_dev *dev = ctx->dev;
208 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
209 int ret;
210
211 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
212 ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
213 ctx->ctx.size = buf_size->h264_ctx;
214 else
215 ctx->ctx.size = buf_size->non_h264_ctx;
216
217 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->ctx);
218 if (ret) {
219 mfc_err("Failed to allocate instance buffer\n");
220 return ret;
221 }
222 ctx->ctx.ofs = OFFSETA(ctx->ctx.dma);
223
224 /* Zero content of the allocated memory */
225 memset(ctx->ctx.virt, 0, ctx->ctx.size);
226 wmb();
227
228 /* Initialize shared memory */
229 ctx->shm.size = buf_size->shm;
230 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->shm);
231 if (ret) {
232 mfc_err("Failed to allocate shared memory buffer\n");
233 s5p_mfc_release_priv_buf(dev->mem_dev_l, &ctx->ctx);
234 return ret;
235 }
236
237 /* shared memory offset only keeps the offset from base (port a) */
238 ctx->shm.ofs = ctx->shm.dma - dev->bank1;
239 BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
240
241 memset(ctx->shm.virt, 0, buf_size->shm);
242 wmb();
243 return 0;
244 }
245
246 /* Release instance buffer */
247 static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
248 {
249 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
250 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm);
251 }
252
253 static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev)
254 {
255 /* NOP */
256
257 return 0;
258 }
259
260 static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev)
261 {
262 /* NOP */
263 }
264
265 static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data,
266 unsigned int ofs)
267 {
268 *(u32 *)(ctx->shm.virt + ofs) = data;
269 wmb();
270 }
271
272 static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx,
273 unsigned long ofs)
274 {
275 rmb();
276 return *(u32 *)(ctx->shm.virt + ofs);
277 }
278
279 static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx)
280 {
281 unsigned int guard_width, guard_height;
282
283 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
284 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
285 mfc_debug(2,
286 "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n",
287 ctx->img_width, ctx->img_height, ctx->buf_width,
288 ctx->buf_height);
289
290 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) {
291 ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height,
292 S5P_FIMV_DEC_BUF_ALIGN);
293 ctx->chroma_size = ALIGN(ctx->buf_width *
294 ALIGN((ctx->img_height >> 1),
295 S5P_FIMV_NV12MT_VALIGN),
296 S5P_FIMV_DEC_BUF_ALIGN);
297 ctx->mv_size = ALIGN(ctx->buf_width *
298 ALIGN((ctx->buf_height >> 2),
299 S5P_FIMV_NV12MT_VALIGN),
300 S5P_FIMV_DEC_BUF_ALIGN);
301 } else {
302 guard_width =
303 ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN);
304 guard_height =
305 ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN);
306 ctx->luma_size = ALIGN(guard_width * guard_height,
307 S5P_FIMV_DEC_BUF_ALIGN);
308
309 guard_width =
310 ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
311 guard_height =
312 ALIGN((ctx->img_height >> 1) + 4,
313 S5P_FIMV_NV12MT_VALIGN);
314 ctx->chroma_size = ALIGN(guard_width * guard_height,
315 S5P_FIMV_DEC_BUF_ALIGN);
316
317 ctx->mv_size = 0;
318 }
319 }
320
321 static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx)
322 {
323 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
324 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN);
325
326 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
327 * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN);
328 ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
329 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN);
330
331 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN);
332 ctx->chroma_size =
333 ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN);
334 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
335 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
336
337 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
338 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
339 ctx->chroma_size =
340 ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
341 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
342
343 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN);
344 ctx->chroma_size =
345 ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN);
346 }
347 }
348
349 /* Set registers for decoding temporary buffers */
350 static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
351 {
352 struct s5p_mfc_dev *dev = ctx->dev;
353 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
354
355 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);
356 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);
357 }
358
359 /* Set registers for shared buffer */
360 static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx)
361 {
362 struct s5p_mfc_dev *dev = ctx->dev;
363 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
364 }
365
366 /* Set registers for decoding stream buffer */
367 static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx,
368 int buf_addr, unsigned int start_num_byte,
369 unsigned int buf_size)
370 {
371 struct s5p_mfc_dev *dev = ctx->dev;
372
373 mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
374 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
375 mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
376 s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM);
377 return 0;
378 }
379
380 /* Set decoding frame buffer */
381 static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx)
382 {
383 unsigned int frame_size_lu, i;
384 unsigned int frame_size_ch, frame_size_mv;
385 struct s5p_mfc_dev *dev = ctx->dev;
386 unsigned int dpb;
387 size_t buf_addr1, buf_addr2;
388 int buf_size1, buf_size2;
389
390 buf_addr1 = ctx->bank1.dma;
391 buf_size1 = ctx->bank1.size;
392 buf_addr2 = ctx->bank2.dma;
393 buf_size2 = ctx->bank2.size;
394 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
395 ~S5P_FIMV_DPB_COUNT_MASK;
396 mfc_write(dev, ctx->total_dpb_count | dpb,
397 S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
398 s5p_mfc_set_shared_buffer(ctx);
399 switch (ctx->codec_mode) {
400 case S5P_MFC_CODEC_H264_DEC:
401 mfc_write(dev, OFFSETA(buf_addr1),
402 S5P_FIMV_H264_VERT_NB_MV_ADR);
403 buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE;
404 buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE;
405 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR);
406 buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE;
407 buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE;
408 break;
409 case S5P_MFC_CODEC_MPEG4_DEC:
410 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR);
411 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
412 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
413 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR);
414 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
415 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
416 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR);
417 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
418 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
419 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR);
420 buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE;
421 buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE;
422 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR);
423 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
424 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
425 break;
426 case S5P_MFC_CODEC_H263_DEC:
427 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR);
428 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
429 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
430 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR);
431 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
432 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
433 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR);
434 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
435 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
436 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR);
437 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
438 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
439 break;
440 case S5P_MFC_CODEC_VC1_DEC:
441 case S5P_MFC_CODEC_VC1RCV_DEC:
442 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR);
443 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
444 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
445 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR);
446 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
447 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
448 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR);
449 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
450 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
451 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR);
452 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
453 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
454 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR);
455 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
456 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
457 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR);
458 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
459 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
460 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR);
461 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
462 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
463 break;
464 case S5P_MFC_CODEC_MPEG2_DEC:
465 break;
466 default:
467 mfc_err("Unknown codec for decoding (%x)\n",
468 ctx->codec_mode);
469 return -EINVAL;
470 }
471 frame_size_lu = ctx->luma_size;
472 frame_size_ch = ctx->chroma_size;
473 frame_size_mv = ctx->mv_size;
474 mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size_lu, frame_size_ch,
475 frame_size_mv);
476 for (i = 0; i < ctx->total_dpb_count; i++) {
477 /* Bank2 */
478 mfc_debug(2, "Luma %d: %zx\n", i,
479 ctx->dst_bufs[i].cookie.raw.luma);
480 mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma),
481 S5P_FIMV_DEC_LUMA_ADR + i * 4);
482 mfc_debug(2, "\tChroma %d: %zx\n", i,
483 ctx->dst_bufs[i].cookie.raw.chroma);
484 mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma),
485 S5P_FIMV_DEC_CHROMA_ADR + i * 4);
486 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) {
487 mfc_debug(2, "\tBuf2: %zx, size: %d\n",
488 buf_addr2, buf_size2);
489 mfc_write(dev, OFFSETB(buf_addr2),
490 S5P_FIMV_H264_MV_ADR + i * 4);
491 buf_addr2 += frame_size_mv;
492 buf_size2 -= frame_size_mv;
493 }
494 }
495 mfc_debug(2, "Buf1: %zu, buf_size1: %d\n", buf_addr1, buf_size1);
496 mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n",
497 buf_size1, buf_size2, ctx->total_dpb_count);
498 if (buf_size1 < 0 || buf_size2 < 0) {
499 mfc_debug(2, "Not enough memory has been allocated\n");
500 return -ENOMEM;
501 }
502 s5p_mfc_write_info_v5(ctx, frame_size_lu, ALLOC_LUMA_DPB_SIZE);
503 s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
504 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC)
505 s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE);
506 mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK)
507 << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
508 S5P_FIMV_SI_CH0_INST_ID);
509 return 0;
510 }
511
512 /* Set registers for encoding stream buffer */
513 static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx,
514 unsigned long addr, unsigned int size)
515 {
516 struct s5p_mfc_dev *dev = ctx->dev;
517
518 mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR);
519 mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE);
520 return 0;
521 }
522
523 static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
524 unsigned long y_addr, unsigned long c_addr)
525 {
526 struct s5p_mfc_dev *dev = ctx->dev;
527
528 mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR);
529 mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR);
530 }
531
532 static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
533 unsigned long *y_addr, unsigned long *c_addr)
534 {
535 struct s5p_mfc_dev *dev = ctx->dev;
536
537 *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR)
538 << MFC_OFFSET_SHIFT);
539 *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR)
540 << MFC_OFFSET_SHIFT);
541 }
542
543 /* Set encoding ref & codec buffer */
544 static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx)
545 {
546 struct s5p_mfc_dev *dev = ctx->dev;
547 size_t buf_addr1, buf_addr2;
548 size_t buf_size1, buf_size2;
549 unsigned int enc_ref_y_size, enc_ref_c_size;
550 unsigned int guard_width, guard_height;
551 int i;
552
553 buf_addr1 = ctx->bank1.dma;
554 buf_size1 = ctx->bank1.size;
555 buf_addr2 = ctx->bank2.dma;
556 buf_size2 = ctx->bank2.size;
557 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
558 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
559 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
560 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) {
561 enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
562 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
563 enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN);
564 } else {
565 guard_width = ALIGN(ctx->img_width + 16,
566 S5P_FIMV_NV12MT_HALIGN);
567 guard_height = ALIGN((ctx->img_height >> 1) + 4,
568 S5P_FIMV_NV12MT_VALIGN);
569 enc_ref_c_size = ALIGN(guard_width * guard_height,
570 S5P_FIMV_NV12MT_SALIGN);
571 }
572 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2);
573 switch (ctx->codec_mode) {
574 case S5P_MFC_CODEC_H264_ENC:
575 for (i = 0; i < 2; i++) {
576 mfc_write(dev, OFFSETA(buf_addr1),
577 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
578 buf_addr1 += enc_ref_y_size;
579 buf_size1 -= enc_ref_y_size;
580
581 mfc_write(dev, OFFSETB(buf_addr2),
582 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
583 buf_addr2 += enc_ref_y_size;
584 buf_size2 -= enc_ref_y_size;
585 }
586 for (i = 0; i < 4; i++) {
587 mfc_write(dev, OFFSETB(buf_addr2),
588 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
589 buf_addr2 += enc_ref_c_size;
590 buf_size2 -= enc_ref_c_size;
591 }
592 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR);
593 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
594 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
595 mfc_write(dev, OFFSETA(buf_addr1),
596 S5P_FIMV_H264_COZERO_FLAG_ADR);
597 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
598 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
599 mfc_write(dev, OFFSETA(buf_addr1),
600 S5P_FIMV_H264_UP_INTRA_MD_ADR);
601 buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE;
602 buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE;
603 mfc_write(dev, OFFSETB(buf_addr2),
604 S5P_FIMV_H264_UP_INTRA_PRED_ADR);
605 buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE;
606 buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE;
607 mfc_write(dev, OFFSETA(buf_addr1),
608 S5P_FIMV_H264_NBOR_INFO_ADR);
609 buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE;
610 buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE;
611 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n",
612 buf_size1, buf_size2);
613 break;
614 case S5P_MFC_CODEC_MPEG4_ENC:
615 for (i = 0; i < 2; i++) {
616 mfc_write(dev, OFFSETA(buf_addr1),
617 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
618 buf_addr1 += enc_ref_y_size;
619 buf_size1 -= enc_ref_y_size;
620 mfc_write(dev, OFFSETB(buf_addr2),
621 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
622 buf_addr2 += enc_ref_y_size;
623 buf_size2 -= enc_ref_y_size;
624 }
625 for (i = 0; i < 4; i++) {
626 mfc_write(dev, OFFSETB(buf_addr2),
627 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
628 buf_addr2 += enc_ref_c_size;
629 buf_size2 -= enc_ref_c_size;
630 }
631 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR);
632 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
633 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
634 mfc_write(dev, OFFSETA(buf_addr1),
635 S5P_FIMV_MPEG4_COZERO_FLAG_ADR);
636 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
637 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
638 mfc_write(dev, OFFSETA(buf_addr1),
639 S5P_FIMV_MPEG4_ACDC_COEF_ADR);
640 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
641 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
642 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n",
643 buf_size1, buf_size2);
644 break;
645 case S5P_MFC_CODEC_H263_ENC:
646 for (i = 0; i < 2; i++) {
647 mfc_write(dev, OFFSETA(buf_addr1),
648 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
649 buf_addr1 += enc_ref_y_size;
650 buf_size1 -= enc_ref_y_size;
651 mfc_write(dev, OFFSETB(buf_addr2),
652 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
653 buf_addr2 += enc_ref_y_size;
654 buf_size2 -= enc_ref_y_size;
655 }
656 for (i = 0; i < 4; i++) {
657 mfc_write(dev, OFFSETB(buf_addr2),
658 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
659 buf_addr2 += enc_ref_c_size;
660 buf_size2 -= enc_ref_c_size;
661 }
662 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR);
663 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
664 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
665 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR);
666 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
667 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
668 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n",
669 buf_size1, buf_size2);
670 break;
671 default:
672 mfc_err("Unknown codec set for encoding: %d\n",
673 ctx->codec_mode);
674 return -EINVAL;
675 }
676 return 0;
677 }
678
679 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
680 {
681 struct s5p_mfc_dev *dev = ctx->dev;
682 struct s5p_mfc_enc_params *p = &ctx->enc_params;
683 unsigned int reg;
684 unsigned int shm;
685
686 /* width */
687 mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX);
688 /* height */
689 mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX);
690 /* pictype : enable, IDR period */
691 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
692 reg |= (1 << 18);
693 reg &= ~(0xFFFF);
694 reg |= p->gop_size;
695 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
696 mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON);
697 /* multi-slice control */
698 /* multi-slice MB number or bit size */
699 mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL);
700 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
701 mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB);
702 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
703 mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT);
704 } else {
705 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB);
706 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT);
707 }
708 /* cyclic intra refresh */
709 mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL);
710 /* memory structure cur. frame */
711 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
712 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
713 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
714 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
715 /* padding control & value */
716 reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL);
717 if (p->pad) {
718 /** enable */
719 reg |= (1 << 31);
720 /** cr value */
721 reg &= ~(0xFF << 16);
722 reg |= (p->pad_cr << 16);
723 /** cb value */
724 reg &= ~(0xFF << 8);
725 reg |= (p->pad_cb << 8);
726 /** y value */
727 reg &= ~(0xFF);
728 reg |= (p->pad_luma);
729 } else {
730 /** disable & all value clear */
731 reg = 0;
732 }
733 mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL);
734 /* rate control config. */
735 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
736 /** frame-level rate control */
737 reg &= ~(0x1 << 9);
738 reg |= (p->rc_frame << 9);
739 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
740 /* bit rate */
741 if (p->rc_frame)
742 mfc_write(dev, p->rc_bitrate,
743 S5P_FIMV_ENC_RC_BIT_RATE);
744 else
745 mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE);
746 /* reaction coefficient */
747 if (p->rc_frame)
748 mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA);
749 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
750 /* seq header ctrl */
751 shm &= ~(0x1 << 3);
752 shm |= (p->seq_hdr_mode << 3);
753 /* frame skip mode */
754 shm &= ~(0x3 << 1);
755 shm |= (p->frame_skip_mode << 1);
756 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
757 /* fixed target bit */
758 s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
759 return 0;
760 }
761
762 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
763 {
764 struct s5p_mfc_dev *dev = ctx->dev;
765 struct s5p_mfc_enc_params *p = &ctx->enc_params;
766 struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264;
767 unsigned int reg;
768 unsigned int shm;
769
770 s5p_mfc_set_enc_params(ctx);
771 /* pictype : number of B */
772 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
773 /* num_b_frame - 0 ~ 2 */
774 reg &= ~(0x3 << 16);
775 reg |= (p->num_b_frame << 16);
776 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
777 /* profile & level */
778 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
779 /* level */
780 reg &= ~(0xFF << 8);
781 reg |= (p_264->level << 8);
782 /* profile - 0 ~ 2 */
783 reg &= ~(0x3F);
784 reg |= p_264->profile;
785 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
786 /* interlace */
787 mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT);
788 /* height */
789 if (p_264->interlace)
790 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
791 /* loopfilter ctrl */
792 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL);
793 /* loopfilter alpha offset */
794 if (p_264->loop_filter_alpha < 0) {
795 reg = 0x10;
796 reg |= (0xFF - p_264->loop_filter_alpha) + 1;
797 } else {
798 reg = 0x00;
799 reg |= (p_264->loop_filter_alpha & 0xF);
800 }
801 mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF);
802 /* loopfilter beta offset */
803 if (p_264->loop_filter_beta < 0) {
804 reg = 0x10;
805 reg |= (0xFF - p_264->loop_filter_beta) + 1;
806 } else {
807 reg = 0x00;
808 reg |= (p_264->loop_filter_beta & 0xF);
809 }
810 mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF);
811 /* entropy coding mode */
812 if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC)
813 mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE);
814 else
815 mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE);
816 /* number of ref. picture */
817 reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF);
818 /* num of ref. pictures of P */
819 reg &= ~(0x3 << 5);
820 reg |= (p_264->num_ref_pic_4p << 5);
821 /* max number of ref. pictures */
822 reg &= ~(0x1F);
823 reg |= p_264->max_ref_pic;
824 mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF);
825 /* 8x8 transform enable */
826 mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG);
827 /* rate control config. */
828 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
829 /* macroblock level rate control */
830 reg &= ~(0x1 << 8);
831 reg |= (p->rc_mb << 8);
832 /* frame QP */
833 reg &= ~(0x3F);
834 reg |= p_264->rc_frame_qp;
835 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
836 /* frame rate */
837 if (p->rc_frame && p->rc_framerate_denom)
838 mfc_write(dev, p->rc_framerate_num * 1000
839 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE);
840 else
841 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
842 /* max & min value of QP */
843 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
844 /* max QP */
845 reg &= ~(0x3F << 8);
846 reg |= (p_264->rc_max_qp << 8);
847 /* min QP */
848 reg &= ~(0x3F);
849 reg |= p_264->rc_min_qp;
850 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
851 /* macroblock adaptive scaling features */
852 if (p->rc_mb) {
853 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL);
854 /* dark region */
855 reg &= ~(0x1 << 3);
856 reg |= (p_264->rc_mb_dark << 3);
857 /* smooth region */
858 reg &= ~(0x1 << 2);
859 reg |= (p_264->rc_mb_smooth << 2);
860 /* static region */
861 reg &= ~(0x1 << 1);
862 reg |= (p_264->rc_mb_static << 1);
863 /* high activity region */
864 reg &= ~(0x1);
865 reg |= p_264->rc_mb_activity;
866 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL);
867 }
868 if (!p->rc_frame && !p->rc_mb) {
869 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
870 shm &= ~(0xFFF);
871 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6);
872 shm |= (p_264->rc_p_frame_qp & 0x3F);
873 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
874 }
875 /* extended encoder ctrl */
876 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
877 /* AR VUI control */
878 shm &= ~(0x1 << 15);
879 shm |= (p_264->vui_sar << 1);
880 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
881 if (p_264->vui_sar) {
882 /* aspect ration IDC */
883 shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC);
884 shm &= ~(0xFF);
885 shm |= p_264->vui_sar_idc;
886 s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC);
887 if (p_264->vui_sar_idc == 0xFF) {
888 /* sample AR info */
889 shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR);
890 shm &= ~(0xFFFFFFFF);
891 shm |= p_264->vui_ext_sar_width << 16;
892 shm |= p_264->vui_ext_sar_height;
893 s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR);
894 }
895 }
896 /* intra picture period for H.264 */
897 shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD);
898 /* control */
899 shm &= ~(0x1 << 16);
900 shm |= (p_264->open_gop << 16);
901 /* value */
902 if (p_264->open_gop) {
903 shm &= ~(0xFFFF);
904 shm |= p_264->open_gop_size;
905 }
906 s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD);
907 /* extended encoder ctrl */
908 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
909 /* vbv buffer size */
910 if (p->frame_skip_mode ==
911 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
912 shm &= ~(0xFFFF << 16);
913 shm |= (p_264->cpb_size << 16);
914 }
915 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
916 return 0;
917 }
918
919 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
920 {
921 struct s5p_mfc_dev *dev = ctx->dev;
922 struct s5p_mfc_enc_params *p = &ctx->enc_params;
923 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
924 unsigned int reg;
925 unsigned int shm;
926 unsigned int framerate;
927
928 s5p_mfc_set_enc_params(ctx);
929 /* pictype : number of B */
930 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
931 /* num_b_frame - 0 ~ 2 */
932 reg &= ~(0x3 << 16);
933 reg |= (p->num_b_frame << 16);
934 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
935 /* profile & level */
936 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
937 /* level */
938 reg &= ~(0xFF << 8);
939 reg |= (p_mpeg4->level << 8);
940 /* profile - 0 ~ 2 */
941 reg &= ~(0x3F);
942 reg |= p_mpeg4->profile;
943 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
944 /* quarter_pixel */
945 mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL);
946 /* qp */
947 if (!p->rc_frame) {
948 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
949 shm &= ~(0xFFF);
950 shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6);
951 shm |= (p_mpeg4->rc_p_frame_qp & 0x3F);
952 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
953 }
954 /* frame rate */
955 if (p->rc_frame) {
956 if (p->rc_framerate_denom > 0) {
957 framerate = p->rc_framerate_num * 1000 /
958 p->rc_framerate_denom;
959 mfc_write(dev, framerate,
960 S5P_FIMV_ENC_RC_FRAME_RATE);
961 shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING);
962 shm &= ~(0xFFFFFFFF);
963 shm |= (1 << 31);
964 shm |= ((p->rc_framerate_num & 0x7FFF) << 16);
965 shm |= (p->rc_framerate_denom & 0xFFFF);
966 s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING);
967 }
968 } else {
969 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
970 }
971 /* rate control config. */
972 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
973 /* frame QP */
974 reg &= ~(0x3F);
975 reg |= p_mpeg4->rc_frame_qp;
976 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
977 /* max & min value of QP */
978 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
979 /* max QP */
980 reg &= ~(0x3F << 8);
981 reg |= (p_mpeg4->rc_max_qp << 8);
982 /* min QP */
983 reg &= ~(0x3F);
984 reg |= p_mpeg4->rc_min_qp;
985 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
986 /* extended encoder ctrl */
987 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
988 /* vbv buffer size */
989 if (p->frame_skip_mode ==
990 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
991 shm &= ~(0xFFFF << 16);
992 shm |= (p->vbv_size << 16);
993 }
994 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
995 return 0;
996 }
997
998 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
999 {
1000 struct s5p_mfc_dev *dev = ctx->dev;
1001 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1002 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1003 unsigned int reg;
1004 unsigned int shm;
1005
1006 s5p_mfc_set_enc_params(ctx);
1007 /* qp */
1008 if (!p->rc_frame) {
1009 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
1010 shm &= ~(0xFFF);
1011 shm |= (p_h263->rc_p_frame_qp & 0x3F);
1012 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
1013 }
1014 /* frame rate */
1015 if (p->rc_frame && p->rc_framerate_denom)
1016 mfc_write(dev, p->rc_framerate_num * 1000
1017 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE);
1018 else
1019 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
1020 /* rate control config. */
1021 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
1022 /* frame QP */
1023 reg &= ~(0x3F);
1024 reg |= p_h263->rc_frame_qp;
1025 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
1026 /* max & min value of QP */
1027 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
1028 /* max QP */
1029 reg &= ~(0x3F << 8);
1030 reg |= (p_h263->rc_max_qp << 8);
1031 /* min QP */
1032 reg &= ~(0x3F);
1033 reg |= p_h263->rc_min_qp;
1034 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
1035 /* extended encoder ctrl */
1036 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
1037 /* vbv buffer size */
1038 if (p->frame_skip_mode ==
1039 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1040 shm &= ~(0xFFFF << 16);
1041 shm |= (p->vbv_size << 16);
1042 }
1043 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
1044 return 0;
1045 }
1046
1047 /* Initialize decoding */
1048 static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx)
1049 {
1050 struct s5p_mfc_dev *dev = ctx->dev;
1051
1052 s5p_mfc_set_shared_buffer(ctx);
1053 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1054 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC)
1055 mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL);
1056 else
1057 mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL);
1058 mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) <<
1059 S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable <<
1060 S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay &
1061 S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT),
1062 S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
1063 mfc_write(dev,
1064 ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
1065 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1066 return 0;
1067 }
1068
1069 static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1070 {
1071 struct s5p_mfc_dev *dev = ctx->dev;
1072 unsigned int dpb;
1073
1074 if (flush)
1075 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | (
1076 S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT);
1077 else
1078 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
1079 ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT);
1080 mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
1081 }
1082
1083 /* Decode a single frame */
1084 static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx,
1085 enum s5p_mfc_decode_arg last_frame)
1086 {
1087 struct s5p_mfc_dev *dev = ctx->dev;
1088
1089 mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF);
1090 s5p_mfc_set_shared_buffer(ctx);
1091 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1092 /* Issue different commands to instance basing on whether it
1093 * is the last frame or not. */
1094 switch (last_frame) {
1095 case MFC_DEC_FRAME:
1096 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) <<
1097 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1098 break;
1099 case MFC_DEC_LAST_FRAME:
1100 mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) <<
1101 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1102 break;
1103 case MFC_DEC_RES_CHANGE:
1104 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC &
1105 S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
1106 S5P_FIMV_SI_CH0_INST_ID);
1107 break;
1108 }
1109 mfc_debug(2, "Decoding a usual frame\n");
1110 return 0;
1111 }
1112
1113 static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx)
1114 {
1115 struct s5p_mfc_dev *dev = ctx->dev;
1116
1117 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1118 s5p_mfc_set_enc_params_h264(ctx);
1119 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1120 s5p_mfc_set_enc_params_mpeg4(ctx);
1121 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1122 s5p_mfc_set_enc_params_h263(ctx);
1123 else {
1124 mfc_err("Unknown codec for encoding (%x)\n",
1125 ctx->codec_mode);
1126 return -EINVAL;
1127 }
1128 s5p_mfc_set_shared_buffer(ctx);
1129 mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) |
1130 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1131 return 0;
1132 }
1133
1134 /* Encode a single frame */
1135 static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx)
1136 {
1137 struct s5p_mfc_dev *dev = ctx->dev;
1138 int cmd;
1139 /* memory structure cur. frame */
1140 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
1141 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
1142 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
1143 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
1144 s5p_mfc_set_shared_buffer(ctx);
1145
1146 if (ctx->state == MFCINST_FINISHING)
1147 cmd = S5P_FIMV_CH_LAST_FRAME;
1148 else
1149 cmd = S5P_FIMV_CH_FRAME_START;
1150 mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
1151 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1152
1153 return 0;
1154 }
1155
1156 static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx)
1157 {
1158 struct s5p_mfc_dev *dev = ctx->dev;
1159
1160 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0);
1161 dev->curr_ctx = ctx->num;
1162 s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE);
1163 }
1164
1165 static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame)
1166 {
1167 struct s5p_mfc_dev *dev = ctx->dev;
1168 struct s5p_mfc_buf *temp_vb;
1169
1170 if (ctx->state == MFCINST_FINISHING) {
1171 last_frame = MFC_DEC_LAST_FRAME;
1172 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0);
1173 dev->curr_ctx = ctx->num;
1174 s5p_mfc_decode_one_frame_v5(ctx, last_frame);
1175 return 0;
1176 }
1177
1178 /* Frames are being decoded */
1179 if (list_empty(&ctx->src_queue)) {
1180 mfc_debug(2, "No src buffers\n");
1181 return -EAGAIN;
1182 }
1183 /* Get the next source buffer */
1184 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1185 temp_vb->flags |= MFC_BUF_FLAG_USED;
1186 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1187 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1188 ctx->consumed_stream, temp_vb->b->vb2_buf.planes[0].bytesused);
1189 dev->curr_ctx = ctx->num;
1190 if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {
1191 last_frame = MFC_DEC_LAST_FRAME;
1192 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1193 ctx->state = MFCINST_FINISHING;
1194 }
1195 s5p_mfc_decode_one_frame_v5(ctx, last_frame);
1196 return 0;
1197 }
1198
1199 static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1200 {
1201 struct s5p_mfc_dev *dev = ctx->dev;
1202 struct s5p_mfc_buf *dst_mb;
1203 struct s5p_mfc_buf *src_mb;
1204 unsigned long src_y_addr, src_c_addr, dst_addr;
1205 unsigned int dst_size;
1206
1207 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
1208 mfc_debug(2, "no src buffers\n");
1209 return -EAGAIN;
1210 }
1211 if (list_empty(&ctx->dst_queue)) {
1212 mfc_debug(2, "no dst buffers\n");
1213 return -EAGAIN;
1214 }
1215 if (list_empty(&ctx->src_queue)) {
1216 /* send null frame */
1217 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2);
1218 src_mb = NULL;
1219 } else {
1220 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
1221 list);
1222 src_mb->flags |= MFC_BUF_FLAG_USED;
1223 if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
1224 /* send null frame */
1225 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2,
1226 dev->bank2);
1227 ctx->state = MFCINST_FINISHING;
1228 } else {
1229 src_y_addr = vb2_dma_contig_plane_dma_addr(
1230 &src_mb->b->vb2_buf, 0);
1231 src_c_addr = vb2_dma_contig_plane_dma_addr(
1232 &src_mb->b->vb2_buf, 1);
1233 s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr,
1234 src_c_addr);
1235 if (src_mb->flags & MFC_BUF_FLAG_EOS)
1236 ctx->state = MFCINST_FINISHING;
1237 }
1238 }
1239 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1240 dst_mb->flags |= MFC_BUF_FLAG_USED;
1241 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1242 dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1243 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size);
1244 dev->curr_ctx = ctx->num;
1245 mfc_debug(2, "encoding buffer with index=%d state=%d\n",
1246 src_mb ? src_mb->b->vb2_buf.index : -1, ctx->state);
1247 s5p_mfc_encode_one_frame_v5(ctx);
1248 return 0;
1249 }
1250
1251 static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1252 {
1253 struct s5p_mfc_dev *dev = ctx->dev;
1254 struct s5p_mfc_buf *temp_vb;
1255
1256 /* Initializing decoding - parsing header */
1257 mfc_debug(2, "Preparing to init decoding\n");
1258 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1259 s5p_mfc_set_dec_desc_buffer(ctx);
1260 mfc_debug(2, "Header size: %d\n",
1261 temp_vb->b->vb2_buf.planes[0].bytesused);
1262 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1263 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1264 0, temp_vb->b->vb2_buf.planes[0].bytesused);
1265 dev->curr_ctx = ctx->num;
1266 s5p_mfc_init_decode_v5(ctx);
1267 }
1268
1269 static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1270 {
1271 struct s5p_mfc_dev *dev = ctx->dev;
1272 struct s5p_mfc_buf *dst_mb;
1273 unsigned long dst_addr;
1274 unsigned int dst_size;
1275
1276 s5p_mfc_set_enc_ref_buffer_v5(ctx);
1277 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1278 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1279 dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1280 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size);
1281 dev->curr_ctx = ctx->num;
1282 s5p_mfc_init_encode_v5(ctx);
1283 }
1284
1285 static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1286 {
1287 struct s5p_mfc_dev *dev = ctx->dev;
1288 struct s5p_mfc_buf *temp_vb;
1289 int ret;
1290
1291 /*
1292 * Header was parsed now starting processing
1293 * First set the output frame buffers
1294 */
1295 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1296 mfc_err("It seems that not all destionation buffers were "
1297 "mmaped\nMFC requires that all destination are mmaped "
1298 "before starting processing\n");
1299 return -EAGAIN;
1300 }
1301 if (list_empty(&ctx->src_queue)) {
1302 mfc_err("Header has been deallocated in the middle of"
1303 " initialization\n");
1304 return -EIO;
1305 }
1306 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1307 mfc_debug(2, "Header size: %d\n",
1308 temp_vb->b->vb2_buf.planes[0].bytesused);
1309 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1310 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1311 0, temp_vb->b->vb2_buf.planes[0].bytesused);
1312 dev->curr_ctx = ctx->num;
1313 ret = s5p_mfc_set_dec_frame_buffer_v5(ctx);
1314 if (ret) {
1315 mfc_err("Failed to alloc frame mem\n");
1316 ctx->state = MFCINST_ERROR;
1317 }
1318 return ret;
1319 }
1320
1321 /* Try running an operation on hardware */
1322 static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev)
1323 {
1324 struct s5p_mfc_ctx *ctx;
1325 int new_ctx;
1326 unsigned int ret = 0;
1327
1328 if (test_bit(0, &dev->enter_suspend)) {
1329 mfc_debug(1, "Entering suspend so do not schedule any jobs\n");
1330 return;
1331 }
1332 /* Check whether hardware is not running */
1333 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1334 /* This is perfectly ok, the scheduled ctx should wait */
1335 mfc_debug(1, "Couldn't lock HW\n");
1336 return;
1337 }
1338 /* Choose the context to run */
1339 new_ctx = s5p_mfc_get_new_ctx(dev);
1340 if (new_ctx < 0) {
1341 /* No contexts to run */
1342 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1343 mfc_err("Failed to unlock hardware\n");
1344 return;
1345 }
1346 mfc_debug(1, "No ctx is scheduled to be run\n");
1347 return;
1348 }
1349 ctx = dev->ctx[new_ctx];
1350 /* Got context to run in ctx */
1351 /*
1352 * Last frame has already been sent to MFC.
1353 * Now obtaining frames from MFC buffer
1354 */
1355 s5p_mfc_clock_on();
1356 s5p_mfc_clean_ctx_int_flags(ctx);
1357
1358 if (ctx->type == MFCINST_DECODER) {
1359 s5p_mfc_set_dec_desc_buffer(ctx);
1360 switch (ctx->state) {
1361 case MFCINST_FINISHING:
1362 s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME);
1363 break;
1364 case MFCINST_RUNNING:
1365 ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1366 break;
1367 case MFCINST_INIT:
1368 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1369 ctx);
1370 break;
1371 case MFCINST_RETURN_INST:
1372 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1373 ctx);
1374 break;
1375 case MFCINST_GOT_INST:
1376 s5p_mfc_run_init_dec(ctx);
1377 break;
1378 case MFCINST_HEAD_PARSED:
1379 ret = s5p_mfc_run_init_dec_buffers(ctx);
1380 mfc_debug(1, "head parsed\n");
1381 break;
1382 case MFCINST_RES_CHANGE_INIT:
1383 s5p_mfc_run_res_change(ctx);
1384 break;
1385 case MFCINST_RES_CHANGE_FLUSH:
1386 s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1387 break;
1388 case MFCINST_RES_CHANGE_END:
1389 mfc_debug(2, "Finished remaining frames after resolution change\n");
1390 ctx->capture_state = QUEUE_FREE;
1391 mfc_debug(2, "Will re-init the codec\n");
1392 s5p_mfc_run_init_dec(ctx);
1393 break;
1394 default:
1395 ret = -EAGAIN;
1396 }
1397 } else if (ctx->type == MFCINST_ENCODER) {
1398 switch (ctx->state) {
1399 case MFCINST_FINISHING:
1400 case MFCINST_RUNNING:
1401 ret = s5p_mfc_run_enc_frame(ctx);
1402 break;
1403 case MFCINST_INIT:
1404 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1405 ctx);
1406 break;
1407 case MFCINST_RETURN_INST:
1408 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1409 ctx);
1410 break;
1411 case MFCINST_GOT_INST:
1412 s5p_mfc_run_init_enc(ctx);
1413 break;
1414 default:
1415 ret = -EAGAIN;
1416 }
1417 } else {
1418 mfc_err("Invalid context type: %d\n", ctx->type);
1419 ret = -EAGAIN;
1420 }
1421
1422 if (ret) {
1423 /* Free hardware lock */
1424 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1425 mfc_err("Failed to unlock hardware\n");
1426
1427 /* This is in deed imporant, as no operation has been
1428 * scheduled, reduce the clock count as no one will
1429 * ever do this, because no interrupt related to this try_run
1430 * will ever come from hardware. */
1431 s5p_mfc_clock_off();
1432 }
1433 }
1434
1435 static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev)
1436 {
1437 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
1438 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
1439 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
1440 }
1441
1442 static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev)
1443 {
1444 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT;
1445 }
1446
1447 static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev)
1448 {
1449 return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT;
1450 }
1451
1452 static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev)
1453 {
1454 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS);
1455 }
1456
1457 static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev)
1458 {
1459 return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS);
1460 }
1461
1462 static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev)
1463 {
1464 return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) &
1465 S5P_FIMV_DECODE_FRAME_MASK;
1466 }
1467
1468 static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx)
1469 {
1470 return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >>
1471 S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) &
1472 S5P_FIMV_DECODE_FRAME_MASK;
1473 }
1474
1475 static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev)
1476 {
1477 return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES);
1478 }
1479
1480 static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev)
1481 {
1482 int reason;
1483 reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) &
1484 S5P_FIMV_RISC2HOST_CMD_MASK;
1485 switch (reason) {
1486 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET:
1487 reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET;
1488 break;
1489 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET:
1490 reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET;
1491 break;
1492 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET:
1493 reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET;
1494 break;
1495 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET:
1496 reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET;
1497 break;
1498 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET:
1499 reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET;
1500 break;
1501 case S5P_FIMV_R2H_CMD_SYS_INIT_RET:
1502 reason = S5P_MFC_R2H_CMD_SYS_INIT_RET;
1503 break;
1504 case S5P_FIMV_R2H_CMD_FW_STATUS_RET:
1505 reason = S5P_MFC_R2H_CMD_FW_STATUS_RET;
1506 break;
1507 case S5P_FIMV_R2H_CMD_SLEEP_RET:
1508 reason = S5P_MFC_R2H_CMD_SLEEP_RET;
1509 break;
1510 case S5P_FIMV_R2H_CMD_WAKEUP_RET:
1511 reason = S5P_MFC_R2H_CMD_WAKEUP_RET;
1512 break;
1513 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET:
1514 reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET;
1515 break;
1516 case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET:
1517 reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET;
1518 break;
1519 case S5P_FIMV_R2H_CMD_ERR_RET:
1520 reason = S5P_MFC_R2H_CMD_ERR_RET;
1521 break;
1522 default:
1523 reason = S5P_MFC_R2H_CMD_EMPTY;
1524 }
1525 return reason;
1526 }
1527
1528 static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev)
1529 {
1530 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2);
1531 }
1532
1533 static int s5p_mfc_err_dec_v5(unsigned int err)
1534 {
1535 return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT;
1536 }
1537
1538 static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev)
1539 {
1540 return mfc_read(dev, S5P_FIMV_SI_HRESOL);
1541 }
1542
1543 static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev)
1544 {
1545 return mfc_read(dev, S5P_FIMV_SI_VRESOL);
1546 }
1547
1548 static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev)
1549 {
1550 return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER);
1551 }
1552
1553 static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev)
1554 {
1555 /* NOP */
1556 return -1;
1557 }
1558
1559 static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev)
1560 {
1561 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1);
1562 }
1563
1564 static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev)
1565 {
1566 return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE);
1567 }
1568
1569 static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev)
1570 {
1571 return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE);
1572 }
1573
1574 static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev)
1575 {
1576 return -1;
1577 }
1578
1579 static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx)
1580 {
1581 return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP);
1582 }
1583
1584 static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx)
1585 {
1586 return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT);
1587 }
1588
1589 static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx)
1590 {
1591 return s5p_mfc_read_info_v5(ctx, CROP_INFO_H);
1592 }
1593
1594 static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx)
1595 {
1596 return s5p_mfc_read_info_v5(ctx, CROP_INFO_V);
1597 }
1598
1599 /* Initialize opr function pointers for MFC v5 */
1600 static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = {
1601 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5,
1602 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5,
1603 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5,
1604 .release_codec_buffers = s5p_mfc_release_codec_buffers_v5,
1605 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5,
1606 .release_instance_buffer = s5p_mfc_release_instance_buffer_v5,
1607 .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5,
1608 .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5,
1609 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5,
1610 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5,
1611 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5,
1612 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5,
1613 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5,
1614 .try_run = s5p_mfc_try_run_v5,
1615 .clear_int_flags = s5p_mfc_clear_int_flags_v5,
1616 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5,
1617 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5,
1618 .get_dspl_status = s5p_mfc_get_dspl_status_v5,
1619 .get_dec_status = s5p_mfc_get_dec_status_v5,
1620 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5,
1621 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5,
1622 .get_consumed_stream = s5p_mfc_get_consumed_stream_v5,
1623 .get_int_reason = s5p_mfc_get_int_reason_v5,
1624 .get_int_err = s5p_mfc_get_int_err_v5,
1625 .err_dec = s5p_mfc_err_dec_v5,
1626 .get_img_width = s5p_mfc_get_img_width_v5,
1627 .get_img_height = s5p_mfc_get_img_height_v5,
1628 .get_dpb_count = s5p_mfc_get_dpb_count_v5,
1629 .get_mv_count = s5p_mfc_get_mv_count_v5,
1630 .get_inst_no = s5p_mfc_get_inst_no_v5,
1631 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5,
1632 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5,
1633 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5,
1634 .get_pic_type_top = s5p_mfc_get_pic_type_top_v5,
1635 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5,
1636 .get_crop_info_h = s5p_mfc_get_crop_info_h_v5,
1637 .get_crop_info_v = s5p_mfc_get_crop_info_v_v5,
1638 };
1639
1640 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void)
1641 {
1642 return &s5p_mfc_ops_v5;
1643 }
Linux with added FPC-III support