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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / media / rc / nuvoton-cir.c
blob04fedaa7561211a49e235c74ae594a0b1f85da07
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
52 {
53 return nvt->chip_ver == NVT_W83667HG;
54 }
55
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
61 }
62
63 /* read val from config reg */
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
65 {
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
68 }
69
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
72 {
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
75 }
76
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
79 {
80 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
81 nvt_cr_write(nvt, tmp, reg);
82 }
83
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
86 {
87 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
88 return -EBUSY;
89
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE, nvt->cr_efir);
92 outb(EFER_EFM_ENABLE, nvt->cr_efir);
93
94 return 0;
95 }
96
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
99 {
100 outb(EFER_EFM_DISABLE, nvt->cr_efir);
101
102 release_region(nvt->cr_efir, 2);
103 }
104
105 /*
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
109 */
110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 {
112 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
113 }
114
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
117 {
118 nvt_efm_enable(nvt);
119 nvt_select_logical_dev(nvt, ldev);
120 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
121 nvt_efm_disable(nvt);
122 }
123
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
126 {
127 nvt_efm_enable(nvt);
128 nvt_select_logical_dev(nvt, ldev);
129 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
130 nvt_efm_disable(nvt);
131 }
132
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
135 {
136 outb(val, nvt->cir_addr + offset);
137 }
138
139 /* read val from cir config register */
140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
141 {
142 return inb(nvt->cir_addr + offset);
143 }
144
145 /* write val to cir wake register */
146 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
147 u8 val, u8 offset)
148 {
149 outb(val, nvt->cir_wake_addr + offset);
150 }
151
152 /* read val from cir wake config register */
153 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
154 {
155 return inb(nvt->cir_wake_addr + offset);
156 }
157
158 /* don't override io address if one is set already */
159 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
160 {
161 unsigned long old_addr;
162
163 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
164 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
165
166 if (old_addr)
167 *ioaddr = old_addr;
168 else {
169 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
170 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
171 }
172 }
173
174 static ssize_t wakeup_data_show(struct device *dev,
175 struct device_attribute *attr,
176 char *buf)
177 {
178 struct rc_dev *rc_dev = to_rc_dev(dev);
179 struct nvt_dev *nvt = rc_dev->priv;
180 int fifo_len, duration;
181 unsigned long flags;
182 ssize_t buf_len = 0;
183 int i;
184
185 spin_lock_irqsave(&nvt->nvt_lock, flags);
186
187 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
188 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
189
190 /* go to first element to be read */
191 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
193
194 for (i = 0; i < fifo_len; i++) {
195 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
196 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
197 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
198 "%d ", duration);
199 }
200 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
201
202 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
203
204 return buf_len;
205 }
206
207 static ssize_t wakeup_data_store(struct device *dev,
208 struct device_attribute *attr,
209 const char *buf, size_t len)
210 {
211 struct rc_dev *rc_dev = to_rc_dev(dev);
212 struct nvt_dev *nvt = rc_dev->priv;
213 unsigned long flags;
214 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
215 char **argv;
216 int i, count;
217 unsigned int val;
218 ssize_t ret;
219
220 argv = argv_split(GFP_KERNEL, buf, &count);
221 if (!argv)
222 return -ENOMEM;
223 if (!count || count > WAKEUP_MAX_SIZE) {
224 ret = -EINVAL;
225 goto out;
226 }
227
228 for (i = 0; i < count; i++) {
229 ret = kstrtouint(argv[i], 10, &val);
230 if (ret)
231 goto out;
232 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
233 if (!val || val > 0x7f) {
234 ret = -EINVAL;
235 goto out;
236 }
237 wake_buf[i] = val;
238 /* sequence must start with a pulse */
239 if (i % 2 == 0)
240 wake_buf[i] |= BUF_PULSE_BIT;
241 }
242
243 /* hardcode the tolerance to 10% */
244 tolerance = DIV_ROUND_UP(count, 10);
245
246 spin_lock_irqsave(&nvt->nvt_lock, flags);
247
248 nvt_clear_cir_wake_fifo(nvt);
249 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
250 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
251
252 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
253
254 /* enable writes to wake fifo */
255 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
256 CIR_WAKE_IRCON);
257
258 for (i = 0; i < count; i++)
259 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
260
261 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
262
263 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
264
265 ret = len;
266 out:
267 argv_free(argv);
268 return ret;
269 }
270 static DEVICE_ATTR_RW(wakeup_data);
271
272 /* dump current cir register contents */
273 static void cir_dump_regs(struct nvt_dev *nvt)
274 {
275 nvt_efm_enable(nvt);
276 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
277
278 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
279 pr_info(" * CR CIR ACTIVE : 0x%x\n",
280 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
281 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
282 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
283 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
284 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
285 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
286
287 nvt_efm_disable(nvt);
288
289 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
290 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
291 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
292 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
293 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
294 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
295 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
296 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
297 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
298 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
299 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
300 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
301 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
302 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
303 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
304 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
305 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
306 }
307
308 /* dump current cir wake register contents */
309 static void cir_wake_dump_regs(struct nvt_dev *nvt)
310 {
311 u8 i, fifo_len;
312
313 nvt_efm_enable(nvt);
314 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
315
316 pr_info("%s: Dump CIR WAKE logical device registers:\n",
317 NVT_DRIVER_NAME);
318 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
319 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
320 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
321 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
322 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
323 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
324 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
325
326 nvt_efm_disable(nvt);
327
328 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
329 pr_info(" * IRCON: 0x%x\n",
330 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
331 pr_info(" * IRSTS: 0x%x\n",
332 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
333 pr_info(" * IREN: 0x%x\n",
334 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
335 pr_info(" * FIFO CMP DEEP: 0x%x\n",
336 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
337 pr_info(" * FIFO CMP TOL: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
339 pr_info(" * FIFO COUNT: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
341 pr_info(" * SLCH: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
343 pr_info(" * SLCL: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
345 pr_info(" * FIFOCON: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
347 pr_info(" * SRXFSTS: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
349 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
351 pr_info(" * WR FIFO DATA: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
353 pr_info(" * RD FIFO ONLY: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
355 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
357 pr_info(" * FIFO IGNORE: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
359 pr_info(" * IRFSM: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
361
362 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
363 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
364 pr_info("* Contents =");
365 for (i = 0; i < fifo_len; i++)
366 pr_cont(" %02x",
367 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
368 pr_cont("\n");
369 }
370
371 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
372 {
373 int i;
374
375 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
376 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
377 nvt->chip_ver = nvt_chips[i].chip_ver;
378 return nvt_chips[i].name;
379 }
380
381 return NULL;
382 }
383
384
385 /* detect hardware features */
386 static int nvt_hw_detect(struct nvt_dev *nvt)
387 {
388 const char *chip_name;
389 int chip_id;
390
391 nvt_efm_enable(nvt);
392
393 /* Check if we're wired for the alternate EFER setup */
394 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
395 if (nvt->chip_major == 0xff) {
396 nvt_efm_disable(nvt);
397 nvt->cr_efir = CR_EFIR2;
398 nvt->cr_efdr = CR_EFDR2;
399 nvt_efm_enable(nvt);
400 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
401 }
402 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
403
404 nvt_efm_disable(nvt);
405
406 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
407 if (chip_id == NVT_INVALID) {
408 dev_err(&nvt->pdev->dev,
409 "No device found on either EFM port\n");
410 return -ENODEV;
411 }
412
413 chip_name = nvt_find_chip(nvt, chip_id);
414
415 /* warn, but still let the driver load, if we don't know this chip */
416 if (!chip_name)
417 dev_warn(&nvt->pdev->dev,
418 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
419 nvt->chip_major, nvt->chip_minor);
420 else
421 dev_info(&nvt->pdev->dev,
422 "found %s or compatible: chip id: 0x%02x 0x%02x",
423 chip_name, nvt->chip_major, nvt->chip_minor);
424
425 return 0;
426 }
427
428 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
429 {
430 u8 val, psreg, psmask, psval;
431
432 if (is_w83667hg(nvt)) {
433 psreg = CR_MULTIFUNC_PIN_SEL;
434 psmask = MULTIFUNC_PIN_SEL_MASK;
435 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
436 } else {
437 psreg = CR_OUTPUT_PIN_SEL;
438 psmask = OUTPUT_PIN_SEL_MASK;
439 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
440 }
441
442 /* output pin selection: enable CIR, with WB sensor enabled */
443 val = nvt_cr_read(nvt, psreg);
444 val &= psmask;
445 val |= psval;
446 nvt_cr_write(nvt, val, psreg);
447
448 /* Select CIR logical device */
449 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
450
451 nvt_set_ioaddr(nvt, &nvt->cir_addr);
452
453 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
454
455 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
456 nvt->cir_addr, nvt->cir_irq);
457 }
458
459 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
460 {
461 /* Select ACPI logical device and anable it */
462 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
463 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
464
465 /* Enable CIR Wake via PSOUT# (Pin60) */
466 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
467
468 /* enable pme interrupt of cir wakeup event */
469 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
470
471 /* Select CIR Wake logical device */
472 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
473
474 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
475
476 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
477 nvt->cir_wake_addr);
478 }
479
480 /* clear out the hardware's cir rx fifo */
481 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
482 {
483 u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
484 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
485 }
486
487 /* clear out the hardware's cir wake rx fifo */
488 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
489 {
490 u8 val, config;
491
492 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
493
494 /* clearing wake fifo works in learning mode only */
495 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
496 CIR_WAKE_IRCON);
497
498 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
499 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
500 CIR_WAKE_FIFOCON);
501
502 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
503 }
504
505 /* clear out the hardware's cir tx fifo */
506 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
507 {
508 u8 val;
509
510 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
511 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
512 }
513
514 /* enable RX Trigger Level Reach and Packet End interrupts */
515 static void nvt_set_cir_iren(struct nvt_dev *nvt)
516 {
517 u8 iren;
518
519 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
520 nvt_cir_reg_write(nvt, iren, CIR_IREN);
521 }
522
523 static void nvt_cir_regs_init(struct nvt_dev *nvt)
524 {
525 /* set sample limit count (PE interrupt raised when reached) */
526 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
527 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
528
529 /* set fifo irq trigger levels */
530 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
531 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
532
533 /*
534 * Enable TX and RX, specify carrier on = low, off = high, and set
535 * sample period (currently 50us)
536 */
537 nvt_cir_reg_write(nvt,
538 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
539 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
540 CIR_IRCON);
541
542 /* clear hardware rx and tx fifos */
543 nvt_clear_cir_fifo(nvt);
544 nvt_clear_tx_fifo(nvt);
545
546 /* clear any and all stray interrupts */
547 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
548
549 /* and finally, enable interrupts */
550 nvt_set_cir_iren(nvt);
551
552 /* enable the CIR logical device */
553 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
554 }
555
556 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
557 {
558 /*
559 * Disable RX, set specific carrier on = low, off = high,
560 * and sample period (currently 50us)
561 */
562 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
563 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
564 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
565 CIR_WAKE_IRCON);
566
567 /* clear any and all stray interrupts */
568 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
569
570 /* enable the CIR WAKE logical device */
571 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
572 }
573
574 static void nvt_enable_wake(struct nvt_dev *nvt)
575 {
576 unsigned long flags;
577
578 nvt_efm_enable(nvt);
579
580 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
581 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
582 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
583
584 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
585 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
586
587 nvt_efm_disable(nvt);
588
589 spin_lock_irqsave(&nvt->nvt_lock, flags);
590
591 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
592 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
593 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
594 CIR_WAKE_IRCON);
595 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
596 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
597
598 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
599 }
600
601 #if 0 /* Currently unused */
602 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
603 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
604 {
605 u32 count, carrier, duration = 0;
606 int i;
607
608 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
609 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
610
611 for (i = 0; i < nvt->pkts; i++) {
612 if (nvt->buf[i] & BUF_PULSE_BIT)
613 duration += nvt->buf[i] & BUF_LEN_MASK;
614 }
615
616 duration *= SAMPLE_PERIOD;
617
618 if (!count || !duration) {
619 dev_notice(&nvt->pdev->dev,
620 "Unable to determine carrier! (c:%u, d:%u)",
621 count, duration);
622 return 0;
623 }
624
625 carrier = MS_TO_NS(count) / duration;
626
627 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
628 nvt_dbg("WTF? Carrier frequency out of range!");
629
630 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
631 carrier, count, duration);
632
633 return carrier;
634 }
635 #endif
636 /*
637 * set carrier frequency
638 *
639 * set carrier on 2 registers: CP & CC
640 * always set CP as 0x81
641 * set CC by SPEC, CC = 3MHz/carrier - 1
642 */
643 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
644 {
645 struct nvt_dev *nvt = dev->priv;
646 u16 val;
647
648 if (carrier == 0)
649 return -EINVAL;
650
651 nvt_cir_reg_write(nvt, 1, CIR_CP);
652 val = 3000000 / (carrier) - 1;
653 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
654
655 nvt_dbg("cp: 0x%x cc: 0x%x\n",
656 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
657
658 return 0;
659 }
660
661 /*
662 * nvt_tx_ir
663 *
664 * 1) clean TX fifo first (handled by AP)
665 * 2) copy data from user space
666 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
667 * 4) send 9 packets to TX FIFO to open TTR
668 * in interrupt_handler:
669 * 5) send all data out
670 * go back to write():
671 * 6) disable TX interrupts, re-enable RX interupts
672 *
673 * The key problem of this function is user space data may larger than
674 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
675 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
676 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
677 * set TXFCONT as 0xff, until buf_count less than 0xff.
678 */
679 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
680 {
681 struct nvt_dev *nvt = dev->priv;
682 unsigned long flags;
683 unsigned int i;
684 u8 iren;
685 int ret;
686
687 spin_lock_irqsave(&nvt->tx.lock, flags);
688
689 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
690 nvt->tx.buf_count = (ret * sizeof(unsigned));
691
692 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
693
694 nvt->tx.cur_buf_num = 0;
695
696 /* save currently enabled interrupts */
697 iren = nvt_cir_reg_read(nvt, CIR_IREN);
698
699 /* now disable all interrupts, save TFU & TTR */
700 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
701
702 nvt->tx.tx_state = ST_TX_REPLY;
703
704 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
705 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
706
707 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
708 for (i = 0; i < 9; i++)
709 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
710
711 spin_unlock_irqrestore(&nvt->tx.lock, flags);
712
713 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
714
715 spin_lock_irqsave(&nvt->tx.lock, flags);
716 nvt->tx.tx_state = ST_TX_NONE;
717 spin_unlock_irqrestore(&nvt->tx.lock, flags);
718
719 /* restore enabled interrupts to prior state */
720 nvt_cir_reg_write(nvt, iren, CIR_IREN);
721
722 return ret;
723 }
724
725 /* dump contents of the last rx buffer we got from the hw rx fifo */
726 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
727 {
728 int i;
729
730 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
731 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
732 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
733 printk(KERN_CONT "\n");
734 }
735
736 /*
737 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
738 * trigger decode when appropriate.
739 *
740 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
741 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
742 * (default 50us) intervals for that pulse/space. A discrete signal is
743 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
744 * to signal more IR coming (repeats) or end of IR, respectively. We store
745 * sample data in the raw event kfifo until we see 0x7<something> (except f)
746 * or 0x80, at which time, we trigger a decode operation.
747 */
748 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
749 {
750 DEFINE_IR_RAW_EVENT(rawir);
751 u8 sample;
752 int i;
753
754 nvt_dbg_verbose("%s firing", __func__);
755
756 if (debug)
757 nvt_dump_rx_buf(nvt);
758
759 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
760
761 for (i = 0; i < nvt->pkts; i++) {
762 sample = nvt->buf[i];
763
764 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
765 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
766 * SAMPLE_PERIOD);
767
768 nvt_dbg("Storing %s with duration %d",
769 rawir.pulse ? "pulse" : "space", rawir.duration);
770
771 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
772 }
773
774 nvt->pkts = 0;
775
776 nvt_dbg("Calling ir_raw_event_handle\n");
777 ir_raw_event_handle(nvt->rdev);
778
779 nvt_dbg_verbose("%s done", __func__);
780 }
781
782 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
783 {
784 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
785
786 nvt->pkts = 0;
787 nvt_clear_cir_fifo(nvt);
788 ir_raw_event_reset(nvt->rdev);
789 }
790
791 /* copy data from hardware rx fifo into driver buffer */
792 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
793 {
794 u8 fifocount;
795 int i;
796
797 /* Get count of how many bytes to read from RX FIFO */
798 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
799
800 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
801
802 /* Read fifocount bytes from CIR Sample RX FIFO register */
803 for (i = 0; i < fifocount; i++)
804 nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
805
806 nvt->pkts = fifocount;
807 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
808
809 nvt_process_rx_ir_data(nvt);
810 }
811
812 static void nvt_cir_log_irqs(u8 status, u8 iren)
813 {
814 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
815 status, iren,
816 status & CIR_IRSTS_RDR ? " RDR" : "",
817 status & CIR_IRSTS_RTR ? " RTR" : "",
818 status & CIR_IRSTS_PE ? " PE" : "",
819 status & CIR_IRSTS_RFO ? " RFO" : "",
820 status & CIR_IRSTS_TE ? " TE" : "",
821 status & CIR_IRSTS_TTR ? " TTR" : "",
822 status & CIR_IRSTS_TFU ? " TFU" : "",
823 status & CIR_IRSTS_GH ? " GH" : "",
824 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
825 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
826 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
827 }
828
829 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
830 {
831 unsigned long flags;
832 u8 tx_state;
833
834 spin_lock_irqsave(&nvt->tx.lock, flags);
835 tx_state = nvt->tx.tx_state;
836 spin_unlock_irqrestore(&nvt->tx.lock, flags);
837
838 return tx_state == ST_TX_NONE;
839 }
840
841 /* interrupt service routine for incoming and outgoing CIR data */
842 static irqreturn_t nvt_cir_isr(int irq, void *data)
843 {
844 struct nvt_dev *nvt = data;
845 u8 status, iren;
846 unsigned long flags;
847
848 nvt_dbg_verbose("%s firing", __func__);
849
850 spin_lock_irqsave(&nvt->nvt_lock, flags);
851
852 /*
853 * Get IR Status register contents. Write 1 to ack/clear
854 *
855 * bit: reg name - description
856 * 7: CIR_IRSTS_RDR - RX Data Ready
857 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
858 * 5: CIR_IRSTS_PE - Packet End
859 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
860 * 3: CIR_IRSTS_TE - TX FIFO Empty
861 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
862 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
863 * 0: CIR_IRSTS_GH - Min Length Detected
864 */
865 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
866 iren = nvt_cir_reg_read(nvt, CIR_IREN);
867
868 /* At least NCT6779D creates a spurious interrupt when the
869 * logical device is being disabled.
870 */
871 if (status == 0xff && iren == 0xff) {
872 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
873 nvt_dbg_verbose("Spurious interrupt detected");
874 return IRQ_HANDLED;
875 }
876
877 /* IRQ may be shared with CIR WAKE, therefore check for each
878 * status bit whether the related interrupt source is enabled
879 */
880 if (!(status & iren)) {
881 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
882 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
883 return IRQ_NONE;
884 }
885
886 /* ack/clear all irq flags we've got */
887 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
888 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
889
890 nvt_cir_log_irqs(status, iren);
891
892 if (status & CIR_IRSTS_RFO)
893 nvt_handle_rx_fifo_overrun(nvt);
894
895 else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE)) {
896 /* We only do rx if not tx'ing */
897 if (nvt_cir_tx_inactive(nvt))
898 nvt_get_rx_ir_data(nvt);
899 }
900
901 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
902
903 if (status & CIR_IRSTS_TE)
904 nvt_clear_tx_fifo(nvt);
905
906 if (status & CIR_IRSTS_TTR) {
907 unsigned int pos, count;
908 u8 tmp;
909
910 spin_lock_irqsave(&nvt->tx.lock, flags);
911
912 pos = nvt->tx.cur_buf_num;
913 count = nvt->tx.buf_count;
914
915 /* Write data into the hardware tx fifo while pos < count */
916 if (pos < count) {
917 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
918 nvt->tx.cur_buf_num++;
919 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
920 } else {
921 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
922 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
923 }
924
925 spin_unlock_irqrestore(&nvt->tx.lock, flags);
926
927 }
928
929 if (status & CIR_IRSTS_TFU) {
930 spin_lock_irqsave(&nvt->tx.lock, flags);
931 if (nvt->tx.tx_state == ST_TX_REPLY) {
932 nvt->tx.tx_state = ST_TX_REQUEST;
933 wake_up(&nvt->tx.queue);
934 }
935 spin_unlock_irqrestore(&nvt->tx.lock, flags);
936 }
937
938 nvt_dbg_verbose("%s done", __func__);
939 return IRQ_HANDLED;
940 }
941
942 static void nvt_disable_cir(struct nvt_dev *nvt)
943 {
944 unsigned long flags;
945
946 spin_lock_irqsave(&nvt->nvt_lock, flags);
947
948 /* disable CIR interrupts */
949 nvt_cir_reg_write(nvt, 0, CIR_IREN);
950
951 /* clear any and all pending interrupts */
952 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
953
954 /* clear all function enable flags */
955 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
956
957 /* clear hardware rx and tx fifos */
958 nvt_clear_cir_fifo(nvt);
959 nvt_clear_tx_fifo(nvt);
960
961 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
962
963 /* disable the CIR logical device */
964 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
965 }
966
967 static int nvt_open(struct rc_dev *dev)
968 {
969 struct nvt_dev *nvt = dev->priv;
970 unsigned long flags;
971
972 spin_lock_irqsave(&nvt->nvt_lock, flags);
973
974 /* set function enable flags */
975 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
976 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
977 CIR_IRCON);
978
979 /* clear all pending interrupts */
980 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
981
982 /* enable interrupts */
983 nvt_set_cir_iren(nvt);
984
985 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
986
987 /* enable the CIR logical device */
988 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
989
990 return 0;
991 }
992
993 static void nvt_close(struct rc_dev *dev)
994 {
995 struct nvt_dev *nvt = dev->priv;
996
997 nvt_disable_cir(nvt);
998 }
999
1000 /* Allocate memory, probe hardware, and initialize everything */
1001 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1002 {
1003 struct nvt_dev *nvt;
1004 struct rc_dev *rdev;
1005 int ret = -ENOMEM;
1006
1007 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
1008 if (!nvt)
1009 return ret;
1010
1011 /* input device for IR remote (and tx) */
1012 rdev = rc_allocate_device();
1013 if (!rdev)
1014 goto exit_free_dev_rdev;
1015
1016 ret = -ENODEV;
1017 /* activate pnp device */
1018 if (pnp_activate_dev(pdev) < 0) {
1019 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1020 goto exit_free_dev_rdev;
1021 }
1022
1023 /* validate pnp resources */
1024 if (!pnp_port_valid(pdev, 0) ||
1025 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1026 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1027 goto exit_free_dev_rdev;
1028 }
1029
1030 if (!pnp_irq_valid(pdev, 0)) {
1031 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1032 goto exit_free_dev_rdev;
1033 }
1034
1035 if (!pnp_port_valid(pdev, 1) ||
1036 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1037 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1038 goto exit_free_dev_rdev;
1039 }
1040
1041 nvt->cir_addr = pnp_port_start(pdev, 0);
1042 nvt->cir_irq = pnp_irq(pdev, 0);
1043
1044 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1045
1046 nvt->cr_efir = CR_EFIR;
1047 nvt->cr_efdr = CR_EFDR;
1048
1049 spin_lock_init(&nvt->nvt_lock);
1050 spin_lock_init(&nvt->tx.lock);
1051
1052 pnp_set_drvdata(pdev, nvt);
1053 nvt->pdev = pdev;
1054
1055 init_waitqueue_head(&nvt->tx.queue);
1056
1057 ret = nvt_hw_detect(nvt);
1058 if (ret)
1059 goto exit_free_dev_rdev;
1060
1061 /* Initialize CIR & CIR Wake Logical Devices */
1062 nvt_efm_enable(nvt);
1063 nvt_cir_ldev_init(nvt);
1064 nvt_cir_wake_ldev_init(nvt);
1065 nvt_efm_disable(nvt);
1066
1067 /*
1068 * Initialize CIR & CIR Wake Config Registers
1069 * and enable logical devices
1070 */
1071 nvt_cir_regs_init(nvt);
1072 nvt_cir_wake_regs_init(nvt);
1073
1074 /* Set up the rc device */
1075 rdev->priv = nvt;
1076 rdev->driver_type = RC_DRIVER_IR_RAW;
1077 rdev->allowed_protocols = RC_BIT_ALL;
1078 rdev->open = nvt_open;
1079 rdev->close = nvt_close;
1080 rdev->tx_ir = nvt_tx_ir;
1081 rdev->s_tx_carrier = nvt_set_tx_carrier;
1082 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1083 rdev->input_phys = "nuvoton/cir0";
1084 rdev->input_id.bustype = BUS_HOST;
1085 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1086 rdev->input_id.product = nvt->chip_major;
1087 rdev->input_id.version = nvt->chip_minor;
1088 rdev->dev.parent = &pdev->dev;
1089 rdev->driver_name = NVT_DRIVER_NAME;
1090 rdev->map_name = RC_MAP_RC6_MCE;
1091 rdev->timeout = MS_TO_NS(100);
1092 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1093 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1094 #if 0
1095 rdev->min_timeout = XYZ;
1096 rdev->max_timeout = XYZ;
1097 /* tx bits */
1098 rdev->tx_resolution = XYZ;
1099 #endif
1100 nvt->rdev = rdev;
1101
1102 ret = rc_register_device(rdev);
1103 if (ret)
1104 goto exit_free_dev_rdev;
1105
1106 ret = -EBUSY;
1107 /* now claim resources */
1108 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1109 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1110 goto exit_unregister_device;
1111
1112 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1113 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1114 goto exit_unregister_device;
1115
1116 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1117 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1118 goto exit_unregister_device;
1119
1120 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1121 if (ret)
1122 goto exit_unregister_device;
1123
1124 device_init_wakeup(&pdev->dev, true);
1125
1126 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1127 if (debug) {
1128 cir_dump_regs(nvt);
1129 cir_wake_dump_regs(nvt);
1130 }
1131
1132 return 0;
1133
1134 exit_unregister_device:
1135 rc_unregister_device(rdev);
1136 rdev = NULL;
1137 exit_free_dev_rdev:
1138 rc_free_device(rdev);
1139
1140 return ret;
1141 }
1142
1143 static void nvt_remove(struct pnp_dev *pdev)
1144 {
1145 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1146
1147 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1148
1149 nvt_disable_cir(nvt);
1150
1151 /* enable CIR Wake (for IR power-on) */
1152 nvt_enable_wake(nvt);
1153
1154 rc_unregister_device(nvt->rdev);
1155 }
1156
1157 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1158 {
1159 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1160 unsigned long flags;
1161
1162 nvt_dbg("%s called", __func__);
1163
1164 spin_lock_irqsave(&nvt->tx.lock, flags);
1165 nvt->tx.tx_state = ST_TX_NONE;
1166 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1167
1168 spin_lock_irqsave(&nvt->nvt_lock, flags);
1169
1170 /* disable all CIR interrupts */
1171 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1172
1173 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1174
1175 /* disable cir logical dev */
1176 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1177
1178 /* make sure wake is enabled */
1179 nvt_enable_wake(nvt);
1180
1181 return 0;
1182 }
1183
1184 static int nvt_resume(struct pnp_dev *pdev)
1185 {
1186 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1187
1188 nvt_dbg("%s called", __func__);
1189
1190 nvt_cir_regs_init(nvt);
1191 nvt_cir_wake_regs_init(nvt);
1192
1193 return 0;
1194 }
1195
1196 static void nvt_shutdown(struct pnp_dev *pdev)
1197 {
1198 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1199
1200 nvt_enable_wake(nvt);
1201 }
1202
1203 static const struct pnp_device_id nvt_ids[] = {
1204 { "WEC0530", 0 }, /* CIR */
1205 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1206 { "", 0 },
1207 };
1208
1209 static struct pnp_driver nvt_driver = {
1210 .name = NVT_DRIVER_NAME,
1211 .id_table = nvt_ids,
1212 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1213 .probe = nvt_probe,
1214 .remove = nvt_remove,
1215 .suspend = nvt_suspend,
1216 .resume = nvt_resume,
1217 .shutdown = nvt_shutdown,
1218 };
1219
1220 module_param(debug, int, S_IRUGO | S_IWUSR);
1221 MODULE_PARM_DESC(debug, "Enable debugging output");
1222
1223 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1224 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1225
1226 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1227 MODULE_LICENSE("GPL");
1228
1229 module_pnp_driver(nvt_driver);
Linux with added FPC-III support