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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-rockchip.c
blobf826793e972c533077236aebfdf9b83bc16c8f9f
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
43
44 #include "core.h"
45 #include "pinconf.h"
46
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
60
61 enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
65 RK3288,
66 RK3368,
67 RK3399,
68 };
69
70 /**
71 * Encode variants of iomux registers into a type variable
72 */
73 #define IOMUX_GPIO_ONLY BIT(0)
74 #define IOMUX_WIDTH_4BIT BIT(1)
75 #define IOMUX_SOURCE_PMU BIT(2)
76 #define IOMUX_UNROUTED BIT(3)
77
78 /**
79 * @type: iomux variant using IOMUX_* constants
80 * @offset: if initialized to -1 it will be autocalculated, by specifying
81 * an initial offset value the relevant source offset can be reset
82 * to a new value for autocalculating the following iomux registers.
83 */
84 struct rockchip_iomux {
85 int type;
86 int offset;
87 };
88
89 /**
90 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
91 */
92 enum rockchip_pin_drv_type {
93 DRV_TYPE_IO_DEFAULT = 0,
94 DRV_TYPE_IO_1V8_OR_3V0,
95 DRV_TYPE_IO_1V8_ONLY,
96 DRV_TYPE_IO_1V8_3V0_AUTO,
97 DRV_TYPE_IO_3V3_ONLY,
98 DRV_TYPE_MAX
99 };
100
101 /**
102 * enum type index corresponding to rockchip_pull_list arrays index.
103 */
104 enum rockchip_pin_pull_type {
105 PULL_TYPE_IO_DEFAULT = 0,
106 PULL_TYPE_IO_1V8_ONLY,
107 PULL_TYPE_MAX
108 };
109
110 /**
111 * @drv_type: drive strength variant using rockchip_perpin_drv_type
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
113 * an initial offset value the relevant source offset can be reset
114 * to a new value for autocalculating the following drive strength
115 * registers. if used chips own cal_drv func instead to calculate
116 * registers offset, the variant could be ignored.
117 */
118 struct rockchip_drv {
119 enum rockchip_pin_drv_type drv_type;
120 int offset;
121 };
122
123 /**
124 * @reg_base: register base of the gpio bank
125 * @reg_pull: optional separate register for additional pull settings
126 * @clk: clock of the gpio bank
127 * @irq: interrupt of the gpio bank
128 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
129 * @pin_base: first pin number
130 * @nr_pins: number of pins in this bank
131 * @name: name of the bank
132 * @bank_num: number of the bank, to account for holes
133 * @iomux: array describing the 4 iomux sources of the bank
134 * @drv: array describing the 4 drive strength sources of the bank
135 * @pull_type: array describing the 4 pull type sources of the bank
136 * @valid: are all necessary informations present
137 * @of_node: dt node of this bank
138 * @drvdata: common pinctrl basedata
139 * @domain: irqdomain of the gpio bank
140 * @gpio_chip: gpiolib chip
141 * @grange: gpio range
142 * @slock: spinlock for the gpio bank
143 */
144 struct rockchip_pin_bank {
145 void __iomem *reg_base;
146 struct regmap *regmap_pull;
147 struct clk *clk;
148 int irq;
149 u32 saved_masks;
150 u32 pin_base;
151 u8 nr_pins;
152 char *name;
153 u8 bank_num;
154 struct rockchip_iomux iomux[4];
155 struct rockchip_drv drv[4];
156 enum rockchip_pin_pull_type pull_type[4];
157 bool valid;
158 struct device_node *of_node;
159 struct rockchip_pinctrl *drvdata;
160 struct irq_domain *domain;
161 struct gpio_chip gpio_chip;
162 struct pinctrl_gpio_range grange;
163 spinlock_t slock;
164 u32 toggle_edge_mode;
165 };
166
167 #define PIN_BANK(id, pins, label) \
168 { \
169 .bank_num = id, \
170 .nr_pins = pins, \
171 .name = label, \
172 .iomux = { \
173 { .offset = -1 }, \
174 { .offset = -1 }, \
175 { .offset = -1 }, \
176 { .offset = -1 }, \
177 }, \
178 }
179
180 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
181 { \
182 .bank_num = id, \
183 .nr_pins = pins, \
184 .name = label, \
185 .iomux = { \
186 { .type = iom0, .offset = -1 }, \
187 { .type = iom1, .offset = -1 }, \
188 { .type = iom2, .offset = -1 }, \
189 { .type = iom3, .offset = -1 }, \
190 }, \
191 }
192
193 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
194 { \
195 .bank_num = id, \
196 .nr_pins = pins, \
197 .name = label, \
198 .iomux = { \
199 { .offset = -1 }, \
200 { .offset = -1 }, \
201 { .offset = -1 }, \
202 { .offset = -1 }, \
203 }, \
204 .drv = { \
205 { .drv_type = type0, .offset = -1 }, \
206 { .drv_type = type1, .offset = -1 }, \
207 { .drv_type = type2, .offset = -1 }, \
208 { .drv_type = type3, .offset = -1 }, \
209 }, \
210 }
211
212 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
213 drv2, drv3, pull0, pull1, \
214 pull2, pull3) \
215 { \
216 .bank_num = id, \
217 .nr_pins = pins, \
218 .name = label, \
219 .iomux = { \
220 { .offset = -1 }, \
221 { .offset = -1 }, \
222 { .offset = -1 }, \
223 { .offset = -1 }, \
224 }, \
225 .drv = { \
226 { .drv_type = drv0, .offset = -1 }, \
227 { .drv_type = drv1, .offset = -1 }, \
228 { .drv_type = drv2, .offset = -1 }, \
229 { .drv_type = drv3, .offset = -1 }, \
230 }, \
231 .pull_type[0] = pull0, \
232 .pull_type[1] = pull1, \
233 .pull_type[2] = pull2, \
234 .pull_type[3] = pull3, \
235 }
236
237 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
238 iom2, iom3, drv0, drv1, drv2, \
239 drv3, offset0, offset1, \
240 offset2, offset3) \
241 { \
242 .bank_num = id, \
243 .nr_pins = pins, \
244 .name = label, \
245 .iomux = { \
246 { .type = iom0, .offset = -1 }, \
247 { .type = iom1, .offset = -1 }, \
248 { .type = iom2, .offset = -1 }, \
249 { .type = iom3, .offset = -1 }, \
250 }, \
251 .drv = { \
252 { .drv_type = drv0, .offset = offset0 }, \
253 { .drv_type = drv1, .offset = offset1 }, \
254 { .drv_type = drv2, .offset = offset2 }, \
255 { .drv_type = drv3, .offset = offset3 }, \
256 }, \
257 }
258
259 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
260 label, iom0, iom1, iom2, \
261 iom3, drv0, drv1, drv2, \
262 drv3, offset0, offset1, \
263 offset2, offset3, pull0, \
264 pull1, pull2, pull3) \
265 { \
266 .bank_num = id, \
267 .nr_pins = pins, \
268 .name = label, \
269 .iomux = { \
270 { .type = iom0, .offset = -1 }, \
271 { .type = iom1, .offset = -1 }, \
272 { .type = iom2, .offset = -1 }, \
273 { .type = iom3, .offset = -1 }, \
274 }, \
275 .drv = { \
276 { .drv_type = drv0, .offset = offset0 }, \
277 { .drv_type = drv1, .offset = offset1 }, \
278 { .drv_type = drv2, .offset = offset2 }, \
279 { .drv_type = drv3, .offset = offset3 }, \
280 }, \
281 .pull_type[0] = pull0, \
282 .pull_type[1] = pull1, \
283 .pull_type[2] = pull2, \
284 .pull_type[3] = pull3, \
285 }
286
287 /**
288 */
289 struct rockchip_pin_ctrl {
290 struct rockchip_pin_bank *pin_banks;
291 u32 nr_banks;
292 u32 nr_pins;
293 char *label;
294 enum rockchip_pinctrl_type type;
295 int grf_mux_offset;
296 int pmu_mux_offset;
297 int grf_drv_offset;
298 int pmu_drv_offset;
299
300 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
301 int pin_num, struct regmap **regmap,
302 int *reg, u8 *bit);
303 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
304 int pin_num, struct regmap **regmap,
305 int *reg, u8 *bit);
306 };
307
308 struct rockchip_pin_config {
309 unsigned int func;
310 unsigned long *configs;
311 unsigned int nconfigs;
312 };
313
314 /**
315 * struct rockchip_pin_group: represent group of pins of a pinmux function.
316 * @name: name of the pin group, used to lookup the group.
317 * @pins: the pins included in this group.
318 * @npins: number of pins included in this group.
319 * @func: the mux function number to be programmed when selected.
320 * @configs: the config values to be set for each pin
321 * @nconfigs: number of configs for each pin
322 */
323 struct rockchip_pin_group {
324 const char *name;
325 unsigned int npins;
326 unsigned int *pins;
327 struct rockchip_pin_config *data;
328 };
329
330 /**
331 * struct rockchip_pmx_func: represent a pin function.
332 * @name: name of the pin function, used to lookup the function.
333 * @groups: one or more names of pin groups that provide this function.
334 * @num_groups: number of groups included in @groups.
335 */
336 struct rockchip_pmx_func {
337 const char *name;
338 const char **groups;
339 u8 ngroups;
340 };
341
342 struct rockchip_pinctrl {
343 struct regmap *regmap_base;
344 int reg_size;
345 struct regmap *regmap_pull;
346 struct regmap *regmap_pmu;
347 struct device *dev;
348 struct rockchip_pin_ctrl *ctrl;
349 struct pinctrl_desc pctl;
350 struct pinctrl_dev *pctl_dev;
351 struct rockchip_pin_group *groups;
352 unsigned int ngroups;
353 struct rockchip_pmx_func *functions;
354 unsigned int nfunctions;
355 };
356
357 static struct regmap_config rockchip_regmap_config = {
358 .reg_bits = 32,
359 .val_bits = 32,
360 .reg_stride = 4,
361 };
362
363 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
364 const struct rockchip_pinctrl *info,
365 const char *name)
366 {
367 int i;
368
369 for (i = 0; i < info->ngroups; i++) {
370 if (!strcmp(info->groups[i].name, name))
371 return &info->groups[i];
372 }
373
374 return NULL;
375 }
376
377 /*
378 * given a pin number that is local to a pin controller, find out the pin bank
379 * and the register base of the pin bank.
380 */
381 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
382 unsigned pin)
383 {
384 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
385
386 while (pin >= (b->pin_base + b->nr_pins))
387 b++;
388
389 return b;
390 }
391
392 static struct rockchip_pin_bank *bank_num_to_bank(
393 struct rockchip_pinctrl *info,
394 unsigned num)
395 {
396 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
397 int i;
398
399 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
400 if (b->bank_num == num)
401 return b;
402 }
403
404 return ERR_PTR(-EINVAL);
405 }
406
407 /*
408 * Pinctrl_ops handling
409 */
410
411 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
412 {
413 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
414
415 return info->ngroups;
416 }
417
418 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
419 unsigned selector)
420 {
421 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
422
423 return info->groups[selector].name;
424 }
425
426 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
427 unsigned selector, const unsigned **pins,
428 unsigned *npins)
429 {
430 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
431
432 if (selector >= info->ngroups)
433 return -EINVAL;
434
435 *pins = info->groups[selector].pins;
436 *npins = info->groups[selector].npins;
437
438 return 0;
439 }
440
441 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
442 struct device_node *np,
443 struct pinctrl_map **map, unsigned *num_maps)
444 {
445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
446 const struct rockchip_pin_group *grp;
447 struct pinctrl_map *new_map;
448 struct device_node *parent;
449 int map_num = 1;
450 int i;
451
452 /*
453 * first find the group of this node and check if we need to create
454 * config maps for pins
455 */
456 grp = pinctrl_name_to_group(info, np->name);
457 if (!grp) {
458 dev_err(info->dev, "unable to find group for node %s\n",
459 np->name);
460 return -EINVAL;
461 }
462
463 map_num += grp->npins;
464 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
465 GFP_KERNEL);
466 if (!new_map)
467 return -ENOMEM;
468
469 *map = new_map;
470 *num_maps = map_num;
471
472 /* create mux map */
473 parent = of_get_parent(np);
474 if (!parent) {
475 devm_kfree(pctldev->dev, new_map);
476 return -EINVAL;
477 }
478 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
479 new_map[0].data.mux.function = parent->name;
480 new_map[0].data.mux.group = np->name;
481 of_node_put(parent);
482
483 /* create config map */
484 new_map++;
485 for (i = 0; i < grp->npins; i++) {
486 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
487 new_map[i].data.configs.group_or_pin =
488 pin_get_name(pctldev, grp->pins[i]);
489 new_map[i].data.configs.configs = grp->data[i].configs;
490 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
491 }
492
493 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
494 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
495
496 return 0;
497 }
498
499 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
500 struct pinctrl_map *map, unsigned num_maps)
501 {
502 }
503
504 static const struct pinctrl_ops rockchip_pctrl_ops = {
505 .get_groups_count = rockchip_get_groups_count,
506 .get_group_name = rockchip_get_group_name,
507 .get_group_pins = rockchip_get_group_pins,
508 .dt_node_to_map = rockchip_dt_node_to_map,
509 .dt_free_map = rockchip_dt_free_map,
510 };
511
512 /*
513 * Hardware access
514 */
515
516 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
517 {
518 struct rockchip_pinctrl *info = bank->drvdata;
519 int iomux_num = (pin / 8);
520 struct regmap *regmap;
521 unsigned int val;
522 int reg, ret, mask;
523 u8 bit;
524
525 if (iomux_num > 3)
526 return -EINVAL;
527
528 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
529 dev_err(info->dev, "pin %d is unrouted\n", pin);
530 return -EINVAL;
531 }
532
533 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
534 return RK_FUNC_GPIO;
535
536 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
537 ? info->regmap_pmu : info->regmap_base;
538
539 /* get basic quadrupel of mux registers and the correct reg inside */
540 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
541 reg = bank->iomux[iomux_num].offset;
542 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
543 if ((pin % 8) >= 4)
544 reg += 0x4;
545 bit = (pin % 4) * 4;
546 } else {
547 bit = (pin % 8) * 2;
548 }
549
550 ret = regmap_read(regmap, reg, &val);
551 if (ret)
552 return ret;
553
554 return ((val >> bit) & mask);
555 }
556
557 /*
558 * Set a new mux function for a pin.
559 *
560 * The register is divided into the upper and lower 16 bit. When changing
561 * a value, the previous register value is not read and changed. Instead
562 * it seems the changed bits are marked in the upper 16 bit, while the
563 * changed value gets set in the same offset in the lower 16 bit.
564 * All pin settings seem to be 2 bit wide in both the upper and lower
565 * parts.
566 * @bank: pin bank to change
567 * @pin: pin to change
568 * @mux: new mux function to set
569 */
570 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
571 {
572 struct rockchip_pinctrl *info = bank->drvdata;
573 int iomux_num = (pin / 8);
574 struct regmap *regmap;
575 int reg, ret, mask;
576 unsigned long flags;
577 u8 bit;
578 u32 data, rmask;
579
580 if (iomux_num > 3)
581 return -EINVAL;
582
583 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
584 dev_err(info->dev, "pin %d is unrouted\n", pin);
585 return -EINVAL;
586 }
587
588 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
589 if (mux != RK_FUNC_GPIO) {
590 dev_err(info->dev,
591 "pin %d only supports a gpio mux\n", pin);
592 return -ENOTSUPP;
593 } else {
594 return 0;
595 }
596 }
597
598 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
599 bank->bank_num, pin, mux);
600
601 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
602 ? info->regmap_pmu : info->regmap_base;
603
604 /* get basic quadrupel of mux registers and the correct reg inside */
605 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
606 reg = bank->iomux[iomux_num].offset;
607 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
608 if ((pin % 8) >= 4)
609 reg += 0x4;
610 bit = (pin % 4) * 4;
611 } else {
612 bit = (pin % 8) * 2;
613 }
614
615 spin_lock_irqsave(&bank->slock, flags);
616
617 data = (mask << (bit + 16));
618 rmask = data | (data >> 16);
619 data |= (mux & mask) << bit;
620 ret = regmap_update_bits(regmap, reg, rmask, data);
621
622 spin_unlock_irqrestore(&bank->slock, flags);
623
624 return ret;
625 }
626
627 #define RK2928_PULL_OFFSET 0x118
628 #define RK2928_PULL_PINS_PER_REG 16
629 #define RK2928_PULL_BANK_STRIDE 8
630
631 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
632 int pin_num, struct regmap **regmap,
633 int *reg, u8 *bit)
634 {
635 struct rockchip_pinctrl *info = bank->drvdata;
636
637 *regmap = info->regmap_base;
638 *reg = RK2928_PULL_OFFSET;
639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
640 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
641
642 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
643 };
644
645 #define RK3188_PULL_OFFSET 0x164
646 #define RK3188_PULL_BITS_PER_PIN 2
647 #define RK3188_PULL_PINS_PER_REG 8
648 #define RK3188_PULL_BANK_STRIDE 16
649 #define RK3188_PULL_PMU_OFFSET 0x64
650
651 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
652 int pin_num, struct regmap **regmap,
653 int *reg, u8 *bit)
654 {
655 struct rockchip_pinctrl *info = bank->drvdata;
656
657 /* The first 12 pins of the first bank are located elsewhere */
658 if (bank->bank_num == 0 && pin_num < 12) {
659 *regmap = info->regmap_pmu ? info->regmap_pmu
660 : bank->regmap_pull;
661 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
662 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
663 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
664 *bit *= RK3188_PULL_BITS_PER_PIN;
665 } else {
666 *regmap = info->regmap_pull ? info->regmap_pull
667 : info->regmap_base;
668 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
669
670 /* correct the offset, as it is the 2nd pull register */
671 *reg -= 4;
672 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
673 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
674
675 /*
676 * The bits in these registers have an inverse ordering
677 * with the lowest pin being in bits 15:14 and the highest
678 * pin in bits 1:0
679 */
680 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
681 *bit *= RK3188_PULL_BITS_PER_PIN;
682 }
683 }
684
685 #define RK3288_PULL_OFFSET 0x140
686 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
687 int pin_num, struct regmap **regmap,
688 int *reg, u8 *bit)
689 {
690 struct rockchip_pinctrl *info = bank->drvdata;
691
692 /* The first 24 pins of the first bank are located in PMU */
693 if (bank->bank_num == 0) {
694 *regmap = info->regmap_pmu;
695 *reg = RK3188_PULL_PMU_OFFSET;
696
697 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
698 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
699 *bit *= RK3188_PULL_BITS_PER_PIN;
700 } else {
701 *regmap = info->regmap_base;
702 *reg = RK3288_PULL_OFFSET;
703
704 /* correct the offset, as we're starting with the 2nd bank */
705 *reg -= 0x10;
706 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
707 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
708
709 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
710 *bit *= RK3188_PULL_BITS_PER_PIN;
711 }
712 }
713
714 #define RK3288_DRV_PMU_OFFSET 0x70
715 #define RK3288_DRV_GRF_OFFSET 0x1c0
716 #define RK3288_DRV_BITS_PER_PIN 2
717 #define RK3288_DRV_PINS_PER_REG 8
718 #define RK3288_DRV_BANK_STRIDE 16
719
720 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
721 int pin_num, struct regmap **regmap,
722 int *reg, u8 *bit)
723 {
724 struct rockchip_pinctrl *info = bank->drvdata;
725
726 /* The first 24 pins of the first bank are located in PMU */
727 if (bank->bank_num == 0) {
728 *regmap = info->regmap_pmu;
729 *reg = RK3288_DRV_PMU_OFFSET;
730
731 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
732 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
733 *bit *= RK3288_DRV_BITS_PER_PIN;
734 } else {
735 *regmap = info->regmap_base;
736 *reg = RK3288_DRV_GRF_OFFSET;
737
738 /* correct the offset, as we're starting with the 2nd bank */
739 *reg -= 0x10;
740 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
741 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
742
743 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
744 *bit *= RK3288_DRV_BITS_PER_PIN;
745 }
746 }
747
748 #define RK3228_PULL_OFFSET 0x100
749
750 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751 int pin_num, struct regmap **regmap,
752 int *reg, u8 *bit)
753 {
754 struct rockchip_pinctrl *info = bank->drvdata;
755
756 *regmap = info->regmap_base;
757 *reg = RK3228_PULL_OFFSET;
758 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
759 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
760
761 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
762 *bit *= RK3188_PULL_BITS_PER_PIN;
763 }
764
765 #define RK3228_DRV_GRF_OFFSET 0x200
766
767 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
768 int pin_num, struct regmap **regmap,
769 int *reg, u8 *bit)
770 {
771 struct rockchip_pinctrl *info = bank->drvdata;
772
773 *regmap = info->regmap_base;
774 *reg = RK3228_DRV_GRF_OFFSET;
775 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
776 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
777
778 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
779 *bit *= RK3288_DRV_BITS_PER_PIN;
780 }
781
782 #define RK3368_PULL_GRF_OFFSET 0x100
783 #define RK3368_PULL_PMU_OFFSET 0x10
784
785 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
786 int pin_num, struct regmap **regmap,
787 int *reg, u8 *bit)
788 {
789 struct rockchip_pinctrl *info = bank->drvdata;
790
791 /* The first 32 pins of the first bank are located in PMU */
792 if (bank->bank_num == 0) {
793 *regmap = info->regmap_pmu;
794 *reg = RK3368_PULL_PMU_OFFSET;
795
796 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
797 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
798 *bit *= RK3188_PULL_BITS_PER_PIN;
799 } else {
800 *regmap = info->regmap_base;
801 *reg = RK3368_PULL_GRF_OFFSET;
802
803 /* correct the offset, as we're starting with the 2nd bank */
804 *reg -= 0x10;
805 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
806 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
807
808 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
809 *bit *= RK3188_PULL_BITS_PER_PIN;
810 }
811 }
812
813 #define RK3368_DRV_PMU_OFFSET 0x20
814 #define RK3368_DRV_GRF_OFFSET 0x200
815
816 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
817 int pin_num, struct regmap **regmap,
818 int *reg, u8 *bit)
819 {
820 struct rockchip_pinctrl *info = bank->drvdata;
821
822 /* The first 32 pins of the first bank are located in PMU */
823 if (bank->bank_num == 0) {
824 *regmap = info->regmap_pmu;
825 *reg = RK3368_DRV_PMU_OFFSET;
826
827 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
828 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
829 *bit *= RK3288_DRV_BITS_PER_PIN;
830 } else {
831 *regmap = info->regmap_base;
832 *reg = RK3368_DRV_GRF_OFFSET;
833
834 /* correct the offset, as we're starting with the 2nd bank */
835 *reg -= 0x10;
836 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
837 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
838
839 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
840 *bit *= RK3288_DRV_BITS_PER_PIN;
841 }
842 }
843
844 #define RK3399_PULL_GRF_OFFSET 0xe040
845 #define RK3399_PULL_PMU_OFFSET 0x40
846 #define RK3399_DRV_3BITS_PER_PIN 3
847
848 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
849 int pin_num, struct regmap **regmap,
850 int *reg, u8 *bit)
851 {
852 struct rockchip_pinctrl *info = bank->drvdata;
853
854 /* The bank0:16 and bank1:32 pins are located in PMU */
855 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
856 *regmap = info->regmap_pmu;
857 *reg = RK3399_PULL_PMU_OFFSET;
858
859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
860
861 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
862 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
863 *bit *= RK3188_PULL_BITS_PER_PIN;
864 } else {
865 *regmap = info->regmap_base;
866 *reg = RK3399_PULL_GRF_OFFSET;
867
868 /* correct the offset, as we're starting with the 3rd bank */
869 *reg -= 0x20;
870 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
871 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
872
873 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
874 *bit *= RK3188_PULL_BITS_PER_PIN;
875 }
876 }
877
878 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
879 int pin_num, struct regmap **regmap,
880 int *reg, u8 *bit)
881 {
882 struct rockchip_pinctrl *info = bank->drvdata;
883 int drv_num = (pin_num / 8);
884
885 /* The bank0:16 and bank1:32 pins are located in PMU */
886 if ((bank->bank_num == 0) || (bank->bank_num == 1))
887 *regmap = info->regmap_pmu;
888 else
889 *regmap = info->regmap_base;
890
891 *reg = bank->drv[drv_num].offset;
892 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
893 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
894 *bit = (pin_num % 8) * 3;
895 else
896 *bit = (pin_num % 8) * 2;
897 }
898
899 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
900 { 2, 4, 8, 12, -1, -1, -1, -1 },
901 { 3, 6, 9, 12, -1, -1, -1, -1 },
902 { 5, 10, 15, 20, -1, -1, -1, -1 },
903 { 4, 6, 8, 10, 12, 14, 16, 18 },
904 { 4, 7, 10, 13, 16, 19, 22, 26 }
905 };
906
907 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
908 int pin_num)
909 {
910 struct rockchip_pinctrl *info = bank->drvdata;
911 struct rockchip_pin_ctrl *ctrl = info->ctrl;
912 struct regmap *regmap;
913 int reg, ret;
914 u32 data, temp, rmask_bits;
915 u8 bit;
916 int drv_type = bank->drv[pin_num / 8].drv_type;
917
918 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
919
920 switch (drv_type) {
921 case DRV_TYPE_IO_1V8_3V0_AUTO:
922 case DRV_TYPE_IO_3V3_ONLY:
923 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
924 switch (bit) {
925 case 0 ... 12:
926 /* regular case, nothing to do */
927 break;
928 case 15:
929 /*
930 * drive-strength offset is special, as it is
931 * spread over 2 registers
932 */
933 ret = regmap_read(regmap, reg, &data);
934 if (ret)
935 return ret;
936
937 ret = regmap_read(regmap, reg + 0x4, &temp);
938 if (ret)
939 return ret;
940
941 /*
942 * the bit data[15] contains bit 0 of the value
943 * while temp[1:0] contains bits 2 and 1
944 */
945 data >>= 15;
946 temp &= 0x3;
947 temp <<= 1;
948 data |= temp;
949
950 return rockchip_perpin_drv_list[drv_type][data];
951 case 18 ... 21:
952 /* setting fully enclosed in the second register */
953 reg += 4;
954 bit -= 16;
955 break;
956 default:
957 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
958 bit, drv_type);
959 return -EINVAL;
960 }
961
962 break;
963 case DRV_TYPE_IO_DEFAULT:
964 case DRV_TYPE_IO_1V8_OR_3V0:
965 case DRV_TYPE_IO_1V8_ONLY:
966 rmask_bits = RK3288_DRV_BITS_PER_PIN;
967 break;
968 default:
969 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
970 drv_type);
971 return -EINVAL;
972 }
973
974 ret = regmap_read(regmap, reg, &data);
975 if (ret)
976 return ret;
977
978 data >>= bit;
979 data &= (1 << rmask_bits) - 1;
980
981 return rockchip_perpin_drv_list[drv_type][data];
982 }
983
984 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
985 int pin_num, int strength)
986 {
987 struct rockchip_pinctrl *info = bank->drvdata;
988 struct rockchip_pin_ctrl *ctrl = info->ctrl;
989 struct regmap *regmap;
990 unsigned long flags;
991 int reg, ret, i;
992 u32 data, rmask, rmask_bits, temp;
993 u8 bit;
994 int drv_type = bank->drv[pin_num / 8].drv_type;
995
996 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
997 bank->bank_num, pin_num, strength);
998
999 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1000
1001 ret = -EINVAL;
1002 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1003 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1004 ret = i;
1005 break;
1006 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1007 ret = rockchip_perpin_drv_list[drv_type][i];
1008 break;
1009 }
1010 }
1011
1012 if (ret < 0) {
1013 dev_err(info->dev, "unsupported driver strength %d\n",
1014 strength);
1015 return ret;
1016 }
1017
1018 spin_lock_irqsave(&bank->slock, flags);
1019
1020 switch (drv_type) {
1021 case DRV_TYPE_IO_1V8_3V0_AUTO:
1022 case DRV_TYPE_IO_3V3_ONLY:
1023 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1024 switch (bit) {
1025 case 0 ... 12:
1026 /* regular case, nothing to do */
1027 break;
1028 case 15:
1029 /*
1030 * drive-strength offset is special, as it is spread
1031 * over 2 registers, the bit data[15] contains bit 0
1032 * of the value while temp[1:0] contains bits 2 and 1
1033 */
1034 data = (ret & 0x1) << 15;
1035 temp = (ret >> 0x1) & 0x3;
1036
1037 rmask = BIT(15) | BIT(31);
1038 data |= BIT(31);
1039 ret = regmap_update_bits(regmap, reg, rmask, data);
1040 if (ret) {
1041 spin_unlock_irqrestore(&bank->slock, flags);
1042 return ret;
1043 }
1044
1045 rmask = 0x3 | (0x3 << 16);
1046 temp |= (0x3 << 16);
1047 reg += 0x4;
1048 ret = regmap_update_bits(regmap, reg, rmask, temp);
1049
1050 spin_unlock_irqrestore(&bank->slock, flags);
1051 return ret;
1052 case 18 ... 21:
1053 /* setting fully enclosed in the second register */
1054 reg += 4;
1055 bit -= 16;
1056 break;
1057 default:
1058 spin_unlock_irqrestore(&bank->slock, flags);
1059 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1060 bit, drv_type);
1061 return -EINVAL;
1062 }
1063 break;
1064 case DRV_TYPE_IO_DEFAULT:
1065 case DRV_TYPE_IO_1V8_OR_3V0:
1066 case DRV_TYPE_IO_1V8_ONLY:
1067 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1068 break;
1069 default:
1070 spin_unlock_irqrestore(&bank->slock, flags);
1071 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1072 drv_type);
1073 return -EINVAL;
1074 }
1075
1076 /* enable the write to the equivalent lower bits */
1077 data = ((1 << rmask_bits) - 1) << (bit + 16);
1078 rmask = data | (data >> 16);
1079 data |= (ret << bit);
1080
1081 ret = regmap_update_bits(regmap, reg, rmask, data);
1082 spin_unlock_irqrestore(&bank->slock, flags);
1083
1084 return ret;
1085 }
1086
1087 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1088 {
1089 PIN_CONFIG_BIAS_DISABLE,
1090 PIN_CONFIG_BIAS_PULL_UP,
1091 PIN_CONFIG_BIAS_PULL_DOWN,
1092 PIN_CONFIG_BIAS_BUS_HOLD
1093 },
1094 {
1095 PIN_CONFIG_BIAS_DISABLE,
1096 PIN_CONFIG_BIAS_PULL_DOWN,
1097 PIN_CONFIG_BIAS_DISABLE,
1098 PIN_CONFIG_BIAS_PULL_UP
1099 },
1100 };
1101
1102 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1103 {
1104 struct rockchip_pinctrl *info = bank->drvdata;
1105 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1106 struct regmap *regmap;
1107 int reg, ret, pull_type;
1108 u8 bit;
1109 u32 data;
1110
1111 /* rk3066b does support any pulls */
1112 if (ctrl->type == RK3066B)
1113 return PIN_CONFIG_BIAS_DISABLE;
1114
1115 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1116
1117 ret = regmap_read(regmap, reg, &data);
1118 if (ret)
1119 return ret;
1120
1121 switch (ctrl->type) {
1122 case RK2928:
1123 return !(data & BIT(bit))
1124 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1125 : PIN_CONFIG_BIAS_DISABLE;
1126 case RK3188:
1127 case RK3288:
1128 case RK3368:
1129 case RK3399:
1130 pull_type = bank->pull_type[pin_num / 8];
1131 data >>= bit;
1132 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1133
1134 return rockchip_pull_list[pull_type][data];
1135 default:
1136 dev_err(info->dev, "unsupported pinctrl type\n");
1137 return -EINVAL;
1138 };
1139 }
1140
1141 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1142 int pin_num, int pull)
1143 {
1144 struct rockchip_pinctrl *info = bank->drvdata;
1145 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1146 struct regmap *regmap;
1147 int reg, ret, i, pull_type;
1148 unsigned long flags;
1149 u8 bit;
1150 u32 data, rmask;
1151
1152 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1153 bank->bank_num, pin_num, pull);
1154
1155 /* rk3066b does support any pulls */
1156 if (ctrl->type == RK3066B)
1157 return pull ? -EINVAL : 0;
1158
1159 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1160
1161 switch (ctrl->type) {
1162 case RK2928:
1163 spin_lock_irqsave(&bank->slock, flags);
1164
1165 data = BIT(bit + 16);
1166 if (pull == PIN_CONFIG_BIAS_DISABLE)
1167 data |= BIT(bit);
1168 ret = regmap_write(regmap, reg, data);
1169
1170 spin_unlock_irqrestore(&bank->slock, flags);
1171 break;
1172 case RK3188:
1173 case RK3288:
1174 case RK3368:
1175 case RK3399:
1176 pull_type = bank->pull_type[pin_num / 8];
1177 ret = -EINVAL;
1178 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1179 i++) {
1180 if (rockchip_pull_list[pull_type][i] == pull) {
1181 ret = i;
1182 break;
1183 }
1184 }
1185
1186 if (ret < 0) {
1187 dev_err(info->dev, "unsupported pull setting %d\n",
1188 pull);
1189 return ret;
1190 }
1191
1192 spin_lock_irqsave(&bank->slock, flags);
1193
1194 /* enable the write to the equivalent lower bits */
1195 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1196 rmask = data | (data >> 16);
1197 data |= (ret << bit);
1198
1199 ret = regmap_update_bits(regmap, reg, rmask, data);
1200
1201 spin_unlock_irqrestore(&bank->slock, flags);
1202 break;
1203 default:
1204 dev_err(info->dev, "unsupported pinctrl type\n");
1205 return -EINVAL;
1206 }
1207
1208 return ret;
1209 }
1210
1211 /*
1212 * Pinmux_ops handling
1213 */
1214
1215 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1216 {
1217 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1218
1219 return info->nfunctions;
1220 }
1221
1222 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1223 unsigned selector)
1224 {
1225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1226
1227 return info->functions[selector].name;
1228 }
1229
1230 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1231 unsigned selector, const char * const **groups,
1232 unsigned * const num_groups)
1233 {
1234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1235
1236 *groups = info->functions[selector].groups;
1237 *num_groups = info->functions[selector].ngroups;
1238
1239 return 0;
1240 }
1241
1242 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1243 unsigned group)
1244 {
1245 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1246 const unsigned int *pins = info->groups[group].pins;
1247 const struct rockchip_pin_config *data = info->groups[group].data;
1248 struct rockchip_pin_bank *bank;
1249 int cnt, ret = 0;
1250
1251 dev_dbg(info->dev, "enable function %s group %s\n",
1252 info->functions[selector].name, info->groups[group].name);
1253
1254 /*
1255 * for each pin in the pin group selected, program the correspoding pin
1256 * pin function number in the config register.
1257 */
1258 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1259 bank = pin_to_bank(info, pins[cnt]);
1260 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1261 data[cnt].func);
1262 if (ret)
1263 break;
1264 }
1265
1266 if (ret) {
1267 /* revert the already done pin settings */
1268 for (cnt--; cnt >= 0; cnt--)
1269 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1270
1271 return ret;
1272 }
1273
1274 return 0;
1275 }
1276
1277 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1278 {
1279 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1280 u32 data;
1281 int ret;
1282
1283 ret = clk_enable(bank->clk);
1284 if (ret < 0) {
1285 dev_err(bank->drvdata->dev,
1286 "failed to enable clock for bank %s\n", bank->name);
1287 return ret;
1288 }
1289 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1290 clk_disable(bank->clk);
1291
1292 return !(data & BIT(offset));
1293 }
1294
1295 /*
1296 * The calls to gpio_direction_output() and gpio_direction_input()
1297 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1298 * function called from the gpiolib interface).
1299 */
1300 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1301 int pin, bool input)
1302 {
1303 struct rockchip_pin_bank *bank;
1304 int ret;
1305 unsigned long flags;
1306 u32 data;
1307
1308 bank = gpiochip_get_data(chip);
1309
1310 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1311 if (ret < 0)
1312 return ret;
1313
1314 clk_enable(bank->clk);
1315 spin_lock_irqsave(&bank->slock, flags);
1316
1317 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1318 /* set bit to 1 for output, 0 for input */
1319 if (!input)
1320 data |= BIT(pin);
1321 else
1322 data &= ~BIT(pin);
1323 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1324
1325 spin_unlock_irqrestore(&bank->slock, flags);
1326 clk_disable(bank->clk);
1327
1328 return 0;
1329 }
1330
1331 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1332 struct pinctrl_gpio_range *range,
1333 unsigned offset, bool input)
1334 {
1335 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1336 struct gpio_chip *chip;
1337 int pin;
1338
1339 chip = range->gc;
1340 pin = offset - chip->base;
1341 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1342 offset, range->name, pin, input ? "input" : "output");
1343
1344 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1345 input);
1346 }
1347
1348 static const struct pinmux_ops rockchip_pmx_ops = {
1349 .get_functions_count = rockchip_pmx_get_funcs_count,
1350 .get_function_name = rockchip_pmx_get_func_name,
1351 .get_function_groups = rockchip_pmx_get_groups,
1352 .set_mux = rockchip_pmx_set,
1353 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1354 };
1355
1356 /*
1357 * Pinconf_ops handling
1358 */
1359
1360 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1361 enum pin_config_param pull)
1362 {
1363 switch (ctrl->type) {
1364 case RK2928:
1365 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1366 pull == PIN_CONFIG_BIAS_DISABLE);
1367 case RK3066B:
1368 return pull ? false : true;
1369 case RK3188:
1370 case RK3288:
1371 case RK3368:
1372 case RK3399:
1373 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1374 }
1375
1376 return false;
1377 }
1378
1379 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1380 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1381
1382 /* set the pin config settings for a specified pin */
1383 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1384 unsigned long *configs, unsigned num_configs)
1385 {
1386 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1387 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1388 enum pin_config_param param;
1389 u16 arg;
1390 int i;
1391 int rc;
1392
1393 for (i = 0; i < num_configs; i++) {
1394 param = pinconf_to_config_param(configs[i]);
1395 arg = pinconf_to_config_argument(configs[i]);
1396
1397 switch (param) {
1398 case PIN_CONFIG_BIAS_DISABLE:
1399 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1400 param);
1401 if (rc)
1402 return rc;
1403 break;
1404 case PIN_CONFIG_BIAS_PULL_UP:
1405 case PIN_CONFIG_BIAS_PULL_DOWN:
1406 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1407 case PIN_CONFIG_BIAS_BUS_HOLD:
1408 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1409 return -ENOTSUPP;
1410
1411 if (!arg)
1412 return -EINVAL;
1413
1414 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1415 param);
1416 if (rc)
1417 return rc;
1418 break;
1419 case PIN_CONFIG_OUTPUT:
1420 rockchip_gpio_set(&bank->gpio_chip,
1421 pin - bank->pin_base, arg);
1422 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1423 pin - bank->pin_base, false);
1424 if (rc)
1425 return rc;
1426 break;
1427 case PIN_CONFIG_DRIVE_STRENGTH:
1428 /* rk3288 is the first with per-pin drive-strength */
1429 if (!info->ctrl->drv_calc_reg)
1430 return -ENOTSUPP;
1431
1432 rc = rockchip_set_drive_perpin(bank,
1433 pin - bank->pin_base, arg);
1434 if (rc < 0)
1435 return rc;
1436 break;
1437 default:
1438 return -ENOTSUPP;
1439 break;
1440 }
1441 } /* for each config */
1442
1443 return 0;
1444 }
1445
1446 /* get the pin config settings for a specified pin */
1447 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1448 unsigned long *config)
1449 {
1450 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1451 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1452 enum pin_config_param param = pinconf_to_config_param(*config);
1453 u16 arg;
1454 int rc;
1455
1456 switch (param) {
1457 case PIN_CONFIG_BIAS_DISABLE:
1458 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1459 return -EINVAL;
1460
1461 arg = 0;
1462 break;
1463 case PIN_CONFIG_BIAS_PULL_UP:
1464 case PIN_CONFIG_BIAS_PULL_DOWN:
1465 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1466 case PIN_CONFIG_BIAS_BUS_HOLD:
1467 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1468 return -ENOTSUPP;
1469
1470 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1471 return -EINVAL;
1472
1473 arg = 1;
1474 break;
1475 case PIN_CONFIG_OUTPUT:
1476 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1477 if (rc != RK_FUNC_GPIO)
1478 return -EINVAL;
1479
1480 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1481 if (rc < 0)
1482 return rc;
1483
1484 arg = rc ? 1 : 0;
1485 break;
1486 case PIN_CONFIG_DRIVE_STRENGTH:
1487 /* rk3288 is the first with per-pin drive-strength */
1488 if (!info->ctrl->drv_calc_reg)
1489 return -ENOTSUPP;
1490
1491 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1492 if (rc < 0)
1493 return rc;
1494
1495 arg = rc;
1496 break;
1497 default:
1498 return -ENOTSUPP;
1499 break;
1500 }
1501
1502 *config = pinconf_to_config_packed(param, arg);
1503
1504 return 0;
1505 }
1506
1507 static const struct pinconf_ops rockchip_pinconf_ops = {
1508 .pin_config_get = rockchip_pinconf_get,
1509 .pin_config_set = rockchip_pinconf_set,
1510 .is_generic = true,
1511 };
1512
1513 static const struct of_device_id rockchip_bank_match[] = {
1514 { .compatible = "rockchip,gpio-bank" },
1515 { .compatible = "rockchip,rk3188-gpio-bank0" },
1516 {},
1517 };
1518
1519 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1520 struct device_node *np)
1521 {
1522 struct device_node *child;
1523
1524 for_each_child_of_node(np, child) {
1525 if (of_match_node(rockchip_bank_match, child))
1526 continue;
1527
1528 info->nfunctions++;
1529 info->ngroups += of_get_child_count(child);
1530 }
1531 }
1532
1533 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1534 struct rockchip_pin_group *grp,
1535 struct rockchip_pinctrl *info,
1536 u32 index)
1537 {
1538 struct rockchip_pin_bank *bank;
1539 int size;
1540 const __be32 *list;
1541 int num;
1542 int i, j;
1543 int ret;
1544
1545 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1546
1547 /* Initialise group */
1548 grp->name = np->name;
1549
1550 /*
1551 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1552 * do sanity check and calculate pins number
1553 */
1554 list = of_get_property(np, "rockchip,pins", &size);
1555 /* we do not check return since it's safe node passed down */
1556 size /= sizeof(*list);
1557 if (!size || size % 4) {
1558 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1559 return -EINVAL;
1560 }
1561
1562 grp->npins = size / 4;
1563
1564 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1565 GFP_KERNEL);
1566 grp->data = devm_kzalloc(info->dev, grp->npins *
1567 sizeof(struct rockchip_pin_config),
1568 GFP_KERNEL);
1569 if (!grp->pins || !grp->data)
1570 return -ENOMEM;
1571
1572 for (i = 0, j = 0; i < size; i += 4, j++) {
1573 const __be32 *phandle;
1574 struct device_node *np_config;
1575
1576 num = be32_to_cpu(*list++);
1577 bank = bank_num_to_bank(info, num);
1578 if (IS_ERR(bank))
1579 return PTR_ERR(bank);
1580
1581 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1582 grp->data[j].func = be32_to_cpu(*list++);
1583
1584 phandle = list++;
1585 if (!phandle)
1586 return -EINVAL;
1587
1588 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1589 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1590 &grp->data[j].configs, &grp->data[j].nconfigs);
1591 if (ret)
1592 return ret;
1593 }
1594
1595 return 0;
1596 }
1597
1598 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1599 struct rockchip_pinctrl *info,
1600 u32 index)
1601 {
1602 struct device_node *child;
1603 struct rockchip_pmx_func *func;
1604 struct rockchip_pin_group *grp;
1605 int ret;
1606 static u32 grp_index;
1607 u32 i = 0;
1608
1609 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1610
1611 func = &info->functions[index];
1612
1613 /* Initialise function */
1614 func->name = np->name;
1615 func->ngroups = of_get_child_count(np);
1616 if (func->ngroups <= 0)
1617 return 0;
1618
1619 func->groups = devm_kzalloc(info->dev,
1620 func->ngroups * sizeof(char *), GFP_KERNEL);
1621 if (!func->groups)
1622 return -ENOMEM;
1623
1624 for_each_child_of_node(np, child) {
1625 func->groups[i] = child->name;
1626 grp = &info->groups[grp_index++];
1627 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1628 if (ret) {
1629 of_node_put(child);
1630 return ret;
1631 }
1632 }
1633
1634 return 0;
1635 }
1636
1637 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1638 struct rockchip_pinctrl *info)
1639 {
1640 struct device *dev = &pdev->dev;
1641 struct device_node *np = dev->of_node;
1642 struct device_node *child;
1643 int ret;
1644 int i;
1645
1646 rockchip_pinctrl_child_count(info, np);
1647
1648 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1649 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1650
1651 info->functions = devm_kzalloc(dev, info->nfunctions *
1652 sizeof(struct rockchip_pmx_func),
1653 GFP_KERNEL);
1654 if (!info->functions) {
1655 dev_err(dev, "failed to allocate memory for function list\n");
1656 return -EINVAL;
1657 }
1658
1659 info->groups = devm_kzalloc(dev, info->ngroups *
1660 sizeof(struct rockchip_pin_group),
1661 GFP_KERNEL);
1662 if (!info->groups) {
1663 dev_err(dev, "failed allocate memory for ping group list\n");
1664 return -EINVAL;
1665 }
1666
1667 i = 0;
1668
1669 for_each_child_of_node(np, child) {
1670 if (of_match_node(rockchip_bank_match, child))
1671 continue;
1672
1673 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1674 if (ret) {
1675 dev_err(&pdev->dev, "failed to parse function\n");
1676 of_node_put(child);
1677 return ret;
1678 }
1679 }
1680
1681 return 0;
1682 }
1683
1684 static int rockchip_pinctrl_register(struct platform_device *pdev,
1685 struct rockchip_pinctrl *info)
1686 {
1687 struct pinctrl_desc *ctrldesc = &info->pctl;
1688 struct pinctrl_pin_desc *pindesc, *pdesc;
1689 struct rockchip_pin_bank *pin_bank;
1690 int pin, bank, ret;
1691 int k;
1692
1693 ctrldesc->name = "rockchip-pinctrl";
1694 ctrldesc->owner = THIS_MODULE;
1695 ctrldesc->pctlops = &rockchip_pctrl_ops;
1696 ctrldesc->pmxops = &rockchip_pmx_ops;
1697 ctrldesc->confops = &rockchip_pinconf_ops;
1698
1699 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1700 info->ctrl->nr_pins, GFP_KERNEL);
1701 if (!pindesc) {
1702 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1703 return -ENOMEM;
1704 }
1705 ctrldesc->pins = pindesc;
1706 ctrldesc->npins = info->ctrl->nr_pins;
1707
1708 pdesc = pindesc;
1709 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1710 pin_bank = &info->ctrl->pin_banks[bank];
1711 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1712 pdesc->number = k;
1713 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1714 pin_bank->name, pin);
1715 pdesc++;
1716 }
1717 }
1718
1719 ret = rockchip_pinctrl_parse_dt(pdev, info);
1720 if (ret)
1721 return ret;
1722
1723 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1724 if (IS_ERR(info->pctl_dev)) {
1725 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1726 return PTR_ERR(info->pctl_dev);
1727 }
1728
1729 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1730 pin_bank = &info->ctrl->pin_banks[bank];
1731 pin_bank->grange.name = pin_bank->name;
1732 pin_bank->grange.id = bank;
1733 pin_bank->grange.pin_base = pin_bank->pin_base;
1734 pin_bank->grange.base = pin_bank->gpio_chip.base;
1735 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1736 pin_bank->grange.gc = &pin_bank->gpio_chip;
1737 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1738 }
1739
1740 return 0;
1741 }
1742
1743 /*
1744 * GPIO handling
1745 */
1746
1747 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1748 {
1749 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1750 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1751 unsigned long flags;
1752 u32 data;
1753
1754 clk_enable(bank->clk);
1755 spin_lock_irqsave(&bank->slock, flags);
1756
1757 data = readl(reg);
1758 data &= ~BIT(offset);
1759 if (value)
1760 data |= BIT(offset);
1761 writel(data, reg);
1762
1763 spin_unlock_irqrestore(&bank->slock, flags);
1764 clk_disable(bank->clk);
1765 }
1766
1767 /*
1768 * Returns the level of the pin for input direction and setting of the DR
1769 * register for output gpios.
1770 */
1771 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1772 {
1773 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1774 u32 data;
1775
1776 clk_enable(bank->clk);
1777 data = readl(bank->reg_base + GPIO_EXT_PORT);
1778 clk_disable(bank->clk);
1779 data >>= offset;
1780 data &= 1;
1781 return data;
1782 }
1783
1784 /*
1785 * gpiolib gpio_direction_input callback function. The setting of the pin
1786 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1787 * interface.
1788 */
1789 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1790 {
1791 return pinctrl_gpio_direction_input(gc->base + offset);
1792 }
1793
1794 /*
1795 * gpiolib gpio_direction_output callback function. The setting of the pin
1796 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1797 * interface.
1798 */
1799 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1800 unsigned offset, int value)
1801 {
1802 rockchip_gpio_set(gc, offset, value);
1803 return pinctrl_gpio_direction_output(gc->base + offset);
1804 }
1805
1806 /*
1807 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1808 * and a virtual IRQ, if not already present.
1809 */
1810 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1811 {
1812 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1813 unsigned int virq;
1814
1815 if (!bank->domain)
1816 return -ENXIO;
1817
1818 virq = irq_create_mapping(bank->domain, offset);
1819
1820 return (virq) ? : -ENXIO;
1821 }
1822
1823 static const struct gpio_chip rockchip_gpiolib_chip = {
1824 .request = gpiochip_generic_request,
1825 .free = gpiochip_generic_free,
1826 .set = rockchip_gpio_set,
1827 .get = rockchip_gpio_get,
1828 .get_direction = rockchip_gpio_get_direction,
1829 .direction_input = rockchip_gpio_direction_input,
1830 .direction_output = rockchip_gpio_direction_output,
1831 .to_irq = rockchip_gpio_to_irq,
1832 .owner = THIS_MODULE,
1833 };
1834
1835 /*
1836 * Interrupt handling
1837 */
1838
1839 static void rockchip_irq_demux(struct irq_desc *desc)
1840 {
1841 struct irq_chip *chip = irq_desc_get_chip(desc);
1842 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1843 u32 pend;
1844
1845 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1846
1847 chained_irq_enter(chip, desc);
1848
1849 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1850
1851 while (pend) {
1852 unsigned int irq, virq;
1853
1854 irq = __ffs(pend);
1855 pend &= ~BIT(irq);
1856 virq = irq_linear_revmap(bank->domain, irq);
1857
1858 if (!virq) {
1859 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1860 continue;
1861 }
1862
1863 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1864
1865 /*
1866 * Triggering IRQ on both rising and falling edge
1867 * needs manual intervention.
1868 */
1869 if (bank->toggle_edge_mode & BIT(irq)) {
1870 u32 data, data_old, polarity;
1871 unsigned long flags;
1872
1873 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1874 do {
1875 spin_lock_irqsave(&bank->slock, flags);
1876
1877 polarity = readl_relaxed(bank->reg_base +
1878 GPIO_INT_POLARITY);
1879 if (data & BIT(irq))
1880 polarity &= ~BIT(irq);
1881 else
1882 polarity |= BIT(irq);
1883 writel(polarity,
1884 bank->reg_base + GPIO_INT_POLARITY);
1885
1886 spin_unlock_irqrestore(&bank->slock, flags);
1887
1888 data_old = data;
1889 data = readl_relaxed(bank->reg_base +
1890 GPIO_EXT_PORT);
1891 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
1892 }
1893
1894 generic_handle_irq(virq);
1895 }
1896
1897 chained_irq_exit(chip, desc);
1898 }
1899
1900 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1901 {
1902 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1903 struct rockchip_pin_bank *bank = gc->private;
1904 u32 mask = BIT(d->hwirq);
1905 u32 polarity;
1906 u32 level;
1907 u32 data;
1908 unsigned long flags;
1909 int ret;
1910
1911 /* make sure the pin is configured as gpio input */
1912 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1913 if (ret < 0)
1914 return ret;
1915
1916 clk_enable(bank->clk);
1917 spin_lock_irqsave(&bank->slock, flags);
1918
1919 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1920 data &= ~mask;
1921 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1922
1923 spin_unlock_irqrestore(&bank->slock, flags);
1924
1925 if (type & IRQ_TYPE_EDGE_BOTH)
1926 irq_set_handler_locked(d, handle_edge_irq);
1927 else
1928 irq_set_handler_locked(d, handle_level_irq);
1929
1930 spin_lock_irqsave(&bank->slock, flags);
1931 irq_gc_lock(gc);
1932
1933 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1934 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1935
1936 switch (type) {
1937 case IRQ_TYPE_EDGE_BOTH:
1938 bank->toggle_edge_mode |= mask;
1939 level |= mask;
1940
1941 /*
1942 * Determine gpio state. If 1 next interrupt should be falling
1943 * otherwise rising.
1944 */
1945 data = readl(bank->reg_base + GPIO_EXT_PORT);
1946 if (data & mask)
1947 polarity &= ~mask;
1948 else
1949 polarity |= mask;
1950 break;
1951 case IRQ_TYPE_EDGE_RISING:
1952 bank->toggle_edge_mode &= ~mask;
1953 level |= mask;
1954 polarity |= mask;
1955 break;
1956 case IRQ_TYPE_EDGE_FALLING:
1957 bank->toggle_edge_mode &= ~mask;
1958 level |= mask;
1959 polarity &= ~mask;
1960 break;
1961 case IRQ_TYPE_LEVEL_HIGH:
1962 bank->toggle_edge_mode &= ~mask;
1963 level &= ~mask;
1964 polarity |= mask;
1965 break;
1966 case IRQ_TYPE_LEVEL_LOW:
1967 bank->toggle_edge_mode &= ~mask;
1968 level &= ~mask;
1969 polarity &= ~mask;
1970 break;
1971 default:
1972 irq_gc_unlock(gc);
1973 spin_unlock_irqrestore(&bank->slock, flags);
1974 clk_disable(bank->clk);
1975 return -EINVAL;
1976 }
1977
1978 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1979 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1980
1981 irq_gc_unlock(gc);
1982 spin_unlock_irqrestore(&bank->slock, flags);
1983 clk_disable(bank->clk);
1984
1985 return 0;
1986 }
1987
1988 static void rockchip_irq_suspend(struct irq_data *d)
1989 {
1990 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1991 struct rockchip_pin_bank *bank = gc->private;
1992
1993 clk_enable(bank->clk);
1994 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1995 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1996 clk_disable(bank->clk);
1997 }
1998
1999 static void rockchip_irq_resume(struct irq_data *d)
2000 {
2001 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2002 struct rockchip_pin_bank *bank = gc->private;
2003
2004 clk_enable(bank->clk);
2005 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2006 clk_disable(bank->clk);
2007 }
2008
2009 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2010 {
2011 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2012 struct rockchip_pin_bank *bank = gc->private;
2013
2014 clk_enable(bank->clk);
2015 irq_gc_mask_clr_bit(d);
2016 }
2017
2018 static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2019 {
2020 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2021 struct rockchip_pin_bank *bank = gc->private;
2022
2023 irq_gc_mask_set_bit(d);
2024 clk_disable(bank->clk);
2025 }
2026
2027 static int rockchip_interrupts_register(struct platform_device *pdev,
2028 struct rockchip_pinctrl *info)
2029 {
2030 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2031 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2032 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2033 struct irq_chip_generic *gc;
2034 int ret;
2035 int i, j;
2036
2037 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2038 if (!bank->valid) {
2039 dev_warn(&pdev->dev, "bank %s is not valid\n",
2040 bank->name);
2041 continue;
2042 }
2043
2044 ret = clk_enable(bank->clk);
2045 if (ret) {
2046 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2047 bank->name);
2048 continue;
2049 }
2050
2051 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2052 &irq_generic_chip_ops, NULL);
2053 if (!bank->domain) {
2054 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2055 bank->name);
2056 clk_disable(bank->clk);
2057 continue;
2058 }
2059
2060 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2061 "rockchip_gpio_irq", handle_level_irq,
2062 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2063 if (ret) {
2064 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2065 bank->name);
2066 irq_domain_remove(bank->domain);
2067 clk_disable(bank->clk);
2068 continue;
2069 }
2070
2071 /*
2072 * Linux assumes that all interrupts start out disabled/masked.
2073 * Our driver only uses the concept of masked and always keeps
2074 * things enabled, so for us that's all masked and all enabled.
2075 */
2076 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2077 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2078
2079 gc = irq_get_domain_generic_chip(bank->domain, 0);
2080 gc->reg_base = bank->reg_base;
2081 gc->private = bank;
2082 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2083 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2084 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2085 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2086 gc->chip_types[0].chip.irq_unmask =
2087 rockchip_irq_gc_mask_clr_bit;
2088 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2089 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2090 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2091 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2092 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2093
2094 irq_set_chained_handler_and_data(bank->irq,
2095 rockchip_irq_demux, bank);
2096
2097 /* map the gpio irqs here, when the clock is still running */
2098 for (j = 0 ; j < 32 ; j++)
2099 irq_create_mapping(bank->domain, j);
2100
2101 clk_disable(bank->clk);
2102 }
2103
2104 return 0;
2105 }
2106
2107 static int rockchip_gpiolib_register(struct platform_device *pdev,
2108 struct rockchip_pinctrl *info)
2109 {
2110 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2111 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2112 struct gpio_chip *gc;
2113 int ret;
2114 int i;
2115
2116 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2117 if (!bank->valid) {
2118 dev_warn(&pdev->dev, "bank %s is not valid\n",
2119 bank->name);
2120 continue;
2121 }
2122
2123 bank->gpio_chip = rockchip_gpiolib_chip;
2124
2125 gc = &bank->gpio_chip;
2126 gc->base = bank->pin_base;
2127 gc->ngpio = bank->nr_pins;
2128 gc->parent = &pdev->dev;
2129 gc->of_node = bank->of_node;
2130 gc->label = bank->name;
2131
2132 ret = gpiochip_add_data(gc, bank);
2133 if (ret) {
2134 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2135 gc->label, ret);
2136 goto fail;
2137 }
2138 }
2139
2140 rockchip_interrupts_register(pdev, info);
2141
2142 return 0;
2143
2144 fail:
2145 for (--i, --bank; i >= 0; --i, --bank) {
2146 if (!bank->valid)
2147 continue;
2148 gpiochip_remove(&bank->gpio_chip);
2149 }
2150 return ret;
2151 }
2152
2153 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2154 struct rockchip_pinctrl *info)
2155 {
2156 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2157 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2158 int i;
2159
2160 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2161 if (!bank->valid)
2162 continue;
2163 gpiochip_remove(&bank->gpio_chip);
2164 }
2165
2166 return 0;
2167 }
2168
2169 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2170 struct rockchip_pinctrl *info)
2171 {
2172 struct resource res;
2173 void __iomem *base;
2174
2175 if (of_address_to_resource(bank->of_node, 0, &res)) {
2176 dev_err(info->dev, "cannot find IO resource for bank\n");
2177 return -ENOENT;
2178 }
2179
2180 bank->reg_base = devm_ioremap_resource(info->dev, &res);
2181 if (IS_ERR(bank->reg_base))
2182 return PTR_ERR(bank->reg_base);
2183
2184 /*
2185 * special case, where parts of the pull setting-registers are
2186 * part of the PMU register space
2187 */
2188 if (of_device_is_compatible(bank->of_node,
2189 "rockchip,rk3188-gpio-bank0")) {
2190 struct device_node *node;
2191
2192 node = of_parse_phandle(bank->of_node->parent,
2193 "rockchip,pmu", 0);
2194 if (!node) {
2195 if (of_address_to_resource(bank->of_node, 1, &res)) {
2196 dev_err(info->dev, "cannot find IO resource for bank\n");
2197 return -ENOENT;
2198 }
2199
2200 base = devm_ioremap_resource(info->dev, &res);
2201 if (IS_ERR(base))
2202 return PTR_ERR(base);
2203 rockchip_regmap_config.max_register =
2204 resource_size(&res) - 4;
2205 rockchip_regmap_config.name =
2206 "rockchip,rk3188-gpio-bank0-pull";
2207 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2208 base,
2209 &rockchip_regmap_config);
2210 }
2211 }
2212
2213 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2214
2215 bank->clk = of_clk_get(bank->of_node, 0);
2216 if (IS_ERR(bank->clk))
2217 return PTR_ERR(bank->clk);
2218
2219 return clk_prepare(bank->clk);
2220 }
2221
2222 static const struct of_device_id rockchip_pinctrl_dt_match[];
2223
2224 /* retrieve the soc specific data */
2225 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2226 struct rockchip_pinctrl *d,
2227 struct platform_device *pdev)
2228 {
2229 const struct of_device_id *match;
2230 struct device_node *node = pdev->dev.of_node;
2231 struct device_node *np;
2232 struct rockchip_pin_ctrl *ctrl;
2233 struct rockchip_pin_bank *bank;
2234 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2235
2236 match = of_match_node(rockchip_pinctrl_dt_match, node);
2237 ctrl = (struct rockchip_pin_ctrl *)match->data;
2238
2239 for_each_child_of_node(node, np) {
2240 if (!of_find_property(np, "gpio-controller", NULL))
2241 continue;
2242
2243 bank = ctrl->pin_banks;
2244 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2245 if (!strcmp(bank->name, np->name)) {
2246 bank->of_node = np;
2247
2248 if (!rockchip_get_bank_data(bank, d))
2249 bank->valid = true;
2250
2251 break;
2252 }
2253 }
2254 }
2255
2256 grf_offs = ctrl->grf_mux_offset;
2257 pmu_offs = ctrl->pmu_mux_offset;
2258 drv_pmu_offs = ctrl->pmu_drv_offset;
2259 drv_grf_offs = ctrl->grf_drv_offset;
2260 bank = ctrl->pin_banks;
2261 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2262 int bank_pins = 0;
2263
2264 spin_lock_init(&bank->slock);
2265 bank->drvdata = d;
2266 bank->pin_base = ctrl->nr_pins;
2267 ctrl->nr_pins += bank->nr_pins;
2268
2269 /* calculate iomux and drv offsets */
2270 for (j = 0; j < 4; j++) {
2271 struct rockchip_iomux *iom = &bank->iomux[j];
2272 struct rockchip_drv *drv = &bank->drv[j];
2273 int inc;
2274
2275 if (bank_pins >= bank->nr_pins)
2276 break;
2277
2278 /* preset iomux offset value, set new start value */
2279 if (iom->offset >= 0) {
2280 if (iom->type & IOMUX_SOURCE_PMU)
2281 pmu_offs = iom->offset;
2282 else
2283 grf_offs = iom->offset;
2284 } else { /* set current iomux offset */
2285 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2286 pmu_offs : grf_offs;
2287 }
2288
2289 /* preset drv offset value, set new start value */
2290 if (drv->offset >= 0) {
2291 if (iom->type & IOMUX_SOURCE_PMU)
2292 drv_pmu_offs = drv->offset;
2293 else
2294 drv_grf_offs = drv->offset;
2295 } else { /* set current drv offset */
2296 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2297 drv_pmu_offs : drv_grf_offs;
2298 }
2299
2300 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2301 i, j, iom->offset, drv->offset);
2302
2303 /*
2304 * Increase offset according to iomux width.
2305 * 4bit iomux'es are spread over two registers.
2306 */
2307 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
2308 if (iom->type & IOMUX_SOURCE_PMU)
2309 pmu_offs += inc;
2310 else
2311 grf_offs += inc;
2312
2313 /*
2314 * Increase offset according to drv width.
2315 * 3bit drive-strenth'es are spread over two registers.
2316 */
2317 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2318 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2319 inc = 8;
2320 else
2321 inc = 4;
2322
2323 if (iom->type & IOMUX_SOURCE_PMU)
2324 drv_pmu_offs += inc;
2325 else
2326 drv_grf_offs += inc;
2327
2328 bank_pins += 8;
2329 }
2330 }
2331
2332 return ctrl;
2333 }
2334
2335 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2336 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2337
2338 static u32 rk3288_grf_gpio6c_iomux;
2339
2340 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2341 {
2342 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2343 int ret = pinctrl_force_sleep(info->pctl_dev);
2344
2345 if (ret)
2346 return ret;
2347
2348 /*
2349 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2350 * the setting here, and restore it at resume.
2351 */
2352 if (info->ctrl->type == RK3288) {
2353 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2354 &rk3288_grf_gpio6c_iomux);
2355 if (ret) {
2356 pinctrl_force_default(info->pctl_dev);
2357 return ret;
2358 }
2359 }
2360
2361 return 0;
2362 }
2363
2364 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2365 {
2366 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2367 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2368 rk3288_grf_gpio6c_iomux |
2369 GPIO6C6_SEL_WRITE_ENABLE);
2370
2371 if (ret)
2372 return ret;
2373
2374 return pinctrl_force_default(info->pctl_dev);
2375 }
2376
2377 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2378 rockchip_pinctrl_resume);
2379
2380 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2381 {
2382 struct rockchip_pinctrl *info;
2383 struct device *dev = &pdev->dev;
2384 struct rockchip_pin_ctrl *ctrl;
2385 struct device_node *np = pdev->dev.of_node, *node;
2386 struct resource *res;
2387 void __iomem *base;
2388 int ret;
2389
2390 if (!dev->of_node) {
2391 dev_err(dev, "device tree node not found\n");
2392 return -ENODEV;
2393 }
2394
2395 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2396 if (!info)
2397 return -ENOMEM;
2398
2399 info->dev = dev;
2400
2401 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2402 if (!ctrl) {
2403 dev_err(dev, "driver data not available\n");
2404 return -EINVAL;
2405 }
2406 info->ctrl = ctrl;
2407
2408 node = of_parse_phandle(np, "rockchip,grf", 0);
2409 if (node) {
2410 info->regmap_base = syscon_node_to_regmap(node);
2411 if (IS_ERR(info->regmap_base))
2412 return PTR_ERR(info->regmap_base);
2413 } else {
2414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2415 base = devm_ioremap_resource(&pdev->dev, res);
2416 if (IS_ERR(base))
2417 return PTR_ERR(base);
2418
2419 rockchip_regmap_config.max_register = resource_size(res) - 4;
2420 rockchip_regmap_config.name = "rockchip,pinctrl";
2421 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2422 &rockchip_regmap_config);
2423
2424 /* to check for the old dt-bindings */
2425 info->reg_size = resource_size(res);
2426
2427 /* Honor the old binding, with pull registers as 2nd resource */
2428 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2429 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2430 base = devm_ioremap_resource(&pdev->dev, res);
2431 if (IS_ERR(base))
2432 return PTR_ERR(base);
2433
2434 rockchip_regmap_config.max_register =
2435 resource_size(res) - 4;
2436 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2437 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2438 base,
2439 &rockchip_regmap_config);
2440 }
2441 }
2442
2443 /* try to find the optional reference to the pmu syscon */
2444 node = of_parse_phandle(np, "rockchip,pmu", 0);
2445 if (node) {
2446 info->regmap_pmu = syscon_node_to_regmap(node);
2447 if (IS_ERR(info->regmap_pmu))
2448 return PTR_ERR(info->regmap_pmu);
2449 }
2450
2451 ret = rockchip_gpiolib_register(pdev, info);
2452 if (ret)
2453 return ret;
2454
2455 ret = rockchip_pinctrl_register(pdev, info);
2456 if (ret) {
2457 rockchip_gpiolib_unregister(pdev, info);
2458 return ret;
2459 }
2460
2461 platform_set_drvdata(pdev, info);
2462
2463 return 0;
2464 }
2465
2466 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2467 PIN_BANK(0, 32, "gpio0"),
2468 PIN_BANK(1, 32, "gpio1"),
2469 PIN_BANK(2, 32, "gpio2"),
2470 PIN_BANK(3, 32, "gpio3"),
2471 };
2472
2473 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2474 .pin_banks = rk2928_pin_banks,
2475 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2476 .label = "RK2928-GPIO",
2477 .type = RK2928,
2478 .grf_mux_offset = 0xa8,
2479 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2480 };
2481
2482 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2483 PIN_BANK(0, 32, "gpio0"),
2484 PIN_BANK(1, 32, "gpio1"),
2485 PIN_BANK(2, 32, "gpio2"),
2486 };
2487
2488 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2489 .pin_banks = rk3036_pin_banks,
2490 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2491 .label = "RK3036-GPIO",
2492 .type = RK2928,
2493 .grf_mux_offset = 0xa8,
2494 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2495 };
2496
2497 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2498 PIN_BANK(0, 32, "gpio0"),
2499 PIN_BANK(1, 32, "gpio1"),
2500 PIN_BANK(2, 32, "gpio2"),
2501 PIN_BANK(3, 32, "gpio3"),
2502 PIN_BANK(4, 32, "gpio4"),
2503 PIN_BANK(6, 16, "gpio6"),
2504 };
2505
2506 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2507 .pin_banks = rk3066a_pin_banks,
2508 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2509 .label = "RK3066a-GPIO",
2510 .type = RK2928,
2511 .grf_mux_offset = 0xa8,
2512 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2513 };
2514
2515 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2516 PIN_BANK(0, 32, "gpio0"),
2517 PIN_BANK(1, 32, "gpio1"),
2518 PIN_BANK(2, 32, "gpio2"),
2519 PIN_BANK(3, 32, "gpio3"),
2520 };
2521
2522 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2523 .pin_banks = rk3066b_pin_banks,
2524 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2525 .label = "RK3066b-GPIO",
2526 .type = RK3066B,
2527 .grf_mux_offset = 0x60,
2528 };
2529
2530 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2531 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2532 PIN_BANK(1, 32, "gpio1"),
2533 PIN_BANK(2, 32, "gpio2"),
2534 PIN_BANK(3, 32, "gpio3"),
2535 };
2536
2537 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2538 .pin_banks = rk3188_pin_banks,
2539 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2540 .label = "RK3188-GPIO",
2541 .type = RK3188,
2542 .grf_mux_offset = 0x60,
2543 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2544 };
2545
2546 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2547 PIN_BANK(0, 32, "gpio0"),
2548 PIN_BANK(1, 32, "gpio1"),
2549 PIN_BANK(2, 32, "gpio2"),
2550 PIN_BANK(3, 32, "gpio3"),
2551 };
2552
2553 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2554 .pin_banks = rk3228_pin_banks,
2555 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2556 .label = "RK3228-GPIO",
2557 .type = RK3288,
2558 .grf_mux_offset = 0x0,
2559 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2560 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2561 };
2562
2563 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2564 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2565 IOMUX_SOURCE_PMU,
2566 IOMUX_SOURCE_PMU,
2567 IOMUX_UNROUTED
2568 ),
2569 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2570 IOMUX_UNROUTED,
2571 IOMUX_UNROUTED,
2572 0
2573 ),
2574 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2575 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2576 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2577 IOMUX_WIDTH_4BIT,
2578 0,
2579 0
2580 ),
2581 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2582 0,
2583 0,
2584 IOMUX_UNROUTED
2585 ),
2586 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2587 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2588 0,
2589 IOMUX_WIDTH_4BIT,
2590 IOMUX_UNROUTED
2591 ),
2592 PIN_BANK(8, 16, "gpio8"),
2593 };
2594
2595 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2596 .pin_banks = rk3288_pin_banks,
2597 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2598 .label = "RK3288-GPIO",
2599 .type = RK3288,
2600 .grf_mux_offset = 0x0,
2601 .pmu_mux_offset = 0x84,
2602 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2603 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
2604 };
2605
2606 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2607 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2608 IOMUX_SOURCE_PMU,
2609 IOMUX_SOURCE_PMU,
2610 IOMUX_SOURCE_PMU
2611 ),
2612 PIN_BANK(1, 32, "gpio1"),
2613 PIN_BANK(2, 32, "gpio2"),
2614 PIN_BANK(3, 32, "gpio3"),
2615 };
2616
2617 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2618 .pin_banks = rk3368_pin_banks,
2619 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2620 .label = "RK3368-GPIO",
2621 .type = RK3368,
2622 .grf_mux_offset = 0x0,
2623 .pmu_mux_offset = 0x0,
2624 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2625 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2626 };
2627
2628 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2629 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2630 IOMUX_SOURCE_PMU,
2631 IOMUX_SOURCE_PMU,
2632 IOMUX_SOURCE_PMU,
2633 IOMUX_SOURCE_PMU,
2634 DRV_TYPE_IO_1V8_ONLY,
2635 DRV_TYPE_IO_1V8_ONLY,
2636 DRV_TYPE_IO_DEFAULT,
2637 DRV_TYPE_IO_DEFAULT,
2638 0x0,
2639 0x8,
2640 -1,
2641 -1,
2642 PULL_TYPE_IO_1V8_ONLY,
2643 PULL_TYPE_IO_1V8_ONLY,
2644 PULL_TYPE_IO_DEFAULT,
2645 PULL_TYPE_IO_DEFAULT
2646 ),
2647 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2648 IOMUX_SOURCE_PMU,
2649 IOMUX_SOURCE_PMU,
2650 IOMUX_SOURCE_PMU,
2651 DRV_TYPE_IO_1V8_OR_3V0,
2652 DRV_TYPE_IO_1V8_OR_3V0,
2653 DRV_TYPE_IO_1V8_OR_3V0,
2654 DRV_TYPE_IO_1V8_OR_3V0,
2655 0x20,
2656 0x28,
2657 0x30,
2658 0x38
2659 ),
2660 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2661 DRV_TYPE_IO_1V8_OR_3V0,
2662 DRV_TYPE_IO_1V8_ONLY,
2663 DRV_TYPE_IO_1V8_ONLY,
2664 PULL_TYPE_IO_DEFAULT,
2665 PULL_TYPE_IO_DEFAULT,
2666 PULL_TYPE_IO_1V8_ONLY,
2667 PULL_TYPE_IO_1V8_ONLY
2668 ),
2669 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2670 DRV_TYPE_IO_3V3_ONLY,
2671 DRV_TYPE_IO_3V3_ONLY,
2672 DRV_TYPE_IO_1V8_OR_3V0
2673 ),
2674 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2675 DRV_TYPE_IO_1V8_3V0_AUTO,
2676 DRV_TYPE_IO_1V8_OR_3V0,
2677 DRV_TYPE_IO_1V8_OR_3V0
2678 ),
2679 };
2680
2681 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2682 .pin_banks = rk3399_pin_banks,
2683 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2684 .label = "RK3399-GPIO",
2685 .type = RK3399,
2686 .grf_mux_offset = 0xe000,
2687 .pmu_mux_offset = 0x0,
2688 .grf_drv_offset = 0xe100,
2689 .pmu_drv_offset = 0x80,
2690 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2691 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2692 };
2693
2694 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2695 { .compatible = "rockchip,rk2928-pinctrl",
2696 .data = (void *)&rk2928_pin_ctrl },
2697 { .compatible = "rockchip,rk3036-pinctrl",
2698 .data = (void *)&rk3036_pin_ctrl },
2699 { .compatible = "rockchip,rk3066a-pinctrl",
2700 .data = (void *)&rk3066a_pin_ctrl },
2701 { .compatible = "rockchip,rk3066b-pinctrl",
2702 .data = (void *)&rk3066b_pin_ctrl },
2703 { .compatible = "rockchip,rk3188-pinctrl",
2704 .data = (void *)&rk3188_pin_ctrl },
2705 { .compatible = "rockchip,rk3228-pinctrl",
2706 .data = (void *)&rk3228_pin_ctrl },
2707 { .compatible = "rockchip,rk3288-pinctrl",
2708 .data = (void *)&rk3288_pin_ctrl },
2709 { .compatible = "rockchip,rk3368-pinctrl",
2710 .data = (void *)&rk3368_pin_ctrl },
2711 { .compatible = "rockchip,rk3399-pinctrl",
2712 .data = (void *)&rk3399_pin_ctrl },
2713 {},
2714 };
2715
2716 static struct platform_driver rockchip_pinctrl_driver = {
2717 .probe = rockchip_pinctrl_probe,
2718 .driver = {
2719 .name = "rockchip-pinctrl",
2720 .pm = &rockchip_pinctrl_dev_pm_ops,
2721 .of_match_table = rockchip_pinctrl_dt_match,
2722 },
2723 };
2724
2725 static int __init rockchip_pinctrl_drv_register(void)
2726 {
2727 return platform_driver_register(&rockchip_pinctrl_driver);
2728 }
2729 postcore_initcall(rockchip_pinctrl_drv_register);
Linux with added FPC-III support