drivers/pinctrl/sh-pfc/core.c

   1 /*
   2  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #define DRV_NAME "sh-pfc"
  15
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/errno.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28
  29 #include "core.h"
  30
  31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  32                                 struct platform_device *pdev)
  33 {
  34         unsigned int num_windows, num_irqs;
  35         struct sh_pfc_window *windows;
  36         unsigned int *irqs = NULL;
  37         struct resource *res;
  38         unsigned int i;
  39         int irq;
  40
  41         /* Count the MEM and IRQ resources. */
  42         for (num_windows = 0;; num_windows++) {
  43                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  44                 if (!res)
  45                         break;
  46         }
  47         for (num_irqs = 0;; num_irqs++) {
  48                 irq = platform_get_irq(pdev, num_irqs);
  49                 if (irq == -EPROBE_DEFER)
  50                         return irq;
  51                 if (irq < 0)
  52                         break;
  53         }
  54
  55         if (num_windows == 0)
  56                 return -EINVAL;
  57
  58         /* Allocate memory windows and IRQs arrays. */
  59         windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
  60                                GFP_KERNEL);
  61         if (windows == NULL)
  62                 return -ENOMEM;
  63
  64         pfc->num_windows = num_windows;
  65         pfc->windows = windows;
  66
  67         if (num_irqs) {
  68                 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
  69                                     GFP_KERNEL);
  70                 if (irqs == NULL)
  71                         return -ENOMEM;
  72
  73                 pfc->num_irqs = num_irqs;
  74                 pfc->irqs = irqs;
  75         }
  76
  77         /* Fill them. */
  78         for (i = 0; i < num_windows; i++) {
  79                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  80                 windows->phys = res->start;
  81                 windows->size = resource_size(res);
  82                 windows->virt = devm_ioremap_resource(pfc->dev, res);
  83                 if (IS_ERR(windows->virt))
  84                         return -ENOMEM;
  85                 windows++;
  86         }
  87         for (i = 0; i < num_irqs; i++)
  88                 *irqs++ = platform_get_irq(pdev, i);
  89
  90         return 0;
  91 }
  92
  93 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  94 {
  95         struct sh_pfc_window *window;
  96         phys_addr_t address = reg;
  97         unsigned int i;
  98
  99         /* scan through physical windows and convert address */
 100         for (i = 0; i < pfc->num_windows; i++) {
 101                 window = pfc->windows + i;
 102
 103                 if (address < window->phys)
 104                         continue;
 105
 106                 if (address >= (window->phys + window->size))
 107                         continue;
 108
 109                 return window->virt + (address - window->phys);
 110         }
 111
 112         BUG();
 113         return NULL;
 114 }
 115
 116 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 117 {
 118         unsigned int offset;
 119         unsigned int i;
 120
 121         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 122                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 123
 124                 if (pin <= range->end)
 125                         return pin >= range->start
 126                              ? offset + pin - range->start : -1;
 127
 128                 offset += range->end - range->start + 1;
 129         }
 130
 131         return -EINVAL;
 132 }
 133
 134 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 135 {
 136         if (enum_id < r->begin)
 137                 return 0;
 138
 139         if (enum_id > r->end)
 140                 return 0;
 141
 142         return 1;
 143 }
 144
 145 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 146 {
 147         switch (reg_width) {
 148         case 8:
 149                 return ioread8(mapped_reg);
 150         case 16:
 151                 return ioread16(mapped_reg);
 152         case 32:
 153                 return ioread32(mapped_reg);
 154         }
 155
 156         BUG();
 157         return 0;
 158 }
 159
 160 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 161                           u32 data)
 162 {
 163         switch (reg_width) {
 164         case 8:
 165                 iowrite8(data, mapped_reg);
 166                 return;
 167         case 16:
 168                 iowrite16(data, mapped_reg);
 169                 return;
 170         case 32:
 171                 iowrite32(data, mapped_reg);
 172                 return;
 173         }
 174
 175         BUG();
 176 }
 177
 178 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 179 {
 180         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);
 181 }
 182
 183 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 184 {
 185         if (pfc->info->unlock_reg)
 186                 sh_pfc_write_raw_reg(
 187                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 188                         ~data);
 189
 190         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);
 191 }
 192
 193 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 194                                      const struct pinmux_cfg_reg *crp,
 195                                      unsigned int in_pos,
 196                                      void __iomem **mapped_regp, u32 *maskp,
 197                                      unsigned int *posp)
 198 {
 199         unsigned int k;
 200
 201         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 202
 203         if (crp->field_width) {
 204                 *maskp = (1 << crp->field_width) - 1;
 205                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 206         } else {
 207                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 208                 *posp = crp->reg_width;
 209                 for (k = 0; k <= in_pos; k++)
 210                         *posp -= crp->var_field_width[k];
 211         }
 212 }
 213
 214 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 215                                     const struct pinmux_cfg_reg *crp,
 216                                     unsigned int field, u32 value)
 217 {
 218         void __iomem *mapped_reg;
 219         unsigned int pos;
 220         u32 mask, data;
 221
 222         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 223
 224         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 225                 "r_width = %u, f_width = %u\n",
 226                 crp->reg, value, field, crp->reg_width, crp->field_width);
 227
 228         mask = ~(mask << pos);
 229         value = value << pos;
 230
 231         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 232         data &= mask;
 233         data |= value;
 234
 235         if (pfc->info->unlock_reg)
 236                 sh_pfc_write_raw_reg(
 237                         sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
 238                         ~data);
 239
 240         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 241 }
 242
 243 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 244                                  const struct pinmux_cfg_reg **crp,
 245                                  unsigned int *fieldp, u32 *valuep)
 246 {
 247         unsigned int k = 0;
 248
 249         while (1) {
 250                 const struct pinmux_cfg_reg *config_reg =
 251                         pfc->info->cfg_regs + k;
 252                 unsigned int r_width = config_reg->reg_width;
 253                 unsigned int f_width = config_reg->field_width;
 254                 unsigned int curr_width;
 255                 unsigned int bit_pos;
 256                 unsigned int pos = 0;
 257                 unsigned int m = 0;
 258
 259                 if (!r_width)
 260                         break;
 261
 262                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 263                         u32 ncomb;
 264                         u32 n;
 265
 266                         if (f_width)
 267                                 curr_width = f_width;
 268                         else
 269                                 curr_width = config_reg->var_field_width[m];
 270
 271                         ncomb = 1 << curr_width;
 272                         for (n = 0; n < ncomb; n++) {
 273                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 274                                         *crp = config_reg;
 275                                         *fieldp = m;
 276                                         *valuep = n;
 277                                         return 0;
 278                                 }
 279                         }
 280                         pos += ncomb;
 281                         m++;
 282                 }
 283                 k++;
 284         }
 285
 286         return -EINVAL;
 287 }
 288
 289 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 290                               u16 *enum_idp)
 291 {
 292         const u16 *data = pfc->info->pinmux_data;
 293         unsigned int k;
 294
 295         if (pos) {
 296                 *enum_idp = data[pos + 1];
 297                 return pos + 1;
 298         }
 299
 300         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 301                 if (data[k] == mark) {
 302                         *enum_idp = data[k + 1];
 303                         return k + 1;
 304                 }
 305         }
 306
 307         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 308                 mark);
 309         return -EINVAL;
 310 }
 311
 312 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 313 {
 314         const struct pinmux_range *range;
 315         int pos = 0;
 316
 317         switch (pinmux_type) {
 318         case PINMUX_TYPE_GPIO:
 319         case PINMUX_TYPE_FUNCTION:
 320                 range = NULL;
 321                 break;
 322
 323         case PINMUX_TYPE_OUTPUT:
 324                 range = &pfc->info->output;
 325                 break;
 326
 327         case PINMUX_TYPE_INPUT:
 328                 range = &pfc->info->input;
 329                 break;
 330
 331         default:
 332                 return -EINVAL;
 333         }
 334
 335         /* Iterate over all the configuration fields we need to update. */
 336         while (1) {
 337                 const struct pinmux_cfg_reg *cr;
 338                 unsigned int field;
 339                 u16 enum_id;
 340                 u32 value;
 341                 int in_range;
 342                 int ret;
 343
 344                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 345                 if (pos < 0)
 346                         return pos;
 347
 348                 if (!enum_id)
 349                         break;
 350
 351                 /* Check if the configuration field selects a function. If it
 352                  * doesn't, skip the field if it's not applicable to the
 353                  * requested pinmux type.
 354                  */
 355                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 356                 if (!in_range) {
 357                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 358                                 /* Functions are allowed to modify all
 359                                  * fields.
 360                                  */
 361                                 in_range = 1;
 362                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 363                                 /* Input/output types can only modify fields
 364                                  * that correspond to their respective ranges.
 365                                  */
 366                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 367
 368                                 /*
 369                                  * special case pass through for fixed
 370                                  * input-only or output-only pins without
 371                                  * function enum register association.
 372                                  */
 373                                 if (in_range && enum_id == range->force)
 374                                         continue;
 375                         }
 376                         /* GPIOs are only allowed to modify function fields. */
 377                 }
 378
 379                 if (!in_range)
 380                         continue;
 381
 382                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 383                 if (ret < 0)
 384                         return ret;
 385
 386                 sh_pfc_write_config_reg(pfc, cr, field, value);
 387         }
 388
 389         return 0;
 390 }
 391
 392 const struct sh_pfc_bias_info *
 393 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 394                         unsigned int num, unsigned int pin)
 395 {
 396         unsigned int i;
 397
 398         for (i = 0; i < num; i++)
 399                 if (info[i].pin == pin)
 400                         return &info[i];
 401
 402         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 403
 404         return NULL;
 405 }
 406
 407 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 408 {
 409         struct sh_pfc_pin_range *range;
 410         unsigned int nr_ranges;
 411         unsigned int i;
 412
 413         if (pfc->info->pins[0].pin == (u16)-1) {
 414                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 415                  * in its pin arrays yet. Consider the pin numbers range as
 416                  * continuous and allocate a single range.
 417                  */
 418                 pfc->nr_ranges = 1;
 419                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 420                                            GFP_KERNEL);
 421                 if (pfc->ranges == NULL)
 422                         return -ENOMEM;
 423
 424                 pfc->ranges->start = 0;
 425                 pfc->ranges->end = pfc->info->nr_pins - 1;
 426                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 427
 428                 return 0;
 429         }
 430
 431         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 432          * be sorted by pin numbers, and pins without a GPIO port must come
 433          * last.
 434          */
 435         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 436                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 437                         nr_ranges++;
 438         }
 439
 440         pfc->nr_ranges = nr_ranges;
 441         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
 442                                    GFP_KERNEL);
 443         if (pfc->ranges == NULL)
 444                 return -ENOMEM;
 445
 446         range = pfc->ranges;
 447         range->start = pfc->info->pins[0].pin;
 448
 449         for (i = 1; i < pfc->info->nr_pins; ++i) {
 450                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 451                         continue;
 452
 453                 range->end = pfc->info->pins[i-1].pin;
 454                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 455                         pfc->nr_gpio_pins = range->end + 1;
 456
 457                 range++;
 458                 range->start = pfc->info->pins[i].pin;
 459         }
 460
 461         range->end = pfc->info->pins[i-1].pin;
 462         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 463                 pfc->nr_gpio_pins = range->end + 1;
 464
 465         return 0;
 466 }
 467
 468 #ifdef CONFIG_OF
 469 static const struct of_device_id sh_pfc_of_table[] = {
 470 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 471         {
 472                 .compatible = "renesas,pfc-emev2",
 473                 .data = &emev2_pinmux_info,
 474         },
 475 #endif
 476 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 477         {
 478                 .compatible = "renesas,pfc-r8a73a4",
 479                 .data = &r8a73a4_pinmux_info,
 480         },
 481 #endif
 482 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 483         {
 484                 .compatible = "renesas,pfc-r8a7740",
 485                 .data = &r8a7740_pinmux_info,
 486         },
 487 #endif
 488 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 489         {
 490                 .compatible = "renesas,pfc-r8a7778",
 491                 .data = &r8a7778_pinmux_info,
 492         },
 493 #endif
 494 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 495         {
 496                 .compatible = "renesas,pfc-r8a7779",
 497                 .data = &r8a7779_pinmux_info,
 498         },
 499 #endif
 500 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 501         {
 502                 .compatible = "renesas,pfc-r8a7790",
 503                 .data = &r8a7790_pinmux_info,
 504         },
 505 #endif
 506 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 507         {
 508                 .compatible = "renesas,pfc-r8a7791",
 509                 .data = &r8a7791_pinmux_info,
 510         },
 511 #endif
 512 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 513         {
 514                 .compatible = "renesas,pfc-r8a7792",
 515                 .data = &r8a7792_pinmux_info,
 516         },
 517 #endif
 518 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 519         {
 520                 .compatible = "renesas,pfc-r8a7793",
 521                 .data = &r8a7793_pinmux_info,
 522         },
 523 #endif
 524 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 525         {
 526                 .compatible = "renesas,pfc-r8a7794",
 527                 .data = &r8a7794_pinmux_info,
 528         },
 529 #endif
 530 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 531         {
 532                 .compatible = "renesas,pfc-r8a7795",
 533                 .data = &r8a7795_pinmux_info,
 534         },
 535 #endif
 536 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 537         {
 538                 .compatible = "renesas,pfc-r8a7796",
 539                 .data = &r8a7796_pinmux_info,
 540         },
 541 #endif
 542 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 543         {
 544                 .compatible = "renesas,pfc-sh73a0",
 545                 .data = &sh73a0_pinmux_info,
 546         },
 547 #endif
 548         { },
 549 };
 550 #endif
 551
 552 static int sh_pfc_probe(struct platform_device *pdev)
 553 {
 554         const struct platform_device_id *platid = platform_get_device_id(pdev);
 555 #ifdef CONFIG_OF
 556         struct device_node *np = pdev->dev.of_node;
 557 #endif
 558         const struct sh_pfc_soc_info *info;
 559         struct sh_pfc *pfc;
 560         int ret;
 561
 562 #ifdef CONFIG_OF
 563         if (np)
 564                 info = of_device_get_match_data(&pdev->dev);
 565         else
 566 #endif
 567                 info = platid ? (const void *)platid->driver_data : NULL;
 568
 569         if (info == NULL)
 570                 return -ENODEV;
 571
 572         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
 573         if (pfc == NULL)
 574                 return -ENOMEM;
 575
 576         pfc->info = info;
 577         pfc->dev = &pdev->dev;
 578
 579         ret = sh_pfc_map_resources(pfc, pdev);
 580         if (unlikely(ret < 0))
 581                 return ret;
 582
 583         spin_lock_init(&pfc->lock);
 584
 585         if (info->ops && info->ops->init) {
 586                 ret = info->ops->init(pfc);
 587                 if (ret < 0)
 588                         return ret;
 589
 590                 /* .init() may have overridden pfc->info */
 591                 info = pfc->info;
 592         }
 593
 594         /* Enable dummy states for those platforms without pinctrl support */
 595         if (!of_have_populated_dt())
 596                 pinctrl_provide_dummies();
 597
 598         ret = sh_pfc_init_ranges(pfc);
 599         if (ret < 0)
 600                 return ret;
 601
 602         /*
 603          * Initialize pinctrl bindings first
 604          */
 605         ret = sh_pfc_register_pinctrl(pfc);
 606         if (unlikely(ret != 0))
 607                 return ret;
 608
 609 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 610         /*
 611          * Then the GPIO chip
 612          */
 613         ret = sh_pfc_register_gpiochip(pfc);
 614         if (unlikely(ret != 0)) {
 615                 /*
 616                  * If the GPIO chip fails to come up we still leave the
 617                  * PFC state as it is, given that there are already
 618                  * extant users of it that have succeeded by this point.
 619                  */
 620                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
 621         }
 622 #endif
 623
 624         platform_set_drvdata(pdev, pfc);
 625
 626         dev_info(pfc->dev, "%s support registered\n", info->name);
 627
 628         return 0;
 629 }
 630
 631 static const struct platform_device_id sh_pfc_id_table[] = {
 632 #ifdef CONFIG_PINCTRL_PFC_SH7203
 633         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 634 #endif
 635 #ifdef CONFIG_PINCTRL_PFC_SH7264
 636         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
 637 #endif
 638 #ifdef CONFIG_PINCTRL_PFC_SH7269
 639         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
 640 #endif
 641 #ifdef CONFIG_PINCTRL_PFC_SH7720
 642         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
 643 #endif
 644 #ifdef CONFIG_PINCTRL_PFC_SH7722
 645         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
 646 #endif
 647 #ifdef CONFIG_PINCTRL_PFC_SH7723
 648         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
 649 #endif
 650 #ifdef CONFIG_PINCTRL_PFC_SH7724
 651         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
 652 #endif
 653 #ifdef CONFIG_PINCTRL_PFC_SH7734
 654         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
 655 #endif
 656 #ifdef CONFIG_PINCTRL_PFC_SH7757
 657         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
 658 #endif
 659 #ifdef CONFIG_PINCTRL_PFC_SH7785
 660         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
 661 #endif
 662 #ifdef CONFIG_PINCTRL_PFC_SH7786
 663         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
 664 #endif
 665 #ifdef CONFIG_PINCTRL_PFC_SHX3
 666         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
 667 #endif
 668         { "sh-pfc", 0 },
 669         { },
 670 };
 671
 672 static struct platform_driver sh_pfc_driver = {
 673         .probe          = sh_pfc_probe,
 674         .id_table       = sh_pfc_id_table,
 675         .driver         = {
 676                 .name   = DRV_NAME,
 677                 .of_match_table = of_match_ptr(sh_pfc_of_table),
 678         },
 679 };
 680
 681 static int __init sh_pfc_init(void)
 682 {
 683         return platform_driver_register(&sh_pfc_driver);
 684 }
 685 postcore_initcall(sh_pfc_init);