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Input: xpad - add support for Xbox1 PDP Camo series gamepad
[linux/fpc-iii.git] / drivers / spi / spi-bcm-qspi.c
blob63231760facce686853f5d0c88d492b71b5ed5cd
1 /*
2 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
3 *
4 * Copyright 2016 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation (the "GPL").
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License version 2 (GPLv2) for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * version 2 (GPLv2) along with this source code.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/ioport.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/spi/spi.h>
34 #include <linux/sysfs.h>
35 #include <linux/types.h>
36 #include "spi-bcm-qspi.h"
37
38 #define DRIVER_NAME "bcm_qspi"
39
40
41 /* BSPI register offsets */
42 #define BSPI_REVISION_ID 0x000
43 #define BSPI_SCRATCH 0x004
44 #define BSPI_MAST_N_BOOT_CTRL 0x008
45 #define BSPI_BUSY_STATUS 0x00c
46 #define BSPI_INTR_STATUS 0x010
47 #define BSPI_B0_STATUS 0x014
48 #define BSPI_B0_CTRL 0x018
49 #define BSPI_B1_STATUS 0x01c
50 #define BSPI_B1_CTRL 0x020
51 #define BSPI_STRAP_OVERRIDE_CTRL 0x024
52 #define BSPI_FLEX_MODE_ENABLE 0x028
53 #define BSPI_BITS_PER_CYCLE 0x02c
54 #define BSPI_BITS_PER_PHASE 0x030
55 #define BSPI_CMD_AND_MODE_BYTE 0x034
56 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
57 #define BSPI_BSPI_XOR_VALUE 0x03c
58 #define BSPI_BSPI_XOR_ENABLE 0x040
59 #define BSPI_BSPI_PIO_MODE_ENABLE 0x044
60 #define BSPI_BSPI_PIO_IODIR 0x048
61 #define BSPI_BSPI_PIO_DATA 0x04c
62
63 /* RAF register offsets */
64 #define BSPI_RAF_START_ADDR 0x100
65 #define BSPI_RAF_NUM_WORDS 0x104
66 #define BSPI_RAF_CTRL 0x108
67 #define BSPI_RAF_FULLNESS 0x10c
68 #define BSPI_RAF_WATERMARK 0x110
69 #define BSPI_RAF_STATUS 0x114
70 #define BSPI_RAF_READ_DATA 0x118
71 #define BSPI_RAF_WORD_CNT 0x11c
72 #define BSPI_RAF_CURR_ADDR 0x120
73
74 /* Override mode masks */
75 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
76 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
77 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
78 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
79 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
80
81 #define BSPI_ADDRLEN_3BYTES 3
82 #define BSPI_ADDRLEN_4BYTES 4
83
84 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
85
86 #define BSPI_RAF_CTRL_START_MASK BIT(0)
87 #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
88
89 #define BSPI_BPP_MODE_SELECT_MASK BIT(8)
90 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
91
92 #define BSPI_READ_LENGTH 256
93
94 /* MSPI register offsets */
95 #define MSPI_SPCR0_LSB 0x000
96 #define MSPI_SPCR0_MSB 0x004
97 #define MSPI_SPCR1_LSB 0x008
98 #define MSPI_SPCR1_MSB 0x00c
99 #define MSPI_NEWQP 0x010
100 #define MSPI_ENDQP 0x014
101 #define MSPI_SPCR2 0x018
102 #define MSPI_MSPI_STATUS 0x020
103 #define MSPI_CPTQP 0x024
104 #define MSPI_SPCR3 0x028
105 #define MSPI_TXRAM 0x040
106 #define MSPI_RXRAM 0x0c0
107 #define MSPI_CDRAM 0x140
108 #define MSPI_WRITE_LOCK 0x180
109
110 #define MSPI_MASTER_BIT BIT(7)
111
112 #define MSPI_NUM_CDRAM 16
113 #define MSPI_CDRAM_CONT_BIT BIT(7)
114 #define MSPI_CDRAM_BITSE_BIT BIT(6)
115 #define MSPI_CDRAM_PCS 0xf
116
117 #define MSPI_SPCR2_SPE BIT(6)
118 #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
119
120 #define MSPI_MSPI_STATUS_SPIF BIT(0)
121
122 #define INTR_BASE_BIT_SHIFT 0x02
123 #define INTR_COUNT 0x07
124
125 #define NUM_CHIPSELECT 4
126 #define QSPI_SPBR_MIN 8U
127 #define QSPI_SPBR_MAX 255U
128
129 #define OPCODE_DIOR 0xBB
130 #define OPCODE_QIOR 0xEB
131 #define OPCODE_DIOR_4B 0xBC
132 #define OPCODE_QIOR_4B 0xEC
133
134 #define MAX_CMD_SIZE 6
135
136 #define ADDR_4MB_MASK GENMASK(22, 0)
137
138 /* stop at end of transfer, no other reason */
139 #define TRANS_STATUS_BREAK_NONE 0
140 /* stop at end of spi_message */
141 #define TRANS_STATUS_BREAK_EOM 1
142 /* stop at end of spi_transfer if delay */
143 #define TRANS_STATUS_BREAK_DELAY 2
144 /* stop at end of spi_transfer if cs_change */
145 #define TRANS_STATUS_BREAK_CS_CHANGE 4
146 /* stop if we run out of bytes */
147 #define TRANS_STATUS_BREAK_NO_BYTES 8
148
149 /* events that make us stop filling TX slots */
150 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
151 TRANS_STATUS_BREAK_DELAY | \
152 TRANS_STATUS_BREAK_CS_CHANGE)
153
154 /* events that make us deassert CS */
155 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
156 TRANS_STATUS_BREAK_CS_CHANGE)
157
158 struct bcm_qspi_parms {
159 u32 speed_hz;
160 u8 mode;
161 u8 bits_per_word;
162 };
163
164 struct bcm_xfer_mode {
165 bool flex_mode;
166 unsigned int width;
167 unsigned int addrlen;
168 unsigned int hp;
169 };
170
171 enum base_type {
172 MSPI,
173 BSPI,
174 CHIP_SELECT,
175 BASEMAX,
176 };
177
178 enum irq_source {
179 SINGLE_L2,
180 MUXED_L1,
181 };
182
183 struct bcm_qspi_irq {
184 const char *irq_name;
185 const irq_handler_t irq_handler;
186 int irq_source;
187 u32 mask;
188 };
189
190 struct bcm_qspi_dev_id {
191 const struct bcm_qspi_irq *irqp;
192 void *dev;
193 };
194
195 struct qspi_trans {
196 struct spi_transfer *trans;
197 int byte;
198 };
199
200 struct bcm_qspi {
201 struct platform_device *pdev;
202 struct spi_master *master;
203 struct clk *clk;
204 u32 base_clk;
205 u32 max_speed_hz;
206 void __iomem *base[BASEMAX];
207
208 /* Some SoCs provide custom interrupt status register(s) */
209 struct bcm_qspi_soc_intc *soc_intc;
210
211 struct bcm_qspi_parms last_parms;
212 struct qspi_trans trans_pos;
213 int curr_cs;
214 int bspi_maj_rev;
215 int bspi_min_rev;
216 int bspi_enabled;
217 struct spi_flash_read_message *bspi_rf_msg;
218 u32 bspi_rf_msg_idx;
219 u32 bspi_rf_msg_len;
220 u32 bspi_rf_msg_status;
221 struct bcm_xfer_mode xfer_mode;
222 u32 s3_strap_override_ctrl;
223 bool bspi_mode;
224 bool big_endian;
225 int num_irqs;
226 struct bcm_qspi_dev_id *dev_ids;
227 struct completion mspi_done;
228 struct completion bspi_done;
229 };
230
231 static inline bool has_bspi(struct bcm_qspi *qspi)
232 {
233 return qspi->bspi_mode;
234 }
235
236 /* Read qspi controller register*/
237 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
238 unsigned int offset)
239 {
240 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
241 }
242
243 /* Write qspi controller register*/
244 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
245 unsigned int offset, unsigned int data)
246 {
247 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
248 }
249
250 /* BSPI helpers */
251 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
252 {
253 int i;
254
255 /* this should normally finish within 10us */
256 for (i = 0; i < 1000; i++) {
257 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
258 return 0;
259 udelay(1);
260 }
261 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
262 return -EIO;
263 }
264
265 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
266 {
267 if (qspi->bspi_maj_rev < 4)
268 return true;
269 return false;
270 }
271
272 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
273 {
274 bcm_qspi_bspi_busy_poll(qspi);
275 /* Force rising edge for the b0/b1 'flush' field */
276 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
277 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
278 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
279 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
280 }
281
282 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
283 {
284 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
285 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
286 }
287
288 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
289 {
290 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
291
292 /* BSPI v3 LR is LE only, convert data to host endianness */
293 if (bcm_qspi_bspi_ver_three(qspi))
294 data = le32_to_cpu(data);
295
296 return data;
297 }
298
299 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
300 {
301 bcm_qspi_bspi_busy_poll(qspi);
302 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
303 BSPI_RAF_CTRL_START_MASK);
304 }
305
306 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
307 {
308 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
309 BSPI_RAF_CTRL_CLEAR_MASK);
310 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
311 }
312
313 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
314 {
315 u32 *buf = (u32 *)qspi->bspi_rf_msg->buf;
316 u32 data = 0;
317
318 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg,
319 qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len);
320 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
321 data = bcm_qspi_bspi_lr_read_fifo(qspi);
322 if (likely(qspi->bspi_rf_msg_len >= 4) &&
323 IS_ALIGNED((uintptr_t)buf, 4)) {
324 buf[qspi->bspi_rf_msg_idx++] = data;
325 qspi->bspi_rf_msg_len -= 4;
326 } else {
327 /* Read out remaining bytes, make sure*/
328 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx];
329
330 data = cpu_to_le32(data);
331 while (qspi->bspi_rf_msg_len) {
332 *cbuf++ = (u8)data;
333 data >>= 8;
334 qspi->bspi_rf_msg_len--;
335 }
336 }
337 }
338 }
339
340 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
341 int bpp, int bpc, int flex_mode)
342 {
343 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
344 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
345 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
346 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
347 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
348 }
349
350 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width,
351 int addrlen, int hp)
352 {
353 int bpc = 0, bpp = 0;
354 u8 command = SPINOR_OP_READ_FAST;
355 int flex_mode = 1, rv = 0;
356 bool spans_4byte = false;
357
358 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
359 width, addrlen, hp);
360
361 if (addrlen == BSPI_ADDRLEN_4BYTES) {
362 bpp = BSPI_BPP_ADDR_SELECT_MASK;
363 spans_4byte = true;
364 }
365
366 bpp |= 8;
367
368 switch (width) {
369 case SPI_NBITS_SINGLE:
370 if (addrlen == BSPI_ADDRLEN_3BYTES)
371 /* default mode, does not need flex_cmd */
372 flex_mode = 0;
373 else
374 command = SPINOR_OP_READ4_FAST;
375 break;
376 case SPI_NBITS_DUAL:
377 bpc = 0x00000001;
378 if (hp) {
379 bpc |= 0x00010100; /* address and mode are 2-bit */
380 bpp = BSPI_BPP_MODE_SELECT_MASK;
381 command = OPCODE_DIOR;
382 if (spans_4byte)
383 command = OPCODE_DIOR_4B;
384 } else {
385 command = SPINOR_OP_READ_1_1_2;
386 if (spans_4byte)
387 command = SPINOR_OP_READ4_1_1_2;
388 }
389 break;
390 case SPI_NBITS_QUAD:
391 bpc = 0x00000002;
392 if (hp) {
393 bpc |= 0x00020200; /* address and mode are 4-bit */
394 bpp = 4; /* dummy cycles */
395 bpp |= BSPI_BPP_ADDR_SELECT_MASK;
396 command = OPCODE_QIOR;
397 if (spans_4byte)
398 command = OPCODE_QIOR_4B;
399 } else {
400 command = SPINOR_OP_READ_1_1_4;
401 if (spans_4byte)
402 command = SPINOR_OP_READ4_1_1_4;
403 }
404 break;
405 default:
406 rv = -EINVAL;
407 break;
408 }
409
410 if (rv == 0)
411 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc,
412 flex_mode);
413
414 return rv;
415 }
416
417 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
418 int addrlen, int hp)
419 {
420 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
421
422 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
423 width, addrlen, hp);
424
425 switch (width) {
426 case SPI_NBITS_SINGLE:
427 /* clear quad/dual mode */
428 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
429 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
430 break;
431
432 case SPI_NBITS_QUAD:
433 /* clear dual mode and set quad mode */
434 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
435 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
436 break;
437 case SPI_NBITS_DUAL:
438 /* clear quad mode set dual mode */
439 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
440 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 if (addrlen == BSPI_ADDRLEN_4BYTES)
447 /* set 4byte mode*/
448 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
449 else
450 /* clear 4 byte mode */
451 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
452
453 /* set the override mode */
454 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
455 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
456 bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0);
457
458 return 0;
459 }
460
461 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
462 int width, int addrlen, int hp)
463 {
464 int error = 0;
465
466 /* default mode */
467 qspi->xfer_mode.flex_mode = true;
468
469 if (!bcm_qspi_bspi_ver_three(qspi)) {
470 u32 val, mask;
471
472 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
473 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
474 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
475 qspi->xfer_mode.flex_mode = false;
476 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE,
477 0);
478
479 if ((val | qspi->s3_strap_override_ctrl) &
480 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL)
481 width = SPI_NBITS_DUAL;
482 else if ((val | qspi->s3_strap_override_ctrl) &
483 BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD)
484 width = SPI_NBITS_QUAD;
485
486 error = bcm_qspi_bspi_set_override(qspi, width, addrlen,
487 hp);
488 }
489 }
490
491 if (qspi->xfer_mode.flex_mode)
492 error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp);
493
494 if (error) {
495 dev_warn(&qspi->pdev->dev,
496 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
497 width, addrlen, hp);
498 } else if (qspi->xfer_mode.width != width ||
499 qspi->xfer_mode.addrlen != addrlen ||
500 qspi->xfer_mode.hp != hp) {
501 qspi->xfer_mode.width = width;
502 qspi->xfer_mode.addrlen = addrlen;
503 qspi->xfer_mode.hp = hp;
504 dev_dbg(&qspi->pdev->dev,
505 "cs:%d %d-lane output, %d-byte address%s\n",
506 qspi->curr_cs,
507 qspi->xfer_mode.width,
508 qspi->xfer_mode.addrlen,
509 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
510 }
511
512 return error;
513 }
514
515 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
516 {
517 if (!has_bspi(qspi))
518 return;
519
520 qspi->bspi_enabled = 1;
521 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
522 return;
523
524 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
525 udelay(1);
526 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
527 udelay(1);
528 }
529
530 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
531 {
532 if (!has_bspi(qspi))
533 return;
534
535 qspi->bspi_enabled = 0;
536 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
537 return;
538
539 bcm_qspi_bspi_busy_poll(qspi);
540 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
541 udelay(1);
542 }
543
544 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
545 {
546 u32 rd = 0;
547 u32 wr = 0;
548
549 if (qspi->base[CHIP_SELECT]) {
550 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
551 wr = (rd & ~0xff) | (1 << cs);
552 if (rd == wr)
553 return;
554 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
555 usleep_range(10, 20);
556 }
557
558 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
559 qspi->curr_cs = cs;
560 }
561
562 /* MSPI helpers */
563 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
564 const struct bcm_qspi_parms *xp)
565 {
566 u32 spcr, spbr = 0;
567
568 if (xp->speed_hz)
569 spbr = qspi->base_clk / (2 * xp->speed_hz);
570
571 spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
572 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
573
574 spcr = MSPI_MASTER_BIT;
575 /* for 16 bit the data should be zero */
576 if (xp->bits_per_word != 16)
577 spcr |= xp->bits_per_word << 2;
578 spcr |= xp->mode & 3;
579 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
580
581 qspi->last_parms = *xp;
582 }
583
584 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
585 struct spi_device *spi,
586 struct spi_transfer *trans)
587 {
588 struct bcm_qspi_parms xp;
589
590 xp.speed_hz = trans->speed_hz;
591 xp.bits_per_word = trans->bits_per_word;
592 xp.mode = spi->mode;
593
594 bcm_qspi_hw_set_parms(qspi, &xp);
595 }
596
597 static int bcm_qspi_setup(struct spi_device *spi)
598 {
599 struct bcm_qspi_parms *xp;
600
601 if (spi->bits_per_word > 16)
602 return -EINVAL;
603
604 xp = spi_get_ctldata(spi);
605 if (!xp) {
606 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
607 if (!xp)
608 return -ENOMEM;
609 spi_set_ctldata(spi, xp);
610 }
611 xp->speed_hz = spi->max_speed_hz;
612 xp->mode = spi->mode;
613
614 if (spi->bits_per_word)
615 xp->bits_per_word = spi->bits_per_word;
616 else
617 xp->bits_per_word = 8;
618
619 return 0;
620 }
621
622 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
623 struct qspi_trans *qt, int flags)
624 {
625 int ret = TRANS_STATUS_BREAK_NONE;
626
627 /* count the last transferred bytes */
628 if (qt->trans->bits_per_word <= 8)
629 qt->byte++;
630 else
631 qt->byte += 2;
632
633 if (qt->byte >= qt->trans->len) {
634 /* we're at the end of the spi_transfer */
635
636 /* in TX mode, need to pause for a delay or CS change */
637 if (qt->trans->delay_usecs &&
638 (flags & TRANS_STATUS_BREAK_DELAY))
639 ret |= TRANS_STATUS_BREAK_DELAY;
640 if (qt->trans->cs_change &&
641 (flags & TRANS_STATUS_BREAK_CS_CHANGE))
642 ret |= TRANS_STATUS_BREAK_CS_CHANGE;
643 if (ret)
644 goto done;
645
646 dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
647 if (spi_transfer_is_last(qspi->master, qt->trans))
648 ret = TRANS_STATUS_BREAK_EOM;
649 else
650 ret = TRANS_STATUS_BREAK_NO_BYTES;
651
652 qt->trans = NULL;
653 }
654
655 done:
656 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
657 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
658 return ret;
659 }
660
661 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
662 {
663 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
664
665 /* mask out reserved bits */
666 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
667 }
668
669 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
670 {
671 u32 reg_offset = MSPI_RXRAM;
672 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
673 u32 msb_offset = reg_offset + (slot << 3);
674
675 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
676 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
677 }
678
679 static void read_from_hw(struct bcm_qspi *qspi, int slots)
680 {
681 struct qspi_trans tp;
682 int slot;
683
684 bcm_qspi_disable_bspi(qspi);
685
686 if (slots > MSPI_NUM_CDRAM) {
687 /* should never happen */
688 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
689 return;
690 }
691
692 tp = qspi->trans_pos;
693
694 for (slot = 0; slot < slots; slot++) {
695 if (tp.trans->bits_per_word <= 8) {
696 u8 *buf = tp.trans->rx_buf;
697
698 if (buf)
699 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
700 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
701 buf ? buf[tp.byte] : 0xff);
702 } else {
703 u16 *buf = tp.trans->rx_buf;
704
705 if (buf)
706 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
707 slot);
708 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
709 buf ? buf[tp.byte] : 0xffff);
710 }
711
712 update_qspi_trans_byte_count(qspi, &tp,
713 TRANS_STATUS_BREAK_NONE);
714 }
715
716 qspi->trans_pos = tp;
717 }
718
719 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
720 u8 val)
721 {
722 u32 reg_offset = MSPI_TXRAM + (slot << 3);
723
724 /* mask out reserved bits */
725 bcm_qspi_write(qspi, MSPI, reg_offset, val);
726 }
727
728 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
729 u16 val)
730 {
731 u32 reg_offset = MSPI_TXRAM;
732 u32 msb_offset = reg_offset + (slot << 3);
733 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
734
735 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
736 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
737 }
738
739 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
740 {
741 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
742 }
743
744 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
745 {
746 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
747 }
748
749 /* Return number of slots written */
750 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
751 {
752 struct qspi_trans tp;
753 int slot = 0, tstatus = 0;
754 u32 mspi_cdram = 0;
755
756 bcm_qspi_disable_bspi(qspi);
757 tp = qspi->trans_pos;
758 bcm_qspi_update_parms(qspi, spi, tp.trans);
759
760 /* Run until end of transfer or reached the max data */
761 while (!tstatus && slot < MSPI_NUM_CDRAM) {
762 if (tp.trans->bits_per_word <= 8) {
763 const u8 *buf = tp.trans->tx_buf;
764 u8 val = buf ? buf[tp.byte] : 0xff;
765
766 write_txram_slot_u8(qspi, slot, val);
767 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
768 } else {
769 const u16 *buf = tp.trans->tx_buf;
770 u16 val = buf ? buf[tp.byte / 2] : 0xffff;
771
772 write_txram_slot_u16(qspi, slot, val);
773 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
774 }
775 mspi_cdram = MSPI_CDRAM_CONT_BIT;
776
777 if (has_bspi(qspi))
778 mspi_cdram &= ~1;
779 else
780 mspi_cdram |= (~(1 << spi->chip_select) &
781 MSPI_CDRAM_PCS);
782
783 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
784 MSPI_CDRAM_BITSE_BIT);
785
786 write_cdram_slot(qspi, slot, mspi_cdram);
787
788 tstatus = update_qspi_trans_byte_count(qspi, &tp,
789 TRANS_STATUS_BREAK_TX);
790 slot++;
791 }
792
793 if (!slot) {
794 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
795 goto done;
796 }
797
798 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
799 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
800 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
801
802 if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
803 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
804 ~MSPI_CDRAM_CONT_BIT;
805 write_cdram_slot(qspi, slot - 1, mspi_cdram);
806 }
807
808 if (has_bspi(qspi))
809 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
810
811 /* Must flush previous writes before starting MSPI operation */
812 mb();
813 /* Set cont | spe | spifie */
814 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
815
816 done:
817 return slot;
818 }
819
820 static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
821 struct spi_flash_read_message *msg)
822 {
823 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
824 u32 addr = 0, len, len_words;
825 int ret = 0;
826 unsigned long timeo = msecs_to_jiffies(100);
827 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
828
829 if (bcm_qspi_bspi_ver_three(qspi))
830 if (msg->addr_width == BSPI_ADDRLEN_4BYTES)
831 return -EIO;
832
833 bcm_qspi_chip_select(qspi, spi->chip_select);
834 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
835
836 /*
837 * when using flex mode mode we need to send
838 * the upper address byte to bspi
839 */
840 if (bcm_qspi_bspi_ver_three(qspi) == false) {
841 addr = msg->from & 0xff000000;
842 bcm_qspi_write(qspi, BSPI,
843 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
844 }
845
846 if (!qspi->xfer_mode.flex_mode)
847 addr = msg->from;
848 else
849 addr = msg->from & 0x00ffffff;
850
851 /* set BSPI RAF buffer max read length */
852 len = msg->len;
853 if (len > BSPI_READ_LENGTH)
854 len = BSPI_READ_LENGTH;
855
856 if (bcm_qspi_bspi_ver_three(qspi) == true)
857 addr = (addr + 0xc00000) & 0xffffff;
858
859 reinit_completion(&qspi->bspi_done);
860 bcm_qspi_enable_bspi(qspi);
861 len_words = (len + 3) >> 2;
862 qspi->bspi_rf_msg = msg;
863 qspi->bspi_rf_msg_status = 0;
864 qspi->bspi_rf_msg_idx = 0;
865 qspi->bspi_rf_msg_len = len;
866 dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
867
868 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
869 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
870 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
871
872 if (qspi->soc_intc) {
873 /*
874 * clear soc MSPI and BSPI interrupts and enable
875 * BSPI interrupts.
876 */
877 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
878 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
879 }
880
881 /* Must flush previous writes before starting BSPI operation */
882 mb();
883
884 bcm_qspi_bspi_lr_start(qspi);
885 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
886 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
887 ret = -ETIMEDOUT;
888 } else {
889 /* set the return length for the caller */
890 msg->retlen = len;
891 }
892
893 return ret;
894 }
895
896 static int bcm_qspi_flash_read(struct spi_device *spi,
897 struct spi_flash_read_message *msg)
898 {
899 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
900 int ret = 0;
901 bool mspi_read = false;
902 u32 io_width, addrlen, addr, len;
903 u_char *buf;
904
905 buf = msg->buf;
906 addr = msg->from;
907 len = msg->len;
908
909 if (bcm_qspi_bspi_ver_three(qspi) == true) {
910 /*
911 * The address coming into this function is a raw flash offset.
912 * But for BSPI <= V3, we need to convert it to a remapped BSPI
913 * address. If it crosses a 4MB boundary, just revert back to
914 * using MSPI.
915 */
916 addr = (addr + 0xc00000) & 0xffffff;
917
918 if ((~ADDR_4MB_MASK & addr) ^
919 (~ADDR_4MB_MASK & (addr + len - 1)))
920 mspi_read = true;
921 }
922
923 /* non-aligned and very short transfers are handled by MSPI */
924 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
925 len < 4)
926 mspi_read = true;
927
928 if (mspi_read)
929 /* this will make the m25p80 read to fallback to mspi read */
930 return -EAGAIN;
931
932 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
933 addrlen = msg->addr_width;
934 ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1);
935
936 if (!ret)
937 ret = bcm_qspi_bspi_flash_read(spi, msg);
938
939 return ret;
940 }
941
942 static int bcm_qspi_transfer_one(struct spi_master *master,
943 struct spi_device *spi,
944 struct spi_transfer *trans)
945 {
946 struct bcm_qspi *qspi = spi_master_get_devdata(master);
947 int slots;
948 unsigned long timeo = msecs_to_jiffies(100);
949
950 bcm_qspi_chip_select(qspi, spi->chip_select);
951 qspi->trans_pos.trans = trans;
952 qspi->trans_pos.byte = 0;
953
954 while (qspi->trans_pos.byte < trans->len) {
955 reinit_completion(&qspi->mspi_done);
956
957 slots = write_to_hw(qspi, spi);
958 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
959 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
960 return -ETIMEDOUT;
961 }
962
963 read_from_hw(qspi, slots);
964 }
965
966 return 0;
967 }
968
969 static void bcm_qspi_cleanup(struct spi_device *spi)
970 {
971 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
972
973 kfree(xp);
974 }
975
976 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
977 {
978 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
979 struct bcm_qspi *qspi = qspi_dev_id->dev;
980 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
981
982 if (status & MSPI_MSPI_STATUS_SPIF) {
983 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
984 /* clear interrupt */
985 status &= ~MSPI_MSPI_STATUS_SPIF;
986 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
987 if (qspi->soc_intc)
988 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
989 complete(&qspi->mspi_done);
990 return IRQ_HANDLED;
991 }
992
993 return IRQ_NONE;
994 }
995
996 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
997 {
998 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
999 struct bcm_qspi *qspi = qspi_dev_id->dev;
1000 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1001 u32 status = qspi_dev_id->irqp->mask;
1002
1003 if (qspi->bspi_enabled && qspi->bspi_rf_msg) {
1004 bcm_qspi_bspi_lr_data_read(qspi);
1005 if (qspi->bspi_rf_msg_len == 0) {
1006 qspi->bspi_rf_msg = NULL;
1007 if (qspi->soc_intc) {
1008 /* disable soc BSPI interrupt */
1009 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1010 false);
1011 /* indicate done */
1012 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1013 }
1014
1015 if (qspi->bspi_rf_msg_status)
1016 bcm_qspi_bspi_lr_clear(qspi);
1017 else
1018 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1019 }
1020
1021 if (qspi->soc_intc)
1022 /* clear soc BSPI interrupt */
1023 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1024 }
1025
1026 status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1027 if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0)
1028 complete(&qspi->bspi_done);
1029
1030 return IRQ_HANDLED;
1031 }
1032
1033 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1034 {
1035 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1036 struct bcm_qspi *qspi = qspi_dev_id->dev;
1037 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1038
1039 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1040 qspi->bspi_rf_msg_status = -EIO;
1041 if (qspi->soc_intc)
1042 /* clear soc interrupt */
1043 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1044
1045 complete(&qspi->bspi_done);
1046 return IRQ_HANDLED;
1047 }
1048
1049 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1050 {
1051 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1052 struct bcm_qspi *qspi = qspi_dev_id->dev;
1053 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1054 irqreturn_t ret = IRQ_NONE;
1055
1056 if (soc_intc) {
1057 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1058
1059 if (status & MSPI_DONE)
1060 ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1061 else if (status & BSPI_DONE)
1062 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1063 else if (status & BSPI_ERR)
1064 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1065 }
1066
1067 return ret;
1068 }
1069
1070 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1071 {
1072 .irq_name = "spi_lr_fullness_reached",
1073 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1074 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1075 },
1076 {
1077 .irq_name = "spi_lr_session_aborted",
1078 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1079 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1080 },
1081 {
1082 .irq_name = "spi_lr_impatient",
1083 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1084 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1085 },
1086 {
1087 .irq_name = "spi_lr_session_done",
1088 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1089 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1090 },
1091 #ifdef QSPI_INT_DEBUG
1092 /* this interrupt is for debug purposes only, dont request irq */
1093 {
1094 .irq_name = "spi_lr_overread",
1095 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1096 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1097 },
1098 #endif
1099 {
1100 .irq_name = "mspi_done",
1101 .irq_handler = bcm_qspi_mspi_l2_isr,
1102 .mask = INTR_MSPI_DONE_MASK,
1103 },
1104 {
1105 .irq_name = "mspi_halted",
1106 .irq_handler = bcm_qspi_mspi_l2_isr,
1107 .mask = INTR_MSPI_HALTED_MASK,
1108 },
1109 {
1110 /* single muxed L1 interrupt source */
1111 .irq_name = "spi_l1_intr",
1112 .irq_handler = bcm_qspi_l1_isr,
1113 .irq_source = MUXED_L1,
1114 .mask = QSPI_INTERRUPTS_ALL,
1115 },
1116 };
1117
1118 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1119 {
1120 u32 val = 0;
1121
1122 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1123 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1124 qspi->bspi_min_rev = val & 0xff;
1125 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1126 /* Force mapping of BSPI address -> flash offset */
1127 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1128 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1129 }
1130 qspi->bspi_enabled = 1;
1131 bcm_qspi_disable_bspi(qspi);
1132 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1133 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1134 }
1135
1136 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1137 {
1138 struct bcm_qspi_parms parms;
1139
1140 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1141 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1142 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1143 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1144 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1145
1146 parms.mode = SPI_MODE_3;
1147 parms.bits_per_word = 8;
1148 parms.speed_hz = qspi->max_speed_hz;
1149 bcm_qspi_hw_set_parms(qspi, &parms);
1150
1151 if (has_bspi(qspi))
1152 bcm_qspi_bspi_init(qspi);
1153 }
1154
1155 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1156 {
1157 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1158 if (has_bspi(qspi))
1159 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1160
1161 }
1162
1163 static const struct of_device_id bcm_qspi_of_match[] = {
1164 { .compatible = "brcm,spi-bcm-qspi" },
1165 {},
1166 };
1167 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1168
1169 int bcm_qspi_probe(struct platform_device *pdev,
1170 struct bcm_qspi_soc_intc *soc_intc)
1171 {
1172 struct device *dev = &pdev->dev;
1173 struct bcm_qspi *qspi;
1174 struct spi_master *master;
1175 struct resource *res;
1176 int irq, ret = 0, num_ints = 0;
1177 u32 val;
1178 const char *name = NULL;
1179 int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1180
1181 /* We only support device-tree instantiation */
1182 if (!dev->of_node)
1183 return -ENODEV;
1184
1185 if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1186 return -ENODEV;
1187
1188 master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
1189 if (!master) {
1190 dev_err(dev, "error allocating spi_master\n");
1191 return -ENOMEM;
1192 }
1193
1194 qspi = spi_master_get_devdata(master);
1195 qspi->pdev = pdev;
1196 qspi->trans_pos.trans = NULL;
1197 qspi->trans_pos.byte = 0;
1198 qspi->master = master;
1199
1200 master->bus_num = -1;
1201 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1202 master->setup = bcm_qspi_setup;
1203 master->transfer_one = bcm_qspi_transfer_one;
1204 master->spi_flash_read = bcm_qspi_flash_read;
1205 master->cleanup = bcm_qspi_cleanup;
1206 master->dev.of_node = dev->of_node;
1207 master->num_chipselect = NUM_CHIPSELECT;
1208
1209 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1210
1211 if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1212 master->num_chipselect = val;
1213
1214 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1215 if (!res)
1216 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1217 "mspi");
1218
1219 if (res) {
1220 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1221 if (IS_ERR(qspi->base[MSPI])) {
1222 ret = PTR_ERR(qspi->base[MSPI]);
1223 goto qspi_resource_err;
1224 }
1225 } else {
1226 goto qspi_resource_err;
1227 }
1228
1229 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1230 if (res) {
1231 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1232 if (IS_ERR(qspi->base[BSPI])) {
1233 ret = PTR_ERR(qspi->base[BSPI]);
1234 goto qspi_resource_err;
1235 }
1236 qspi->bspi_mode = true;
1237 } else {
1238 qspi->bspi_mode = false;
1239 }
1240
1241 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1242
1243 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1244 if (res) {
1245 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1246 if (IS_ERR(qspi->base[CHIP_SELECT])) {
1247 ret = PTR_ERR(qspi->base[CHIP_SELECT]);
1248 goto qspi_resource_err;
1249 }
1250 }
1251
1252 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1253 GFP_KERNEL);
1254 if (!qspi->dev_ids) {
1255 ret = -ENOMEM;
1256 goto qspi_resource_err;
1257 }
1258
1259 for (val = 0; val < num_irqs; val++) {
1260 irq = -1;
1261 name = qspi_irq_tab[val].irq_name;
1262 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1263 /* get the l2 interrupts */
1264 irq = platform_get_irq_byname(pdev, name);
1265 } else if (!num_ints && soc_intc) {
1266 /* all mspi, bspi intrs muxed to one L1 intr */
1267 irq = platform_get_irq(pdev, 0);
1268 }
1269
1270 if (irq >= 0) {
1271 ret = devm_request_irq(&pdev->dev, irq,
1272 qspi_irq_tab[val].irq_handler, 0,
1273 name,
1274 &qspi->dev_ids[val]);
1275 if (ret < 0) {
1276 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1277 goto qspi_probe_err;
1278 }
1279
1280 qspi->dev_ids[val].dev = qspi;
1281 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1282 num_ints++;
1283 dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1284 qspi_irq_tab[val].irq_name,
1285 irq);
1286 }
1287 }
1288
1289 if (!num_ints) {
1290 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1291 ret = -EINVAL;
1292 goto qspi_probe_err;
1293 }
1294
1295 /*
1296 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1297 * in specific ways
1298 */
1299 if (soc_intc) {
1300 qspi->soc_intc = soc_intc;
1301 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1302 } else {
1303 qspi->soc_intc = NULL;
1304 }
1305
1306 qspi->clk = devm_clk_get(&pdev->dev, NULL);
1307 if (IS_ERR(qspi->clk)) {
1308 dev_warn(dev, "unable to get clock\n");
1309 ret = PTR_ERR(qspi->clk);
1310 goto qspi_probe_err;
1311 }
1312
1313 ret = clk_prepare_enable(qspi->clk);
1314 if (ret) {
1315 dev_err(dev, "failed to prepare clock\n");
1316 goto qspi_probe_err;
1317 }
1318
1319 qspi->base_clk = clk_get_rate(qspi->clk);
1320 qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
1321
1322 bcm_qspi_hw_init(qspi);
1323 init_completion(&qspi->mspi_done);
1324 init_completion(&qspi->bspi_done);
1325 qspi->curr_cs = -1;
1326
1327 platform_set_drvdata(pdev, qspi);
1328
1329 qspi->xfer_mode.width = -1;
1330 qspi->xfer_mode.addrlen = -1;
1331 qspi->xfer_mode.hp = -1;
1332
1333 ret = devm_spi_register_master(&pdev->dev, master);
1334 if (ret < 0) {
1335 dev_err(dev, "can't register master\n");
1336 goto qspi_reg_err;
1337 }
1338
1339 return 0;
1340
1341 qspi_reg_err:
1342 bcm_qspi_hw_uninit(qspi);
1343 clk_disable_unprepare(qspi->clk);
1344 qspi_probe_err:
1345 kfree(qspi->dev_ids);
1346 qspi_resource_err:
1347 spi_master_put(master);
1348 return ret;
1349 }
1350 /* probe function to be called by SoC specific platform driver probe */
1351 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1352
1353 int bcm_qspi_remove(struct platform_device *pdev)
1354 {
1355 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1356
1357 platform_set_drvdata(pdev, NULL);
1358 bcm_qspi_hw_uninit(qspi);
1359 clk_disable_unprepare(qspi->clk);
1360 kfree(qspi->dev_ids);
1361 spi_unregister_master(qspi->master);
1362
1363 return 0;
1364 }
1365 /* function to be called by SoC specific platform driver remove() */
1366 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1367
1368 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1369 {
1370 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1371
1372 spi_master_suspend(qspi->master);
1373 clk_disable(qspi->clk);
1374 bcm_qspi_hw_uninit(qspi);
1375
1376 return 0;
1377 };
1378
1379 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1380 {
1381 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1382 int ret = 0;
1383
1384 bcm_qspi_hw_init(qspi);
1385 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1386 if (qspi->soc_intc)
1387 /* enable MSPI interrupt */
1388 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1389 true);
1390
1391 ret = clk_enable(qspi->clk);
1392 if (!ret)
1393 spi_master_resume(qspi->master);
1394
1395 return ret;
1396 }
1397
1398 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1399
1400 /* pm_ops to be called by SoC specific platform driver */
1401 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1402
1403 MODULE_AUTHOR("Kamal Dasu");
1404 MODULE_DESCRIPTION("Broadcom QSPI driver");
1405 MODULE_LICENSE("GPL v2");
1406 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support