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jme: Do not enable NIC WoL functions on S0
[linux/fpc-iii.git] / drivers / mtd / spi-nor / spi-nor.c
blobf40d8a6c94c940689802c802f1a8dec9bf8ad626
1 /*
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
25
26 /* Define max times to check status register before we give up. */
27 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
28
29 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
30
31 static const struct spi_device_id *spi_nor_match_id(const char *name);
32
33 /*
34 * Read the status register, returning its value in the location
35 * Return the status register value.
36 * Returns negative if error occurred.
37 */
38 static int read_sr(struct spi_nor *nor)
39 {
40 int ret;
41 u8 val;
42
43 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
44 if (ret < 0) {
45 pr_err("error %d reading SR\n", (int) ret);
46 return ret;
47 }
48
49 return val;
50 }
51
52 /*
53 * Read configuration register, returning its value in the
54 * location. Return the configuration register value.
55 * Returns negative if error occured.
56 */
57 static int read_cr(struct spi_nor *nor)
58 {
59 int ret;
60 u8 val;
61
62 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
63 if (ret < 0) {
64 dev_err(nor->dev, "error %d reading CR\n", ret);
65 return ret;
66 }
67
68 return val;
69 }
70
71 /*
72 * Dummy Cycle calculation for different type of read.
73 * It can be used to support more commands with
74 * different dummy cycle requirements.
75 */
76 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
77 {
78 switch (nor->flash_read) {
79 case SPI_NOR_FAST:
80 case SPI_NOR_DUAL:
81 case SPI_NOR_QUAD:
82 return 1;
83 case SPI_NOR_NORMAL:
84 return 0;
85 }
86 return 0;
87 }
88
89 /*
90 * Write status register 1 byte
91 * Returns negative if error occurred.
92 */
93 static inline int write_sr(struct spi_nor *nor, u8 val)
94 {
95 nor->cmd_buf[0] = val;
96 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
97 }
98
99 /*
100 * Set write enable latch with Write Enable command.
101 * Returns negative if error occurred.
102 */
103 static inline int write_enable(struct spi_nor *nor)
104 {
105 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
106 }
107
108 /*
109 * Send write disble instruction to the chip.
110 */
111 static inline int write_disable(struct spi_nor *nor)
112 {
113 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
114 }
115
116 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
117 {
118 return mtd->priv;
119 }
120
121 /* Enable/disable 4-byte addressing mode. */
122 static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
123 {
124 int status;
125 bool need_wren = false;
126 u8 cmd;
127
128 switch (JEDEC_MFR(jedec_id)) {
129 case CFI_MFR_ST: /* Micron, actually */
130 /* Some Micron need WREN command; all will accept it */
131 need_wren = true;
132 case CFI_MFR_MACRONIX:
133 case 0xEF /* winbond */:
134 if (need_wren)
135 write_enable(nor);
136
137 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
138 status = nor->write_reg(nor, cmd, NULL, 0, 0);
139 if (need_wren)
140 write_disable(nor);
141
142 return status;
143 default:
144 /* Spansion style */
145 nor->cmd_buf[0] = enable << 7;
146 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
147 }
148 }
149
150 static int spi_nor_wait_till_ready(struct spi_nor *nor)
151 {
152 unsigned long deadline;
153 int sr;
154
155 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
156
157 do {
158 cond_resched();
159
160 sr = read_sr(nor);
161 if (sr < 0)
162 break;
163 else if (!(sr & SR_WIP))
164 return 0;
165 } while (!time_after_eq(jiffies, deadline));
166
167 return -ETIMEDOUT;
168 }
169
170 /*
171 * Service routine to read status register until ready, or timeout occurs.
172 * Returns non-zero if error.
173 */
174 static int wait_till_ready(struct spi_nor *nor)
175 {
176 return nor->wait_till_ready(nor);
177 }
178
179 /*
180 * Erase the whole flash memory
181 *
182 * Returns 0 if successful, non-zero otherwise.
183 */
184 static int erase_chip(struct spi_nor *nor)
185 {
186 int ret;
187
188 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
189
190 /* Wait until finished previous write command. */
191 ret = wait_till_ready(nor);
192 if (ret)
193 return ret;
194
195 /* Send write enable, then erase commands. */
196 write_enable(nor);
197
198 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
199 }
200
201 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
202 {
203 int ret = 0;
204
205 mutex_lock(&nor->lock);
206
207 if (nor->prepare) {
208 ret = nor->prepare(nor, ops);
209 if (ret) {
210 dev_err(nor->dev, "failed in the preparation.\n");
211 mutex_unlock(&nor->lock);
212 return ret;
213 }
214 }
215 return ret;
216 }
217
218 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
219 {
220 if (nor->unprepare)
221 nor->unprepare(nor, ops);
222 mutex_unlock(&nor->lock);
223 }
224
225 /*
226 * Erase an address range on the nor chip. The address range may extend
227 * one or more erase sectors. Return an error is there is a problem erasing.
228 */
229 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
230 {
231 struct spi_nor *nor = mtd_to_spi_nor(mtd);
232 u32 addr, len;
233 uint32_t rem;
234 int ret;
235
236 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
237 (long long)instr->len);
238
239 div_u64_rem(instr->len, mtd->erasesize, &rem);
240 if (rem)
241 return -EINVAL;
242
243 addr = instr->addr;
244 len = instr->len;
245
246 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
247 if (ret)
248 return ret;
249
250 /* whole-chip erase? */
251 if (len == mtd->size) {
252 if (erase_chip(nor)) {
253 ret = -EIO;
254 goto erase_err;
255 }
256
257 /* REVISIT in some cases we could speed up erasing large regions
258 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
259 * to use "small sector erase", but that's not always optimal.
260 */
261
262 /* "sector"-at-a-time erase */
263 } else {
264 while (len) {
265 if (nor->erase(nor, addr)) {
266 ret = -EIO;
267 goto erase_err;
268 }
269
270 addr += mtd->erasesize;
271 len -= mtd->erasesize;
272 }
273 }
274
275 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
276
277 instr->state = MTD_ERASE_DONE;
278 mtd_erase_callback(instr);
279
280 return ret;
281
282 erase_err:
283 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
284 instr->state = MTD_ERASE_FAILED;
285 return ret;
286 }
287
288 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
289 {
290 struct spi_nor *nor = mtd_to_spi_nor(mtd);
291 uint32_t offset = ofs;
292 uint8_t status_old, status_new;
293 int ret = 0;
294
295 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
296 if (ret)
297 return ret;
298
299 /* Wait until finished previous command */
300 ret = wait_till_ready(nor);
301 if (ret)
302 goto err;
303
304 status_old = read_sr(nor);
305
306 if (offset < mtd->size - (mtd->size / 2))
307 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
308 else if (offset < mtd->size - (mtd->size / 4))
309 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
310 else if (offset < mtd->size - (mtd->size / 8))
311 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
312 else if (offset < mtd->size - (mtd->size / 16))
313 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
314 else if (offset < mtd->size - (mtd->size / 32))
315 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
316 else if (offset < mtd->size - (mtd->size / 64))
317 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
318 else
319 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
320
321 /* Only modify protection if it will not unlock other areas */
322 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
323 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
324 write_enable(nor);
325 ret = write_sr(nor, status_new);
326 if (ret)
327 goto err;
328 }
329
330 err:
331 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
332 return ret;
333 }
334
335 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
336 {
337 struct spi_nor *nor = mtd_to_spi_nor(mtd);
338 uint32_t offset = ofs;
339 uint8_t status_old, status_new;
340 int ret = 0;
341
342 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
343 if (ret)
344 return ret;
345
346 /* Wait until finished previous command */
347 ret = wait_till_ready(nor);
348 if (ret)
349 goto err;
350
351 status_old = read_sr(nor);
352
353 if (offset+len > mtd->size - (mtd->size / 64))
354 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
355 else if (offset+len > mtd->size - (mtd->size / 32))
356 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
357 else if (offset+len > mtd->size - (mtd->size / 16))
358 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
359 else if (offset+len > mtd->size - (mtd->size / 8))
360 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
361 else if (offset+len > mtd->size - (mtd->size / 4))
362 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
363 else if (offset+len > mtd->size - (mtd->size / 2))
364 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
365 else
366 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
367
368 /* Only modify protection if it will not lock other areas */
369 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
370 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
371 write_enable(nor);
372 ret = write_sr(nor, status_new);
373 if (ret)
374 goto err;
375 }
376
377 err:
378 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
379 return ret;
380 }
381
382 struct flash_info {
383 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
384 * a high byte of zero plus three data bytes: the manufacturer id,
385 * then a two byte device id.
386 */
387 u32 jedec_id;
388 u16 ext_id;
389
390 /* The size listed here is what works with SPINOR_OP_SE, which isn't
391 * necessarily called a "sector" by the vendor.
392 */
393 unsigned sector_size;
394 u16 n_sectors;
395
396 u16 page_size;
397 u16 addr_width;
398
399 u16 flags;
400 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
401 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
402 #define SST_WRITE 0x04 /* use SST byte programming */
403 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
404 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
405 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
406 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
407 };
408
409 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
410 ((kernel_ulong_t)&(struct flash_info) { \
411 .jedec_id = (_jedec_id), \
412 .ext_id = (_ext_id), \
413 .sector_size = (_sector_size), \
414 .n_sectors = (_n_sectors), \
415 .page_size = 256, \
416 .flags = (_flags), \
417 })
418
419 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
420 ((kernel_ulong_t)&(struct flash_info) { \
421 .sector_size = (_sector_size), \
422 .n_sectors = (_n_sectors), \
423 .page_size = (_page_size), \
424 .addr_width = (_addr_width), \
425 .flags = (_flags), \
426 })
427
428 /* NOTE: double check command sets and memory organization when you add
429 * more nor chips. This current list focusses on newer chips, which
430 * have been converging on command sets which including JEDEC ID.
431 */
432 static const struct spi_device_id spi_nor_ids[] = {
433 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
434 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
435 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
436
437 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
438 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
439 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
440
441 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
442 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
443 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
444 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
445
446 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
447
448 /* EON -- en25xxx */
449 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
450 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
451 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
452 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
453 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
454 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
455
456 /* ESMT */
457 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
458
459 /* Everspin */
460 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
461 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
462
463 /* GigaDevice */
464 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
465 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
466
467 /* Intel/Numonyx -- xxxs33b */
468 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
469 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
470 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
471
472 /* Macronix */
473 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
474 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
475 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
476 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
477 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
478 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
479 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
480 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
481 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
482 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
483 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
484 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
485 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
486
487 /* Micron */
488 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
489 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
490 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
491 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
492 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
493
494 /* PMC */
495 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
496 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
497 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
498
499 /* Spansion -- single (large) sector size only, at least
500 * for the chips listed here (without boot sectors).
501 */
502 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
503 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
504 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
505 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
506 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
507 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
508 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
509 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
510 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
511 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
512 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
513 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
514 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
515 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
516 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
517 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
518 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
519 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
520
521 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
522 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
523 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
524 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
525 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
526 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
527 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
528 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
529 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
530 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
531
532 /* ST Microelectronics -- newer production may have feature updates */
533 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
534 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
535 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
536 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
537 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
538 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
539 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
540 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
541 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
542 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
543
544 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
545 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
546 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
547 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
548 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
549 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
550 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
551 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
552 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
553
554 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
555 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
556 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
557
558 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
559 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
560 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
561
562 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
563 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
564 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
565 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
566 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
567
568 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
569 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
570 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
571 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
572 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
573 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
574 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
575 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
576 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
577 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
578 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
579 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
580 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
581 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
582 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
583 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
584
585 /* Catalyst / On Semiconductor -- non-JEDEC */
586 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
587 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
588 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
589 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
590 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
591 { },
592 };
593
594 static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
595 {
596 int tmp;
597 u8 id[5];
598 u32 jedec;
599 u16 ext_jedec;
600 struct flash_info *info;
601
602 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
603 if (tmp < 0) {
604 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
605 return ERR_PTR(tmp);
606 }
607 jedec = id[0];
608 jedec = jedec << 8;
609 jedec |= id[1];
610 jedec = jedec << 8;
611 jedec |= id[2];
612
613 ext_jedec = id[3] << 8 | id[4];
614
615 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
616 info = (void *)spi_nor_ids[tmp].driver_data;
617 if (info->jedec_id == jedec) {
618 if (info->ext_id == 0 || info->ext_id == ext_jedec)
619 return &spi_nor_ids[tmp];
620 }
621 }
622 dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
623 return ERR_PTR(-ENODEV);
624 }
625
626 static const struct spi_device_id *jedec_probe(struct spi_nor *nor)
627 {
628 return nor->read_id(nor);
629 }
630
631 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
632 size_t *retlen, u_char *buf)
633 {
634 struct spi_nor *nor = mtd_to_spi_nor(mtd);
635 int ret;
636
637 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
638
639 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
640 if (ret)
641 return ret;
642
643 ret = nor->read(nor, from, len, retlen, buf);
644
645 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
646 return ret;
647 }
648
649 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
650 size_t *retlen, const u_char *buf)
651 {
652 struct spi_nor *nor = mtd_to_spi_nor(mtd);
653 size_t actual;
654 int ret;
655
656 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
657
658 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
659 if (ret)
660 return ret;
661
662 /* Wait until finished previous write command. */
663 ret = wait_till_ready(nor);
664 if (ret)
665 goto time_out;
666
667 write_enable(nor);
668
669 nor->sst_write_second = false;
670
671 actual = to % 2;
672 /* Start write from odd address. */
673 if (actual) {
674 nor->program_opcode = SPINOR_OP_BP;
675
676 /* write one byte. */
677 nor->write(nor, to, 1, retlen, buf);
678 ret = wait_till_ready(nor);
679 if (ret)
680 goto time_out;
681 }
682 to += actual;
683
684 /* Write out most of the data here. */
685 for (; actual < len - 1; actual += 2) {
686 nor->program_opcode = SPINOR_OP_AAI_WP;
687
688 /* write two bytes. */
689 nor->write(nor, to, 2, retlen, buf + actual);
690 ret = wait_till_ready(nor);
691 if (ret)
692 goto time_out;
693 to += 2;
694 nor->sst_write_second = true;
695 }
696 nor->sst_write_second = false;
697
698 write_disable(nor);
699 ret = wait_till_ready(nor);
700 if (ret)
701 goto time_out;
702
703 /* Write out trailing byte if it exists. */
704 if (actual != len) {
705 write_enable(nor);
706
707 nor->program_opcode = SPINOR_OP_BP;
708 nor->write(nor, to, 1, retlen, buf + actual);
709
710 ret = wait_till_ready(nor);
711 if (ret)
712 goto time_out;
713 write_disable(nor);
714 }
715 time_out:
716 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
717 return ret;
718 }
719
720 /*
721 * Write an address range to the nor chip. Data must be written in
722 * FLASH_PAGESIZE chunks. The address range may be any size provided
723 * it is within the physical boundaries.
724 */
725 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
726 size_t *retlen, const u_char *buf)
727 {
728 struct spi_nor *nor = mtd_to_spi_nor(mtd);
729 u32 page_offset, page_size, i;
730 int ret;
731
732 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
733
734 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
735 if (ret)
736 return ret;
737
738 /* Wait until finished previous write command. */
739 ret = wait_till_ready(nor);
740 if (ret)
741 goto write_err;
742
743 write_enable(nor);
744
745 page_offset = to & (nor->page_size - 1);
746
747 /* do all the bytes fit onto one page? */
748 if (page_offset + len <= nor->page_size) {
749 nor->write(nor, to, len, retlen, buf);
750 } else {
751 /* the size of data remaining on the first page */
752 page_size = nor->page_size - page_offset;
753 nor->write(nor, to, page_size, retlen, buf);
754
755 /* write everything in nor->page_size chunks */
756 for (i = page_size; i < len; i += page_size) {
757 page_size = len - i;
758 if (page_size > nor->page_size)
759 page_size = nor->page_size;
760
761 wait_till_ready(nor);
762 write_enable(nor);
763
764 nor->write(nor, to + i, page_size, retlen, buf + i);
765 }
766 }
767
768 write_err:
769 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
770 return 0;
771 }
772
773 static int macronix_quad_enable(struct spi_nor *nor)
774 {
775 int ret, val;
776
777 val = read_sr(nor);
778 write_enable(nor);
779
780 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
781 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
782
783 if (wait_till_ready(nor))
784 return 1;
785
786 ret = read_sr(nor);
787 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
788 dev_err(nor->dev, "Macronix Quad bit not set\n");
789 return -EINVAL;
790 }
791
792 return 0;
793 }
794
795 /*
796 * Write status Register and configuration register with 2 bytes
797 * The first byte will be written to the status register, while the
798 * second byte will be written to the configuration register.
799 * Return negative if error occured.
800 */
801 static int write_sr_cr(struct spi_nor *nor, u16 val)
802 {
803 nor->cmd_buf[0] = val & 0xff;
804 nor->cmd_buf[1] = (val >> 8);
805
806 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
807 }
808
809 static int spansion_quad_enable(struct spi_nor *nor)
810 {
811 int ret;
812 int quad_en = CR_QUAD_EN_SPAN << 8;
813
814 write_enable(nor);
815
816 ret = write_sr_cr(nor, quad_en);
817 if (ret < 0) {
818 dev_err(nor->dev,
819 "error while writing configuration register\n");
820 return -EINVAL;
821 }
822
823 /* read back and check it */
824 ret = read_cr(nor);
825 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
826 dev_err(nor->dev, "Spansion Quad bit not set\n");
827 return -EINVAL;
828 }
829
830 return 0;
831 }
832
833 static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
834 {
835 int status;
836
837 switch (JEDEC_MFR(jedec_id)) {
838 case CFI_MFR_MACRONIX:
839 status = macronix_quad_enable(nor);
840 if (status) {
841 dev_err(nor->dev, "Macronix quad-read not enabled\n");
842 return -EINVAL;
843 }
844 return status;
845 default:
846 status = spansion_quad_enable(nor);
847 if (status) {
848 dev_err(nor->dev, "Spansion quad-read not enabled\n");
849 return -EINVAL;
850 }
851 return status;
852 }
853 }
854
855 static int spi_nor_check(struct spi_nor *nor)
856 {
857 if (!nor->dev || !nor->read || !nor->write ||
858 !nor->read_reg || !nor->write_reg || !nor->erase) {
859 pr_err("spi-nor: please fill all the necessary fields!\n");
860 return -EINVAL;
861 }
862
863 if (!nor->read_id)
864 nor->read_id = spi_nor_read_id;
865 if (!nor->wait_till_ready)
866 nor->wait_till_ready = spi_nor_wait_till_ready;
867
868 return 0;
869 }
870
871 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
872 {
873 const struct spi_device_id *id = NULL;
874 struct flash_info *info;
875 struct device *dev = nor->dev;
876 struct mtd_info *mtd = nor->mtd;
877 struct device_node *np = dev->of_node;
878 int ret;
879 int i;
880
881 ret = spi_nor_check(nor);
882 if (ret)
883 return ret;
884
885 id = spi_nor_match_id(name);
886 if (!id)
887 return -ENOENT;
888
889 info = (void *)id->driver_data;
890
891 if (info->jedec_id) {
892 const struct spi_device_id *jid;
893
894 jid = jedec_probe(nor);
895 if (IS_ERR(jid)) {
896 return PTR_ERR(jid);
897 } else if (jid != id) {
898 /*
899 * JEDEC knows better, so overwrite platform ID. We
900 * can't trust partitions any longer, but we'll let
901 * mtd apply them anyway, since some partitions may be
902 * marked read-only, and we don't want to lose that
903 * information, even if it's not 100% accurate.
904 */
905 dev_warn(dev, "found %s, expected %s\n",
906 jid->name, id->name);
907 id = jid;
908 info = (void *)jid->driver_data;
909 }
910 }
911
912 mutex_init(&nor->lock);
913
914 /*
915 * Atmel, SST and Intel/Numonyx serial nor tend to power
916 * up with the software protection bits set
917 */
918
919 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
920 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
921 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
922 write_enable(nor);
923 write_sr(nor, 0);
924 }
925
926 if (!mtd->name)
927 mtd->name = dev_name(dev);
928 mtd->type = MTD_NORFLASH;
929 mtd->writesize = 1;
930 mtd->flags = MTD_CAP_NORFLASH;
931 mtd->size = info->sector_size * info->n_sectors;
932 mtd->_erase = spi_nor_erase;
933 mtd->_read = spi_nor_read;
934
935 /* nor protection support for STmicro chips */
936 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
937 mtd->_lock = spi_nor_lock;
938 mtd->_unlock = spi_nor_unlock;
939 }
940
941 /* sst nor chips use AAI word program */
942 if (info->flags & SST_WRITE)
943 mtd->_write = sst_write;
944 else
945 mtd->_write = spi_nor_write;
946
947 /* prefer "small sector" erase if possible */
948 if (info->flags & SECT_4K) {
949 nor->erase_opcode = SPINOR_OP_BE_4K;
950 mtd->erasesize = 4096;
951 } else if (info->flags & SECT_4K_PMC) {
952 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
953 mtd->erasesize = 4096;
954 } else {
955 nor->erase_opcode = SPINOR_OP_SE;
956 mtd->erasesize = info->sector_size;
957 }
958
959 if (info->flags & SPI_NOR_NO_ERASE)
960 mtd->flags |= MTD_NO_ERASE;
961
962 mtd->dev.parent = dev;
963 nor->page_size = info->page_size;
964 mtd->writebufsize = nor->page_size;
965
966 if (np) {
967 /* If we were instantiated by DT, use it */
968 if (of_property_read_bool(np, "m25p,fast-read"))
969 nor->flash_read = SPI_NOR_FAST;
970 else
971 nor->flash_read = SPI_NOR_NORMAL;
972 } else {
973 /* If we weren't instantiated by DT, default to fast-read */
974 nor->flash_read = SPI_NOR_FAST;
975 }
976
977 /* Some devices cannot do fast-read, no matter what DT tells us */
978 if (info->flags & SPI_NOR_NO_FR)
979 nor->flash_read = SPI_NOR_NORMAL;
980
981 /* Quad/Dual-read mode takes precedence over fast/normal */
982 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
983 ret = set_quad_mode(nor, info->jedec_id);
984 if (ret) {
985 dev_err(dev, "quad mode not supported\n");
986 return ret;
987 }
988 nor->flash_read = SPI_NOR_QUAD;
989 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
990 nor->flash_read = SPI_NOR_DUAL;
991 }
992
993 /* Default commands */
994 switch (nor->flash_read) {
995 case SPI_NOR_QUAD:
996 nor->read_opcode = SPINOR_OP_READ_1_1_4;
997 break;
998 case SPI_NOR_DUAL:
999 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1000 break;
1001 case SPI_NOR_FAST:
1002 nor->read_opcode = SPINOR_OP_READ_FAST;
1003 break;
1004 case SPI_NOR_NORMAL:
1005 nor->read_opcode = SPINOR_OP_READ;
1006 break;
1007 default:
1008 dev_err(dev, "No Read opcode defined\n");
1009 return -EINVAL;
1010 }
1011
1012 nor->program_opcode = SPINOR_OP_PP;
1013
1014 if (info->addr_width)
1015 nor->addr_width = info->addr_width;
1016 else if (mtd->size > 0x1000000) {
1017 /* enable 4-byte addressing if the device exceeds 16MiB */
1018 nor->addr_width = 4;
1019 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1020 /* Dedicated 4-byte command set */
1021 switch (nor->flash_read) {
1022 case SPI_NOR_QUAD:
1023 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1024 break;
1025 case SPI_NOR_DUAL:
1026 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1027 break;
1028 case SPI_NOR_FAST:
1029 nor->read_opcode = SPINOR_OP_READ4_FAST;
1030 break;
1031 case SPI_NOR_NORMAL:
1032 nor->read_opcode = SPINOR_OP_READ4;
1033 break;
1034 }
1035 nor->program_opcode = SPINOR_OP_PP_4B;
1036 /* No small sector erase for 4-byte command set */
1037 nor->erase_opcode = SPINOR_OP_SE_4B;
1038 mtd->erasesize = info->sector_size;
1039 } else
1040 set_4byte(nor, info->jedec_id, 1);
1041 } else {
1042 nor->addr_width = 3;
1043 }
1044
1045 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1046
1047 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1048 (long long)mtd->size >> 10);
1049
1050 dev_dbg(dev,
1051 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1052 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1053 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1054 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1055
1056 if (mtd->numeraseregions)
1057 for (i = 0; i < mtd->numeraseregions; i++)
1058 dev_dbg(dev,
1059 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1060 ".erasesize = 0x%.8x (%uKiB), "
1061 ".numblocks = %d }\n",
1062 i, (long long)mtd->eraseregions[i].offset,
1063 mtd->eraseregions[i].erasesize,
1064 mtd->eraseregions[i].erasesize / 1024,
1065 mtd->eraseregions[i].numblocks);
1066 return 0;
1067 }
1068 EXPORT_SYMBOL_GPL(spi_nor_scan);
1069
1070 static const struct spi_device_id *spi_nor_match_id(const char *name)
1071 {
1072 const struct spi_device_id *id = spi_nor_ids;
1073
1074 while (id->name[0]) {
1075 if (!strcmp(name, id->name))
1076 return id;
1077 id++;
1078 }
1079 return NULL;
1080 }
1081
1082 MODULE_LICENSE("GPL");
1083 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1084 MODULE_AUTHOR("Mike Lavender");
1085 MODULE_DESCRIPTION("framework for SPI NOR");
Linux with added FPC-III support