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jme: Do not enable NIC WoL functions on S0
[linux/fpc-iii.git] / drivers / net / ethernet / jme.c
blob03aedbff1587a92f598a050b330e60b7d7b18c80
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/pci-aspm.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/crc32.h>
36 #include <linux/delay.h>
37 #include <linux/spinlock.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <linux/ipv6.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/if_vlan.h>
44 #include <linux/slab.h>
45 #include <net/ip6_checksum.h>
46 #include "jme.h"
47
48 static int force_pseudohp = -1;
49 static int no_pseudohp = -1;
50 static int no_extplug = -1;
51 module_param(force_pseudohp, int, 0);
52 MODULE_PARM_DESC(force_pseudohp,
53 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
54 module_param(no_pseudohp, int, 0);
55 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
56 module_param(no_extplug, int, 0);
57 MODULE_PARM_DESC(no_extplug,
58 "Do not use external plug signal for pseudo hot-plug.");
59
60 static int
61 jme_mdio_read(struct net_device *netdev, int phy, int reg)
62 {
63 struct jme_adapter *jme = netdev_priv(netdev);
64 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
65
66 read_again:
67 jwrite32(jme, JME_SMI, SMI_OP_REQ |
68 smi_phy_addr(phy) |
69 smi_reg_addr(reg));
70
71 wmb();
72 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
73 udelay(20);
74 val = jread32(jme, JME_SMI);
75 if ((val & SMI_OP_REQ) == 0)
76 break;
77 }
78
79 if (i == 0) {
80 pr_err("phy(%d) read timeout : %d\n", phy, reg);
81 return 0;
82 }
83
84 if (again--)
85 goto read_again;
86
87 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
88 }
89
90 static void
91 jme_mdio_write(struct net_device *netdev,
92 int phy, int reg, int val)
93 {
94 struct jme_adapter *jme = netdev_priv(netdev);
95 int i;
96
97 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
98 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
99 smi_phy_addr(phy) | smi_reg_addr(reg));
100
101 wmb();
102 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
103 udelay(20);
104 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
105 break;
106 }
107
108 if (i == 0)
109 pr_err("phy(%d) write timeout : %d\n", phy, reg);
110 }
111
112 static inline void
113 jme_reset_phy_processor(struct jme_adapter *jme)
114 {
115 u32 val;
116
117 jme_mdio_write(jme->dev,
118 jme->mii_if.phy_id,
119 MII_ADVERTISE, ADVERTISE_ALL |
120 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
121
122 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
123 jme_mdio_write(jme->dev,
124 jme->mii_if.phy_id,
125 MII_CTRL1000,
126 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
127
128 val = jme_mdio_read(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR);
131
132 jme_mdio_write(jme->dev,
133 jme->mii_if.phy_id,
134 MII_BMCR, val | BMCR_RESET);
135 }
136
137 static void
138 jme_setup_wakeup_frame(struct jme_adapter *jme,
139 const u32 *mask, u32 crc, int fnr)
140 {
141 int i;
142
143 /*
144 * Setup CRC pattern
145 */
146 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 wmb();
148 jwrite32(jme, JME_WFODP, crc);
149 wmb();
150
151 /*
152 * Setup Mask
153 */
154 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
155 jwrite32(jme, JME_WFOI,
156 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
157 (fnr & WFOI_FRAME_SEL));
158 wmb();
159 jwrite32(jme, JME_WFODP, mask[i]);
160 wmb();
161 }
162 }
163
164 static inline void
165 jme_mac_rxclk_off(struct jme_adapter *jme)
166 {
167 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
168 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
169 }
170
171 static inline void
172 jme_mac_rxclk_on(struct jme_adapter *jme)
173 {
174 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
175 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
176 }
177
178 static inline void
179 jme_mac_txclk_off(struct jme_adapter *jme)
180 {
181 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
182 jwrite32f(jme, JME_GHC, jme->reg_ghc);
183 }
184
185 static inline void
186 jme_mac_txclk_on(struct jme_adapter *jme)
187 {
188 u32 speed = jme->reg_ghc & GHC_SPEED;
189 if (speed == GHC_SPEED_1000M)
190 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
191 else
192 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
193 jwrite32f(jme, JME_GHC, jme->reg_ghc);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
200 jwrite32f(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_reset_250A2_workaround(struct jme_adapter *jme)
205 {
206 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
207 GPREG1_RSSPATCH);
208 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
209 }
210
211 static inline void
212 jme_assert_ghc_reset(struct jme_adapter *jme)
213 {
214 jme->reg_ghc |= GHC_SWRST;
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
216 }
217
218 static inline void
219 jme_clear_ghc_reset(struct jme_adapter *jme)
220 {
221 jme->reg_ghc &= ~GHC_SWRST;
222 jwrite32f(jme, JME_GHC, jme->reg_ghc);
223 }
224
225 static inline void
226 jme_reset_mac_processor(struct jme_adapter *jme)
227 {
228 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
229 u32 crc = 0xCDCDCDCD;
230 u32 gpreg0;
231 int i;
232
233 jme_reset_ghc_speed(jme);
234 jme_reset_250A2_workaround(jme);
235
236 jme_mac_rxclk_on(jme);
237 jme_mac_txclk_on(jme);
238 udelay(1);
239 jme_assert_ghc_reset(jme);
240 udelay(1);
241 jme_mac_rxclk_off(jme);
242 jme_mac_txclk_off(jme);
243 udelay(1);
244 jme_clear_ghc_reset(jme);
245 udelay(1);
246 jme_mac_rxclk_on(jme);
247 jme_mac_txclk_on(jme);
248 udelay(1);
249 jme_mac_rxclk_off(jme);
250 jme_mac_txclk_off(jme);
251
252 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
253 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
254 jwrite32(jme, JME_RXQDC, 0x00000000);
255 jwrite32(jme, JME_RXNDA, 0x00000000);
256 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
257 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
258 jwrite32(jme, JME_TXQDC, 0x00000000);
259 jwrite32(jme, JME_TXNDA, 0x00000000);
260
261 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
262 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
263 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
264 jme_setup_wakeup_frame(jme, mask, crc, i);
265 if (jme->fpgaver)
266 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
267 else
268 gpreg0 = GPREG0_DEFAULT;
269 jwrite32(jme, JME_GPREG0, gpreg0);
270 }
271
272 static inline void
273 jme_clear_pm_enable_wol(struct jme_adapter *jme)
274 {
275 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
276 }
277
278 static inline void
279 jme_clear_pm_disable_wol(struct jme_adapter *jme)
280 {
281 jwrite32(jme, JME_PMCS, PMCS_STMASK);
282 }
283
284 static int
285 jme_reload_eeprom(struct jme_adapter *jme)
286 {
287 u32 val;
288 int i;
289
290 val = jread32(jme, JME_SMBCSR);
291
292 if (val & SMBCSR_EEPROMD) {
293 val |= SMBCSR_CNACK;
294 jwrite32(jme, JME_SMBCSR, val);
295 val |= SMBCSR_RELOAD;
296 jwrite32(jme, JME_SMBCSR, val);
297 mdelay(12);
298
299 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
300 mdelay(1);
301 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
302 break;
303 }
304
305 if (i == 0) {
306 pr_err("eeprom reload timeout\n");
307 return -EIO;
308 }
309 }
310
311 return 0;
312 }
313
314 static void
315 jme_load_macaddr(struct net_device *netdev)
316 {
317 struct jme_adapter *jme = netdev_priv(netdev);
318 unsigned char macaddr[ETH_ALEN];
319 u32 val;
320
321 spin_lock_bh(&jme->macaddr_lock);
322 val = jread32(jme, JME_RXUMA_LO);
323 macaddr[0] = (val >> 0) & 0xFF;
324 macaddr[1] = (val >> 8) & 0xFF;
325 macaddr[2] = (val >> 16) & 0xFF;
326 macaddr[3] = (val >> 24) & 0xFF;
327 val = jread32(jme, JME_RXUMA_HI);
328 macaddr[4] = (val >> 0) & 0xFF;
329 macaddr[5] = (val >> 8) & 0xFF;
330 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
331 spin_unlock_bh(&jme->macaddr_lock);
332 }
333
334 static inline void
335 jme_set_rx_pcc(struct jme_adapter *jme, int p)
336 {
337 switch (p) {
338 case PCC_OFF:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P1:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P2:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 case PCC_P3:
354 jwrite32(jme, JME_PCCRX0,
355 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
356 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
357 break;
358 default:
359 break;
360 }
361 wmb();
362
363 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
364 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
365 }
366
367 static void
368 jme_start_irq(struct jme_adapter *jme)
369 {
370 register struct dynpcc_info *dpi = &(jme->dpi);
371
372 jme_set_rx_pcc(jme, PCC_P1);
373 dpi->cur = PCC_P1;
374 dpi->attempt = PCC_P1;
375 dpi->cnt = 0;
376
377 jwrite32(jme, JME_PCCTX,
378 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
379 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
380 PCCTXQ0_EN
381 );
382
383 /*
384 * Enable Interrupts
385 */
386 jwrite32(jme, JME_IENS, INTR_ENABLE);
387 }
388
389 static inline void
390 jme_stop_irq(struct jme_adapter *jme)
391 {
392 /*
393 * Disable Interrupts
394 */
395 jwrite32f(jme, JME_IENC, INTR_ENABLE);
396 }
397
398 static u32
399 jme_linkstat_from_phy(struct jme_adapter *jme)
400 {
401 u32 phylink, bmsr;
402
403 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
404 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
405 if (bmsr & BMSR_ANCOMP)
406 phylink |= PHY_LINK_AUTONEG_COMPLETE;
407
408 return phylink;
409 }
410
411 static inline void
412 jme_set_phyfifo_5level(struct jme_adapter *jme)
413 {
414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
415 }
416
417 static inline void
418 jme_set_phyfifo_8level(struct jme_adapter *jme)
419 {
420 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
421 }
422
423 static int
424 jme_check_link(struct net_device *netdev, int testonly)
425 {
426 struct jme_adapter *jme = netdev_priv(netdev);
427 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
428 char linkmsg[64];
429 int rc = 0;
430
431 linkmsg[0] = '\0';
432
433 if (jme->fpgaver)
434 phylink = jme_linkstat_from_phy(jme);
435 else
436 phylink = jread32(jme, JME_PHY_LINK);
437
438 if (phylink & PHY_LINK_UP) {
439 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
440 /*
441 * If we did not enable AN
442 * Speed/Duplex Info should be obtained from SMI
443 */
444 phylink = PHY_LINK_UP;
445
446 bmcr = jme_mdio_read(jme->dev,
447 jme->mii_if.phy_id,
448 MII_BMCR);
449
450 phylink |= ((bmcr & BMCR_SPEED1000) &&
451 (bmcr & BMCR_SPEED100) == 0) ?
452 PHY_LINK_SPEED_1000M :
453 (bmcr & BMCR_SPEED100) ?
454 PHY_LINK_SPEED_100M :
455 PHY_LINK_SPEED_10M;
456
457 phylink |= (bmcr & BMCR_FULLDPLX) ?
458 PHY_LINK_DUPLEX : 0;
459
460 strcat(linkmsg, "Forced: ");
461 } else {
462 /*
463 * Keep polling for speed/duplex resolve complete
464 */
465 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
466 --cnt) {
467
468 udelay(1);
469
470 if (jme->fpgaver)
471 phylink = jme_linkstat_from_phy(jme);
472 else
473 phylink = jread32(jme, JME_PHY_LINK);
474 }
475 if (!cnt)
476 pr_err("Waiting speed resolve timeout\n");
477
478 strcat(linkmsg, "ANed: ");
479 }
480
481 if (jme->phylink == phylink) {
482 rc = 1;
483 goto out;
484 }
485 if (testonly)
486 goto out;
487
488 jme->phylink = phylink;
489
490 /*
491 * The speed/duplex setting of jme->reg_ghc already cleared
492 * by jme_reset_mac_processor()
493 */
494 switch (phylink & PHY_LINK_SPEED_MASK) {
495 case PHY_LINK_SPEED_10M:
496 jme->reg_ghc |= GHC_SPEED_10M;
497 strcat(linkmsg, "10 Mbps, ");
498 break;
499 case PHY_LINK_SPEED_100M:
500 jme->reg_ghc |= GHC_SPEED_100M;
501 strcat(linkmsg, "100 Mbps, ");
502 break;
503 case PHY_LINK_SPEED_1000M:
504 jme->reg_ghc |= GHC_SPEED_1000M;
505 strcat(linkmsg, "1000 Mbps, ");
506 break;
507 default:
508 break;
509 }
510
511 if (phylink & PHY_LINK_DUPLEX) {
512 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
513 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
514 jme->reg_ghc |= GHC_DPX;
515 } else {
516 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
517 TXMCS_BACKOFF |
518 TXMCS_CARRIERSENSE |
519 TXMCS_COLLISION);
520 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
521 }
522
523 jwrite32(jme, JME_GHC, jme->reg_ghc);
524
525 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
526 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
527 GPREG1_RSSPATCH);
528 if (!(phylink & PHY_LINK_DUPLEX))
529 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
530 switch (phylink & PHY_LINK_SPEED_MASK) {
531 case PHY_LINK_SPEED_10M:
532 jme_set_phyfifo_8level(jme);
533 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
534 break;
535 case PHY_LINK_SPEED_100M:
536 jme_set_phyfifo_5level(jme);
537 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
538 break;
539 case PHY_LINK_SPEED_1000M:
540 jme_set_phyfifo_8level(jme);
541 break;
542 default:
543 break;
544 }
545 }
546 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
547
548 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
549 "Full-Duplex, " :
550 "Half-Duplex, ");
551 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
552 "MDI-X" :
553 "MDI");
554 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
555 netif_carrier_on(netdev);
556 } else {
557 if (testonly)
558 goto out;
559
560 netif_info(jme, link, jme->dev, "Link is down\n");
561 jme->phylink = 0;
562 netif_carrier_off(netdev);
563 }
564
565 out:
566 return rc;
567 }
568
569 static int
570 jme_setup_tx_resources(struct jme_adapter *jme)
571 {
572 struct jme_ring *txring = &(jme->txring[0]);
573
574 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
576 &(txring->dmaalloc),
577 GFP_ATOMIC);
578
579 if (!txring->alloc)
580 goto err_set_null;
581
582 /*
583 * 16 Bytes align
584 */
585 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
586 RING_DESC_ALIGN);
587 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
588 txring->next_to_use = 0;
589 atomic_set(&txring->next_to_clean, 0);
590 atomic_set(&txring->nr_free, jme->tx_ring_size);
591
592 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
593 jme->tx_ring_size, GFP_ATOMIC);
594 if (unlikely(!(txring->bufinf)))
595 goto err_free_txring;
596
597 /*
598 * Initialize Transmit Descriptors
599 */
600 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
601 memset(txring->bufinf, 0,
602 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
603
604 return 0;
605
606 err_free_txring:
607 dma_free_coherent(&(jme->pdev->dev),
608 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
609 txring->alloc,
610 txring->dmaalloc);
611
612 err_set_null:
613 txring->desc = NULL;
614 txring->dmaalloc = 0;
615 txring->dma = 0;
616 txring->bufinf = NULL;
617
618 return -ENOMEM;
619 }
620
621 static void
622 jme_free_tx_resources(struct jme_adapter *jme)
623 {
624 int i;
625 struct jme_ring *txring = &(jme->txring[0]);
626 struct jme_buffer_info *txbi;
627
628 if (txring->alloc) {
629 if (txring->bufinf) {
630 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
631 txbi = txring->bufinf + i;
632 if (txbi->skb) {
633 dev_kfree_skb(txbi->skb);
634 txbi->skb = NULL;
635 }
636 txbi->mapping = 0;
637 txbi->len = 0;
638 txbi->nr_desc = 0;
639 txbi->start_xmit = 0;
640 }
641 kfree(txring->bufinf);
642 }
643
644 dma_free_coherent(&(jme->pdev->dev),
645 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
646 txring->alloc,
647 txring->dmaalloc);
648
649 txring->alloc = NULL;
650 txring->desc = NULL;
651 txring->dmaalloc = 0;
652 txring->dma = 0;
653 txring->bufinf = NULL;
654 }
655 txring->next_to_use = 0;
656 atomic_set(&txring->next_to_clean, 0);
657 atomic_set(&txring->nr_free, 0);
658 }
659
660 static inline void
661 jme_enable_tx_engine(struct jme_adapter *jme)
662 {
663 /*
664 * Select Queue 0
665 */
666 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
667 wmb();
668
669 /*
670 * Setup TX Queue 0 DMA Bass Address
671 */
672 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
673 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
674 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
675
676 /*
677 * Setup TX Descptor Count
678 */
679 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
680
681 /*
682 * Enable TX Engine
683 */
684 wmb();
685 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
686 TXCS_SELECT_QUEUE0 |
687 TXCS_ENABLE);
688
689 /*
690 * Start clock for TX MAC Processor
691 */
692 jme_mac_txclk_on(jme);
693 }
694
695 static inline void
696 jme_restart_tx_engine(struct jme_adapter *jme)
697 {
698 /*
699 * Restart TX Engine
700 */
701 jwrite32(jme, JME_TXCS, jme->reg_txcs |
702 TXCS_SELECT_QUEUE0 |
703 TXCS_ENABLE);
704 }
705
706 static inline void
707 jme_disable_tx_engine(struct jme_adapter *jme)
708 {
709 int i;
710 u32 val;
711
712 /*
713 * Disable TX Engine
714 */
715 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
716 wmb();
717
718 val = jread32(jme, JME_TXCS);
719 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
720 mdelay(1);
721 val = jread32(jme, JME_TXCS);
722 rmb();
723 }
724
725 if (!i)
726 pr_err("Disable TX engine timeout\n");
727
728 /*
729 * Stop clock for TX MAC Processor
730 */
731 jme_mac_txclk_off(jme);
732 }
733
734 static void
735 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
736 {
737 struct jme_ring *rxring = &(jme->rxring[0]);
738 register struct rxdesc *rxdesc = rxring->desc;
739 struct jme_buffer_info *rxbi = rxring->bufinf;
740 rxdesc += i;
741 rxbi += i;
742
743 rxdesc->dw[0] = 0;
744 rxdesc->dw[1] = 0;
745 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
746 rxdesc->desc1.bufaddrl = cpu_to_le32(
747 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
748 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
749 if (jme->dev->features & NETIF_F_HIGHDMA)
750 rxdesc->desc1.flags = RXFLAG_64BIT;
751 wmb();
752 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
753 }
754
755 static int
756 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
757 {
758 struct jme_ring *rxring = &(jme->rxring[0]);
759 struct jme_buffer_info *rxbi = rxring->bufinf + i;
760 struct sk_buff *skb;
761 dma_addr_t mapping;
762
763 skb = netdev_alloc_skb(jme->dev,
764 jme->dev->mtu + RX_EXTRA_LEN);
765 if (unlikely(!skb))
766 return -ENOMEM;
767
768 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
769 offset_in_page(skb->data), skb_tailroom(skb),
770 PCI_DMA_FROMDEVICE);
771 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
772 dev_kfree_skb(skb);
773 return -ENOMEM;
774 }
775
776 if (likely(rxbi->mapping))
777 pci_unmap_page(jme->pdev, rxbi->mapping,
778 rxbi->len, PCI_DMA_FROMDEVICE);
779
780 rxbi->skb = skb;
781 rxbi->len = skb_tailroom(skb);
782 rxbi->mapping = mapping;
783 return 0;
784 }
785
786 static void
787 jme_free_rx_buf(struct jme_adapter *jme, int i)
788 {
789 struct jme_ring *rxring = &(jme->rxring[0]);
790 struct jme_buffer_info *rxbi = rxring->bufinf;
791 rxbi += i;
792
793 if (rxbi->skb) {
794 pci_unmap_page(jme->pdev,
795 rxbi->mapping,
796 rxbi->len,
797 PCI_DMA_FROMDEVICE);
798 dev_kfree_skb(rxbi->skb);
799 rxbi->skb = NULL;
800 rxbi->mapping = 0;
801 rxbi->len = 0;
802 }
803 }
804
805 static void
806 jme_free_rx_resources(struct jme_adapter *jme)
807 {
808 int i;
809 struct jme_ring *rxring = &(jme->rxring[0]);
810
811 if (rxring->alloc) {
812 if (rxring->bufinf) {
813 for (i = 0 ; i < jme->rx_ring_size ; ++i)
814 jme_free_rx_buf(jme, i);
815 kfree(rxring->bufinf);
816 }
817
818 dma_free_coherent(&(jme->pdev->dev),
819 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
820 rxring->alloc,
821 rxring->dmaalloc);
822 rxring->alloc = NULL;
823 rxring->desc = NULL;
824 rxring->dmaalloc = 0;
825 rxring->dma = 0;
826 rxring->bufinf = NULL;
827 }
828 rxring->next_to_use = 0;
829 atomic_set(&rxring->next_to_clean, 0);
830 }
831
832 static int
833 jme_setup_rx_resources(struct jme_adapter *jme)
834 {
835 int i;
836 struct jme_ring *rxring = &(jme->rxring[0]);
837
838 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
839 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
840 &(rxring->dmaalloc),
841 GFP_ATOMIC);
842 if (!rxring->alloc)
843 goto err_set_null;
844
845 /*
846 * 16 Bytes align
847 */
848 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
849 RING_DESC_ALIGN);
850 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
851 rxring->next_to_use = 0;
852 atomic_set(&rxring->next_to_clean, 0);
853
854 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
855 jme->rx_ring_size, GFP_ATOMIC);
856 if (unlikely(!(rxring->bufinf)))
857 goto err_free_rxring;
858
859 /*
860 * Initiallize Receive Descriptors
861 */
862 memset(rxring->bufinf, 0,
863 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
864 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
865 if (unlikely(jme_make_new_rx_buf(jme, i))) {
866 jme_free_rx_resources(jme);
867 return -ENOMEM;
868 }
869
870 jme_set_clean_rxdesc(jme, i);
871 }
872
873 return 0;
874
875 err_free_rxring:
876 dma_free_coherent(&(jme->pdev->dev),
877 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
878 rxring->alloc,
879 rxring->dmaalloc);
880 err_set_null:
881 rxring->desc = NULL;
882 rxring->dmaalloc = 0;
883 rxring->dma = 0;
884 rxring->bufinf = NULL;
885
886 return -ENOMEM;
887 }
888
889 static inline void
890 jme_enable_rx_engine(struct jme_adapter *jme)
891 {
892 /*
893 * Select Queue 0
894 */
895 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
896 RXCS_QUEUESEL_Q0);
897 wmb();
898
899 /*
900 * Setup RX DMA Bass Address
901 */
902 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
903 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
904 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
905
906 /*
907 * Setup RX Descriptor Count
908 */
909 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
910
911 /*
912 * Setup Unicast Filter
913 */
914 jme_set_unicastaddr(jme->dev);
915 jme_set_multi(jme->dev);
916
917 /*
918 * Enable RX Engine
919 */
920 wmb();
921 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
922 RXCS_QUEUESEL_Q0 |
923 RXCS_ENABLE |
924 RXCS_QST);
925
926 /*
927 * Start clock for RX MAC Processor
928 */
929 jme_mac_rxclk_on(jme);
930 }
931
932 static inline void
933 jme_restart_rx_engine(struct jme_adapter *jme)
934 {
935 /*
936 * Start RX Engine
937 */
938 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
939 RXCS_QUEUESEL_Q0 |
940 RXCS_ENABLE |
941 RXCS_QST);
942 }
943
944 static inline void
945 jme_disable_rx_engine(struct jme_adapter *jme)
946 {
947 int i;
948 u32 val;
949
950 /*
951 * Disable RX Engine
952 */
953 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
954 wmb();
955
956 val = jread32(jme, JME_RXCS);
957 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
958 mdelay(1);
959 val = jread32(jme, JME_RXCS);
960 rmb();
961 }
962
963 if (!i)
964 pr_err("Disable RX engine timeout\n");
965
966 /*
967 * Stop clock for RX MAC Processor
968 */
969 jme_mac_rxclk_off(jme);
970 }
971
972 static u16
973 jme_udpsum(struct sk_buff *skb)
974 {
975 u16 csum = 0xFFFFu;
976
977 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
978 return csum;
979 if (skb->protocol != htons(ETH_P_IP))
980 return csum;
981 skb_set_network_header(skb, ETH_HLEN);
982 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
983 (skb->len < (ETH_HLEN +
984 (ip_hdr(skb)->ihl << 2) +
985 sizeof(struct udphdr)))) {
986 skb_reset_network_header(skb);
987 return csum;
988 }
989 skb_set_transport_header(skb,
990 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
991 csum = udp_hdr(skb)->check;
992 skb_reset_transport_header(skb);
993 skb_reset_network_header(skb);
994
995 return csum;
996 }
997
998 static int
999 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1000 {
1001 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1002 return false;
1003
1004 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1005 == RXWBFLAG_TCPON)) {
1006 if (flags & RXWBFLAG_IPV4)
1007 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1008 return false;
1009 }
1010
1011 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1012 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1013 if (flags & RXWBFLAG_IPV4)
1014 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1015 return false;
1016 }
1017
1018 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1019 == RXWBFLAG_IPV4)) {
1020 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1021 return false;
1022 }
1023
1024 return true;
1025 }
1026
1027 static void
1028 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1029 {
1030 struct jme_ring *rxring = &(jme->rxring[0]);
1031 struct rxdesc *rxdesc = rxring->desc;
1032 struct jme_buffer_info *rxbi = rxring->bufinf;
1033 struct sk_buff *skb;
1034 int framesize;
1035
1036 rxdesc += idx;
1037 rxbi += idx;
1038
1039 skb = rxbi->skb;
1040 pci_dma_sync_single_for_cpu(jme->pdev,
1041 rxbi->mapping,
1042 rxbi->len,
1043 PCI_DMA_FROMDEVICE);
1044
1045 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1046 pci_dma_sync_single_for_device(jme->pdev,
1047 rxbi->mapping,
1048 rxbi->len,
1049 PCI_DMA_FROMDEVICE);
1050
1051 ++(NET_STAT(jme).rx_dropped);
1052 } else {
1053 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1054 - RX_PREPAD_SIZE;
1055
1056 skb_reserve(skb, RX_PREPAD_SIZE);
1057 skb_put(skb, framesize);
1058 skb->protocol = eth_type_trans(skb, jme->dev);
1059
1060 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1061 skb->ip_summed = CHECKSUM_UNNECESSARY;
1062 else
1063 skb_checksum_none_assert(skb);
1064
1065 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1066 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1067
1068 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1069 NET_STAT(jme).rx_bytes += 4;
1070 }
1071 jme->jme_rx(skb);
1072
1073 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1074 cpu_to_le16(RXWBFLAG_DEST_MUL))
1075 ++(NET_STAT(jme).multicast);
1076
1077 NET_STAT(jme).rx_bytes += framesize;
1078 ++(NET_STAT(jme).rx_packets);
1079 }
1080
1081 jme_set_clean_rxdesc(jme, idx);
1082
1083 }
1084
1085 static int
1086 jme_process_receive(struct jme_adapter *jme, int limit)
1087 {
1088 struct jme_ring *rxring = &(jme->rxring[0]);
1089 struct rxdesc *rxdesc = rxring->desc;
1090 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1091
1092 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1093 goto out_inc;
1094
1095 if (unlikely(atomic_read(&jme->link_changing) != 1))
1096 goto out_inc;
1097
1098 if (unlikely(!netif_carrier_ok(jme->dev)))
1099 goto out_inc;
1100
1101 i = atomic_read(&rxring->next_to_clean);
1102 while (limit > 0) {
1103 rxdesc = rxring->desc;
1104 rxdesc += i;
1105
1106 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1107 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1108 goto out;
1109 --limit;
1110
1111 rmb();
1112 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1113
1114 if (unlikely(desccnt > 1 ||
1115 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1116
1117 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1118 ++(NET_STAT(jme).rx_crc_errors);
1119 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1120 ++(NET_STAT(jme).rx_fifo_errors);
1121 else
1122 ++(NET_STAT(jme).rx_errors);
1123
1124 if (desccnt > 1)
1125 limit -= desccnt - 1;
1126
1127 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1128 jme_set_clean_rxdesc(jme, j);
1129 j = (j + 1) & (mask);
1130 }
1131
1132 } else {
1133 jme_alloc_and_feed_skb(jme, i);
1134 }
1135
1136 i = (i + desccnt) & (mask);
1137 }
1138
1139 out:
1140 atomic_set(&rxring->next_to_clean, i);
1141
1142 out_inc:
1143 atomic_inc(&jme->rx_cleaning);
1144
1145 return limit > 0 ? limit : 0;
1146
1147 }
1148
1149 static void
1150 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1151 {
1152 if (likely(atmp == dpi->cur)) {
1153 dpi->cnt = 0;
1154 return;
1155 }
1156
1157 if (dpi->attempt == atmp) {
1158 ++(dpi->cnt);
1159 } else {
1160 dpi->attempt = atmp;
1161 dpi->cnt = 0;
1162 }
1163
1164 }
1165
1166 static void
1167 jme_dynamic_pcc(struct jme_adapter *jme)
1168 {
1169 register struct dynpcc_info *dpi = &(jme->dpi);
1170
1171 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1172 jme_attempt_pcc(dpi, PCC_P3);
1173 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1174 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1175 jme_attempt_pcc(dpi, PCC_P2);
1176 else
1177 jme_attempt_pcc(dpi, PCC_P1);
1178
1179 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1180 if (dpi->attempt < dpi->cur)
1181 tasklet_schedule(&jme->rxclean_task);
1182 jme_set_rx_pcc(jme, dpi->attempt);
1183 dpi->cur = dpi->attempt;
1184 dpi->cnt = 0;
1185 }
1186 }
1187
1188 static void
1189 jme_start_pcc_timer(struct jme_adapter *jme)
1190 {
1191 struct dynpcc_info *dpi = &(jme->dpi);
1192 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1193 dpi->last_pkts = NET_STAT(jme).rx_packets;
1194 dpi->intr_cnt = 0;
1195 jwrite32(jme, JME_TMCSR,
1196 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1197 }
1198
1199 static inline void
1200 jme_stop_pcc_timer(struct jme_adapter *jme)
1201 {
1202 jwrite32(jme, JME_TMCSR, 0);
1203 }
1204
1205 static void
1206 jme_shutdown_nic(struct jme_adapter *jme)
1207 {
1208 u32 phylink;
1209
1210 phylink = jme_linkstat_from_phy(jme);
1211
1212 if (!(phylink & PHY_LINK_UP)) {
1213 /*
1214 * Disable all interrupt before issue timer
1215 */
1216 jme_stop_irq(jme);
1217 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1218 }
1219 }
1220
1221 static void
1222 jme_pcc_tasklet(unsigned long arg)
1223 {
1224 struct jme_adapter *jme = (struct jme_adapter *)arg;
1225 struct net_device *netdev = jme->dev;
1226
1227 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1228 jme_shutdown_nic(jme);
1229 return;
1230 }
1231
1232 if (unlikely(!netif_carrier_ok(netdev) ||
1233 (atomic_read(&jme->link_changing) != 1)
1234 )) {
1235 jme_stop_pcc_timer(jme);
1236 return;
1237 }
1238
1239 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1240 jme_dynamic_pcc(jme);
1241
1242 jme_start_pcc_timer(jme);
1243 }
1244
1245 static inline void
1246 jme_polling_mode(struct jme_adapter *jme)
1247 {
1248 jme_set_rx_pcc(jme, PCC_OFF);
1249 }
1250
1251 static inline void
1252 jme_interrupt_mode(struct jme_adapter *jme)
1253 {
1254 jme_set_rx_pcc(jme, PCC_P1);
1255 }
1256
1257 static inline int
1258 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1259 {
1260 u32 apmc;
1261 apmc = jread32(jme, JME_APMC);
1262 return apmc & JME_APMC_PSEUDO_HP_EN;
1263 }
1264
1265 static void
1266 jme_start_shutdown_timer(struct jme_adapter *jme)
1267 {
1268 u32 apmc;
1269
1270 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1271 apmc &= ~JME_APMC_EPIEN_CTRL;
1272 if (!no_extplug) {
1273 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1274 wmb();
1275 }
1276 jwrite32f(jme, JME_APMC, apmc);
1277
1278 jwrite32f(jme, JME_TIMER2, 0);
1279 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1280 jwrite32(jme, JME_TMCSR,
1281 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1282 }
1283
1284 static void
1285 jme_stop_shutdown_timer(struct jme_adapter *jme)
1286 {
1287 u32 apmc;
1288
1289 jwrite32f(jme, JME_TMCSR, 0);
1290 jwrite32f(jme, JME_TIMER2, 0);
1291 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1292
1293 apmc = jread32(jme, JME_APMC);
1294 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1295 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1296 wmb();
1297 jwrite32f(jme, JME_APMC, apmc);
1298 }
1299
1300 static void
1301 jme_link_change_tasklet(unsigned long arg)
1302 {
1303 struct jme_adapter *jme = (struct jme_adapter *)arg;
1304 struct net_device *netdev = jme->dev;
1305 int rc;
1306
1307 while (!atomic_dec_and_test(&jme->link_changing)) {
1308 atomic_inc(&jme->link_changing);
1309 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1310 while (atomic_read(&jme->link_changing) != 1)
1311 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1312 }
1313
1314 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1315 goto out;
1316
1317 jme->old_mtu = netdev->mtu;
1318 netif_stop_queue(netdev);
1319 if (jme_pseudo_hotplug_enabled(jme))
1320 jme_stop_shutdown_timer(jme);
1321
1322 jme_stop_pcc_timer(jme);
1323 tasklet_disable(&jme->txclean_task);
1324 tasklet_disable(&jme->rxclean_task);
1325 tasklet_disable(&jme->rxempty_task);
1326
1327 if (netif_carrier_ok(netdev)) {
1328 jme_disable_rx_engine(jme);
1329 jme_disable_tx_engine(jme);
1330 jme_reset_mac_processor(jme);
1331 jme_free_rx_resources(jme);
1332 jme_free_tx_resources(jme);
1333
1334 if (test_bit(JME_FLAG_POLL, &jme->flags))
1335 jme_polling_mode(jme);
1336
1337 netif_carrier_off(netdev);
1338 }
1339
1340 jme_check_link(netdev, 0);
1341 if (netif_carrier_ok(netdev)) {
1342 rc = jme_setup_rx_resources(jme);
1343 if (rc) {
1344 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1345 goto out_enable_tasklet;
1346 }
1347
1348 rc = jme_setup_tx_resources(jme);
1349 if (rc) {
1350 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1351 goto err_out_free_rx_resources;
1352 }
1353
1354 jme_enable_rx_engine(jme);
1355 jme_enable_tx_engine(jme);
1356
1357 netif_start_queue(netdev);
1358
1359 if (test_bit(JME_FLAG_POLL, &jme->flags))
1360 jme_interrupt_mode(jme);
1361
1362 jme_start_pcc_timer(jme);
1363 } else if (jme_pseudo_hotplug_enabled(jme)) {
1364 jme_start_shutdown_timer(jme);
1365 }
1366
1367 goto out_enable_tasklet;
1368
1369 err_out_free_rx_resources:
1370 jme_free_rx_resources(jme);
1371 out_enable_tasklet:
1372 tasklet_enable(&jme->txclean_task);
1373 tasklet_hi_enable(&jme->rxclean_task);
1374 tasklet_hi_enable(&jme->rxempty_task);
1375 out:
1376 atomic_inc(&jme->link_changing);
1377 }
1378
1379 static void
1380 jme_rx_clean_tasklet(unsigned long arg)
1381 {
1382 struct jme_adapter *jme = (struct jme_adapter *)arg;
1383 struct dynpcc_info *dpi = &(jme->dpi);
1384
1385 jme_process_receive(jme, jme->rx_ring_size);
1386 ++(dpi->intr_cnt);
1387
1388 }
1389
1390 static int
1391 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1392 {
1393 struct jme_adapter *jme = jme_napi_priv(holder);
1394 int rest;
1395
1396 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1397
1398 while (atomic_read(&jme->rx_empty) > 0) {
1399 atomic_dec(&jme->rx_empty);
1400 ++(NET_STAT(jme).rx_dropped);
1401 jme_restart_rx_engine(jme);
1402 }
1403 atomic_inc(&jme->rx_empty);
1404
1405 if (rest) {
1406 JME_RX_COMPLETE(netdev, holder);
1407 jme_interrupt_mode(jme);
1408 }
1409
1410 JME_NAPI_WEIGHT_SET(budget, rest);
1411 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1412 }
1413
1414 static void
1415 jme_rx_empty_tasklet(unsigned long arg)
1416 {
1417 struct jme_adapter *jme = (struct jme_adapter *)arg;
1418
1419 if (unlikely(atomic_read(&jme->link_changing) != 1))
1420 return;
1421
1422 if (unlikely(!netif_carrier_ok(jme->dev)))
1423 return;
1424
1425 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1426
1427 jme_rx_clean_tasklet(arg);
1428
1429 while (atomic_read(&jme->rx_empty) > 0) {
1430 atomic_dec(&jme->rx_empty);
1431 ++(NET_STAT(jme).rx_dropped);
1432 jme_restart_rx_engine(jme);
1433 }
1434 atomic_inc(&jme->rx_empty);
1435 }
1436
1437 static void
1438 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1439 {
1440 struct jme_ring *txring = &(jme->txring[0]);
1441
1442 smp_wmb();
1443 if (unlikely(netif_queue_stopped(jme->dev) &&
1444 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1445 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1446 netif_wake_queue(jme->dev);
1447 }
1448
1449 }
1450
1451 static void
1452 jme_tx_clean_tasklet(unsigned long arg)
1453 {
1454 struct jme_adapter *jme = (struct jme_adapter *)arg;
1455 struct jme_ring *txring = &(jme->txring[0]);
1456 struct txdesc *txdesc = txring->desc;
1457 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1458 int i, j, cnt = 0, max, err, mask;
1459
1460 tx_dbg(jme, "Into txclean\n");
1461
1462 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1463 goto out;
1464
1465 if (unlikely(atomic_read(&jme->link_changing) != 1))
1466 goto out;
1467
1468 if (unlikely(!netif_carrier_ok(jme->dev)))
1469 goto out;
1470
1471 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1472 mask = jme->tx_ring_mask;
1473
1474 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1475
1476 ctxbi = txbi + i;
1477
1478 if (likely(ctxbi->skb &&
1479 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1480
1481 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1482 i, ctxbi->nr_desc, jiffies);
1483
1484 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1485
1486 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1487 ttxbi = txbi + ((i + j) & (mask));
1488 txdesc[(i + j) & (mask)].dw[0] = 0;
1489
1490 pci_unmap_page(jme->pdev,
1491 ttxbi->mapping,
1492 ttxbi->len,
1493 PCI_DMA_TODEVICE);
1494
1495 ttxbi->mapping = 0;
1496 ttxbi->len = 0;
1497 }
1498
1499 dev_kfree_skb(ctxbi->skb);
1500
1501 cnt += ctxbi->nr_desc;
1502
1503 if (unlikely(err)) {
1504 ++(NET_STAT(jme).tx_carrier_errors);
1505 } else {
1506 ++(NET_STAT(jme).tx_packets);
1507 NET_STAT(jme).tx_bytes += ctxbi->len;
1508 }
1509
1510 ctxbi->skb = NULL;
1511 ctxbi->len = 0;
1512 ctxbi->start_xmit = 0;
1513
1514 } else {
1515 break;
1516 }
1517
1518 i = (i + ctxbi->nr_desc) & mask;
1519
1520 ctxbi->nr_desc = 0;
1521 }
1522
1523 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1524 atomic_set(&txring->next_to_clean, i);
1525 atomic_add(cnt, &txring->nr_free);
1526
1527 jme_wake_queue_if_stopped(jme);
1528
1529 out:
1530 atomic_inc(&jme->tx_cleaning);
1531 }
1532
1533 static void
1534 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1535 {
1536 /*
1537 * Disable interrupt
1538 */
1539 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1540
1541 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1542 /*
1543 * Link change event is critical
1544 * all other events are ignored
1545 */
1546 jwrite32(jme, JME_IEVE, intrstat);
1547 tasklet_schedule(&jme->linkch_task);
1548 goto out_reenable;
1549 }
1550
1551 if (intrstat & INTR_TMINTR) {
1552 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1553 tasklet_schedule(&jme->pcc_task);
1554 }
1555
1556 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1557 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1558 tasklet_schedule(&jme->txclean_task);
1559 }
1560
1561 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1562 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1563 INTR_PCCRX0 |
1564 INTR_RX0EMP)) |
1565 INTR_RX0);
1566 }
1567
1568 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1569 if (intrstat & INTR_RX0EMP)
1570 atomic_inc(&jme->rx_empty);
1571
1572 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1573 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1574 jme_polling_mode(jme);
1575 JME_RX_SCHEDULE(jme);
1576 }
1577 }
1578 } else {
1579 if (intrstat & INTR_RX0EMP) {
1580 atomic_inc(&jme->rx_empty);
1581 tasklet_hi_schedule(&jme->rxempty_task);
1582 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1583 tasklet_hi_schedule(&jme->rxclean_task);
1584 }
1585 }
1586
1587 out_reenable:
1588 /*
1589 * Re-enable interrupt
1590 */
1591 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1592 }
1593
1594 static irqreturn_t
1595 jme_intr(int irq, void *dev_id)
1596 {
1597 struct net_device *netdev = dev_id;
1598 struct jme_adapter *jme = netdev_priv(netdev);
1599 u32 intrstat;
1600
1601 intrstat = jread32(jme, JME_IEVE);
1602
1603 /*
1604 * Check if it's really an interrupt for us
1605 */
1606 if (unlikely((intrstat & INTR_ENABLE) == 0))
1607 return IRQ_NONE;
1608
1609 /*
1610 * Check if the device still exist
1611 */
1612 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1613 return IRQ_NONE;
1614
1615 jme_intr_msi(jme, intrstat);
1616
1617 return IRQ_HANDLED;
1618 }
1619
1620 static irqreturn_t
1621 jme_msi(int irq, void *dev_id)
1622 {
1623 struct net_device *netdev = dev_id;
1624 struct jme_adapter *jme = netdev_priv(netdev);
1625 u32 intrstat;
1626
1627 intrstat = jread32(jme, JME_IEVE);
1628
1629 jme_intr_msi(jme, intrstat);
1630
1631 return IRQ_HANDLED;
1632 }
1633
1634 static void
1635 jme_reset_link(struct jme_adapter *jme)
1636 {
1637 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1638 }
1639
1640 static void
1641 jme_restart_an(struct jme_adapter *jme)
1642 {
1643 u32 bmcr;
1644
1645 spin_lock_bh(&jme->phy_lock);
1646 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1647 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1648 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1649 spin_unlock_bh(&jme->phy_lock);
1650 }
1651
1652 static int
1653 jme_request_irq(struct jme_adapter *jme)
1654 {
1655 int rc;
1656 struct net_device *netdev = jme->dev;
1657 irq_handler_t handler = jme_intr;
1658 int irq_flags = IRQF_SHARED;
1659
1660 if (!pci_enable_msi(jme->pdev)) {
1661 set_bit(JME_FLAG_MSI, &jme->flags);
1662 handler = jme_msi;
1663 irq_flags = 0;
1664 }
1665
1666 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1667 netdev);
1668 if (rc) {
1669 netdev_err(netdev,
1670 "Unable to request %s interrupt (return: %d)\n",
1671 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1672 rc);
1673
1674 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1675 pci_disable_msi(jme->pdev);
1676 clear_bit(JME_FLAG_MSI, &jme->flags);
1677 }
1678 } else {
1679 netdev->irq = jme->pdev->irq;
1680 }
1681
1682 return rc;
1683 }
1684
1685 static void
1686 jme_free_irq(struct jme_adapter *jme)
1687 {
1688 free_irq(jme->pdev->irq, jme->dev);
1689 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1690 pci_disable_msi(jme->pdev);
1691 clear_bit(JME_FLAG_MSI, &jme->flags);
1692 jme->dev->irq = jme->pdev->irq;
1693 }
1694 }
1695
1696 static inline void
1697 jme_new_phy_on(struct jme_adapter *jme)
1698 {
1699 u32 reg;
1700
1701 reg = jread32(jme, JME_PHY_PWR);
1702 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1703 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1704 jwrite32(jme, JME_PHY_PWR, reg);
1705
1706 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1707 reg &= ~PE1_GPREG0_PBG;
1708 reg |= PE1_GPREG0_ENBG;
1709 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1710 }
1711
1712 static inline void
1713 jme_new_phy_off(struct jme_adapter *jme)
1714 {
1715 u32 reg;
1716
1717 reg = jread32(jme, JME_PHY_PWR);
1718 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1719 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1720 jwrite32(jme, JME_PHY_PWR, reg);
1721
1722 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1723 reg &= ~PE1_GPREG0_PBG;
1724 reg |= PE1_GPREG0_PDD3COLD;
1725 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1726 }
1727
1728 static inline void
1729 jme_phy_on(struct jme_adapter *jme)
1730 {
1731 u32 bmcr;
1732
1733 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1734 bmcr &= ~BMCR_PDOWN;
1735 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1736
1737 if (new_phy_power_ctrl(jme->chip_main_rev))
1738 jme_new_phy_on(jme);
1739 }
1740
1741 static inline void
1742 jme_phy_off(struct jme_adapter *jme)
1743 {
1744 u32 bmcr;
1745
1746 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1747 bmcr |= BMCR_PDOWN;
1748 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1749
1750 if (new_phy_power_ctrl(jme->chip_main_rev))
1751 jme_new_phy_off(jme);
1752 }
1753
1754 static int
1755 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1756 {
1757 u32 phy_addr;
1758
1759 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1760 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1761 phy_addr);
1762 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1763 JM_PHY_SPEC_DATA_REG);
1764 }
1765
1766 static void
1767 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1768 {
1769 u32 phy_addr;
1770
1771 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1772 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1773 phy_data);
1774 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1775 phy_addr);
1776 }
1777
1778 static int
1779 jme_phy_calibration(struct jme_adapter *jme)
1780 {
1781 u32 ctrl1000, phy_data;
1782
1783 jme_phy_off(jme);
1784 jme_phy_on(jme);
1785 /* Enabel PHY test mode 1 */
1786 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1787 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1788 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1789 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1790
1791 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1792 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1793 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1794 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1795 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1796 msleep(20);
1797 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1798 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1799 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1800 JM_PHY_EXT_COMM_2_CALI_LATCH);
1801 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1802
1803 /* Disable PHY test mode */
1804 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1805 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1806 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1807 return 0;
1808 }
1809
1810 static int
1811 jme_phy_setEA(struct jme_adapter *jme)
1812 {
1813 u32 phy_comm0 = 0, phy_comm1 = 0;
1814 u8 nic_ctrl;
1815
1816 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1817 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1818 return 0;
1819
1820 switch (jme->pdev->device) {
1821 case PCI_DEVICE_ID_JMICRON_JMC250:
1822 if (((jme->chip_main_rev == 5) &&
1823 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1824 (jme->chip_sub_rev == 3))) ||
1825 (jme->chip_main_rev >= 6)) {
1826 phy_comm0 = 0x008A;
1827 phy_comm1 = 0x4109;
1828 }
1829 if ((jme->chip_main_rev == 3) &&
1830 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1831 phy_comm0 = 0xE088;
1832 break;
1833 case PCI_DEVICE_ID_JMICRON_JMC260:
1834 if (((jme->chip_main_rev == 5) &&
1835 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1836 (jme->chip_sub_rev == 3))) ||
1837 (jme->chip_main_rev >= 6)) {
1838 phy_comm0 = 0x008A;
1839 phy_comm1 = 0x4109;
1840 }
1841 if ((jme->chip_main_rev == 3) &&
1842 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1843 phy_comm0 = 0xE088;
1844 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1845 phy_comm0 = 0x608A;
1846 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1847 phy_comm0 = 0x408A;
1848 break;
1849 default:
1850 return -ENODEV;
1851 }
1852 if (phy_comm0)
1853 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1854 if (phy_comm1)
1855 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1856
1857 return 0;
1858 }
1859
1860 static int
1861 jme_open(struct net_device *netdev)
1862 {
1863 struct jme_adapter *jme = netdev_priv(netdev);
1864 int rc;
1865
1866 jme_clear_pm_disable_wol(jme);
1867 JME_NAPI_ENABLE(jme);
1868
1869 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1870 (unsigned long) jme);
1871 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1872 (unsigned long) jme);
1873 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1874 (unsigned long) jme);
1875 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1876 (unsigned long) jme);
1877
1878 rc = jme_request_irq(jme);
1879 if (rc)
1880 goto err_out;
1881
1882 jme_start_irq(jme);
1883
1884 jme_phy_on(jme);
1885 if (test_bit(JME_FLAG_SSET, &jme->flags))
1886 jme_set_settings(netdev, &jme->old_ecmd);
1887 else
1888 jme_reset_phy_processor(jme);
1889 jme_phy_calibration(jme);
1890 jme_phy_setEA(jme);
1891 jme_reset_link(jme);
1892
1893 return 0;
1894
1895 err_out:
1896 netif_stop_queue(netdev);
1897 netif_carrier_off(netdev);
1898 return rc;
1899 }
1900
1901 static void
1902 jme_set_100m_half(struct jme_adapter *jme)
1903 {
1904 u32 bmcr, tmp;
1905
1906 jme_phy_on(jme);
1907 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1908 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1909 BMCR_SPEED1000 | BMCR_FULLDPLX);
1910 tmp |= BMCR_SPEED100;
1911
1912 if (bmcr != tmp)
1913 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1914
1915 if (jme->fpgaver)
1916 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1917 else
1918 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1919 }
1920
1921 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1922 static void
1923 jme_wait_link(struct jme_adapter *jme)
1924 {
1925 u32 phylink, to = JME_WAIT_LINK_TIME;
1926
1927 mdelay(1000);
1928 phylink = jme_linkstat_from_phy(jme);
1929 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1930 mdelay(10);
1931 phylink = jme_linkstat_from_phy(jme);
1932 }
1933 }
1934
1935 static void
1936 jme_powersave_phy(struct jme_adapter *jme)
1937 {
1938 if (jme->reg_pmcs) {
1939 jme_set_100m_half(jme);
1940 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1941 jme_wait_link(jme);
1942 jme_clear_pm_enable_wol(jme);
1943 } else {
1944 jme_phy_off(jme);
1945 }
1946 }
1947
1948 static int
1949 jme_close(struct net_device *netdev)
1950 {
1951 struct jme_adapter *jme = netdev_priv(netdev);
1952
1953 netif_stop_queue(netdev);
1954 netif_carrier_off(netdev);
1955
1956 jme_stop_irq(jme);
1957 jme_free_irq(jme);
1958
1959 JME_NAPI_DISABLE(jme);
1960
1961 tasklet_kill(&jme->linkch_task);
1962 tasklet_kill(&jme->txclean_task);
1963 tasklet_kill(&jme->rxclean_task);
1964 tasklet_kill(&jme->rxempty_task);
1965
1966 jme_disable_rx_engine(jme);
1967 jme_disable_tx_engine(jme);
1968 jme_reset_mac_processor(jme);
1969 jme_free_rx_resources(jme);
1970 jme_free_tx_resources(jme);
1971 jme->phylink = 0;
1972 jme_phy_off(jme);
1973
1974 return 0;
1975 }
1976
1977 static int
1978 jme_alloc_txdesc(struct jme_adapter *jme,
1979 struct sk_buff *skb)
1980 {
1981 struct jme_ring *txring = &(jme->txring[0]);
1982 int idx, nr_alloc, mask = jme->tx_ring_mask;
1983
1984 idx = txring->next_to_use;
1985 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1986
1987 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1988 return -1;
1989
1990 atomic_sub(nr_alloc, &txring->nr_free);
1991
1992 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1993
1994 return idx;
1995 }
1996
1997 static int
1998 jme_fill_tx_map(struct pci_dev *pdev,
1999 struct txdesc *txdesc,
2000 struct jme_buffer_info *txbi,
2001 struct page *page,
2002 u32 page_offset,
2003 u32 len,
2004 bool hidma)
2005 {
2006 dma_addr_t dmaaddr;
2007
2008 dmaaddr = pci_map_page(pdev,
2009 page,
2010 page_offset,
2011 len,
2012 PCI_DMA_TODEVICE);
2013
2014 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
2015 return -EINVAL;
2016
2017 pci_dma_sync_single_for_device(pdev,
2018 dmaaddr,
2019 len,
2020 PCI_DMA_TODEVICE);
2021
2022 txdesc->dw[0] = 0;
2023 txdesc->dw[1] = 0;
2024 txdesc->desc2.flags = TXFLAG_OWN;
2025 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
2026 txdesc->desc2.datalen = cpu_to_le16(len);
2027 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2028 txdesc->desc2.bufaddrl = cpu_to_le32(
2029 (__u64)dmaaddr & 0xFFFFFFFFUL);
2030
2031 txbi->mapping = dmaaddr;
2032 txbi->len = len;
2033 return 0;
2034 }
2035
2036 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2037 {
2038 struct jme_ring *txring = &(jme->txring[0]);
2039 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2040 int mask = jme->tx_ring_mask;
2041 int j;
2042
2043 for (j = 0 ; j < count ; j++) {
2044 ctxbi = txbi + ((startidx + j + 2) & (mask));
2045 pci_unmap_page(jme->pdev,
2046 ctxbi->mapping,
2047 ctxbi->len,
2048 PCI_DMA_TODEVICE);
2049
2050 ctxbi->mapping = 0;
2051 ctxbi->len = 0;
2052 }
2053
2054 }
2055
2056 static int
2057 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2058 {
2059 struct jme_ring *txring = &(jme->txring[0]);
2060 struct txdesc *txdesc = txring->desc, *ctxdesc;
2061 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2062 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2063 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2064 int mask = jme->tx_ring_mask;
2065 const struct skb_frag_struct *frag;
2066 u32 len;
2067 int ret = 0;
2068
2069 for (i = 0 ; i < nr_frags ; ++i) {
2070 frag = &skb_shinfo(skb)->frags[i];
2071 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2072 ctxbi = txbi + ((idx + i + 2) & (mask));
2073
2074 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2075 skb_frag_page(frag),
2076 frag->page_offset, skb_frag_size(frag), hidma);
2077 if (ret) {
2078 jme_drop_tx_map(jme, idx, i);
2079 goto out;
2080 }
2081
2082 }
2083
2084 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2085 ctxdesc = txdesc + ((idx + 1) & (mask));
2086 ctxbi = txbi + ((idx + 1) & (mask));
2087 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2088 offset_in_page(skb->data), len, hidma);
2089 if (ret)
2090 jme_drop_tx_map(jme, idx, i);
2091
2092 out:
2093 return ret;
2094
2095 }
2096
2097
2098 static int
2099 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2100 {
2101 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2102 if (*mss) {
2103 *flags |= TXFLAG_LSEN;
2104
2105 if (skb->protocol == htons(ETH_P_IP)) {
2106 struct iphdr *iph = ip_hdr(skb);
2107
2108 iph->check = 0;
2109 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2110 iph->daddr, 0,
2111 IPPROTO_TCP,
2112 0);
2113 } else {
2114 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2115
2116 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2117 &ip6h->daddr, 0,
2118 IPPROTO_TCP,
2119 0);
2120 }
2121
2122 return 0;
2123 }
2124
2125 return 1;
2126 }
2127
2128 static void
2129 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2130 {
2131 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2132 u8 ip_proto;
2133
2134 switch (skb->protocol) {
2135 case htons(ETH_P_IP):
2136 ip_proto = ip_hdr(skb)->protocol;
2137 break;
2138 case htons(ETH_P_IPV6):
2139 ip_proto = ipv6_hdr(skb)->nexthdr;
2140 break;
2141 default:
2142 ip_proto = 0;
2143 break;
2144 }
2145
2146 switch (ip_proto) {
2147 case IPPROTO_TCP:
2148 *flags |= TXFLAG_TCPCS;
2149 break;
2150 case IPPROTO_UDP:
2151 *flags |= TXFLAG_UDPCS;
2152 break;
2153 default:
2154 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2155 break;
2156 }
2157 }
2158 }
2159
2160 static inline void
2161 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2162 {
2163 if (vlan_tx_tag_present(skb)) {
2164 *flags |= TXFLAG_TAGON;
2165 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2166 }
2167 }
2168
2169 static int
2170 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2171 {
2172 struct jme_ring *txring = &(jme->txring[0]);
2173 struct txdesc *txdesc;
2174 struct jme_buffer_info *txbi;
2175 u8 flags;
2176 int ret = 0;
2177
2178 txdesc = (struct txdesc *)txring->desc + idx;
2179 txbi = txring->bufinf + idx;
2180
2181 txdesc->dw[0] = 0;
2182 txdesc->dw[1] = 0;
2183 txdesc->dw[2] = 0;
2184 txdesc->dw[3] = 0;
2185 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2186 /*
2187 * Set OWN bit at final.
2188 * When kernel transmit faster than NIC.
2189 * And NIC trying to send this descriptor before we tell
2190 * it to start sending this TX queue.
2191 * Other fields are already filled correctly.
2192 */
2193 wmb();
2194 flags = TXFLAG_OWN | TXFLAG_INT;
2195 /*
2196 * Set checksum flags while not tso
2197 */
2198 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2199 jme_tx_csum(jme, skb, &flags);
2200 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2201 ret = jme_map_tx_skb(jme, skb, idx);
2202 if (ret)
2203 return ret;
2204
2205 txdesc->desc1.flags = flags;
2206 /*
2207 * Set tx buffer info after telling NIC to send
2208 * For better tx_clean timing
2209 */
2210 wmb();
2211 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2212 txbi->skb = skb;
2213 txbi->len = skb->len;
2214 txbi->start_xmit = jiffies;
2215 if (!txbi->start_xmit)
2216 txbi->start_xmit = (0UL-1);
2217
2218 return 0;
2219 }
2220
2221 static void
2222 jme_stop_queue_if_full(struct jme_adapter *jme)
2223 {
2224 struct jme_ring *txring = &(jme->txring[0]);
2225 struct jme_buffer_info *txbi = txring->bufinf;
2226 int idx = atomic_read(&txring->next_to_clean);
2227
2228 txbi += idx;
2229
2230 smp_wmb();
2231 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2232 netif_stop_queue(jme->dev);
2233 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2234 smp_wmb();
2235 if (atomic_read(&txring->nr_free)
2236 >= (jme->tx_wake_threshold)) {
2237 netif_wake_queue(jme->dev);
2238 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2239 }
2240 }
2241
2242 if (unlikely(txbi->start_xmit &&
2243 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2244 txbi->skb)) {
2245 netif_stop_queue(jme->dev);
2246 netif_info(jme, tx_queued, jme->dev,
2247 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2248 }
2249 }
2250
2251 /*
2252 * This function is already protected by netif_tx_lock()
2253 */
2254
2255 static netdev_tx_t
2256 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2257 {
2258 struct jme_adapter *jme = netdev_priv(netdev);
2259 int idx;
2260
2261 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2262 dev_kfree_skb_any(skb);
2263 ++(NET_STAT(jme).tx_dropped);
2264 return NETDEV_TX_OK;
2265 }
2266
2267 idx = jme_alloc_txdesc(jme, skb);
2268
2269 if (unlikely(idx < 0)) {
2270 netif_stop_queue(netdev);
2271 netif_err(jme, tx_err, jme->dev,
2272 "BUG! Tx ring full when queue awake!\n");
2273
2274 return NETDEV_TX_BUSY;
2275 }
2276
2277 if (jme_fill_tx_desc(jme, skb, idx))
2278 return NETDEV_TX_OK;
2279
2280 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2281 TXCS_SELECT_QUEUE0 |
2282 TXCS_QUEUE0S |
2283 TXCS_ENABLE);
2284
2285 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2286 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2287 jme_stop_queue_if_full(jme);
2288
2289 return NETDEV_TX_OK;
2290 }
2291
2292 static void
2293 jme_set_unicastaddr(struct net_device *netdev)
2294 {
2295 struct jme_adapter *jme = netdev_priv(netdev);
2296 u32 val;
2297
2298 val = (netdev->dev_addr[3] & 0xff) << 24 |
2299 (netdev->dev_addr[2] & 0xff) << 16 |
2300 (netdev->dev_addr[1] & 0xff) << 8 |
2301 (netdev->dev_addr[0] & 0xff);
2302 jwrite32(jme, JME_RXUMA_LO, val);
2303 val = (netdev->dev_addr[5] & 0xff) << 8 |
2304 (netdev->dev_addr[4] & 0xff);
2305 jwrite32(jme, JME_RXUMA_HI, val);
2306 }
2307
2308 static int
2309 jme_set_macaddr(struct net_device *netdev, void *p)
2310 {
2311 struct jme_adapter *jme = netdev_priv(netdev);
2312 struct sockaddr *addr = p;
2313
2314 if (netif_running(netdev))
2315 return -EBUSY;
2316
2317 spin_lock_bh(&jme->macaddr_lock);
2318 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2319 jme_set_unicastaddr(netdev);
2320 spin_unlock_bh(&jme->macaddr_lock);
2321
2322 return 0;
2323 }
2324
2325 static void
2326 jme_set_multi(struct net_device *netdev)
2327 {
2328 struct jme_adapter *jme = netdev_priv(netdev);
2329 u32 mc_hash[2] = {};
2330
2331 spin_lock_bh(&jme->rxmcs_lock);
2332
2333 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2334
2335 if (netdev->flags & IFF_PROMISC) {
2336 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2337 } else if (netdev->flags & IFF_ALLMULTI) {
2338 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2339 } else if (netdev->flags & IFF_MULTICAST) {
2340 struct netdev_hw_addr *ha;
2341 int bit_nr;
2342
2343 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2344 netdev_for_each_mc_addr(ha, netdev) {
2345 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2346 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2347 }
2348
2349 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2350 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2351 }
2352
2353 wmb();
2354 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2355
2356 spin_unlock_bh(&jme->rxmcs_lock);
2357 }
2358
2359 static int
2360 jme_change_mtu(struct net_device *netdev, int new_mtu)
2361 {
2362 struct jme_adapter *jme = netdev_priv(netdev);
2363
2364 if (new_mtu == jme->old_mtu)
2365 return 0;
2366
2367 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2368 ((new_mtu) < IPV6_MIN_MTU))
2369 return -EINVAL;
2370
2371
2372 netdev->mtu = new_mtu;
2373 netdev_update_features(netdev);
2374
2375 jme_restart_rx_engine(jme);
2376 jme_reset_link(jme);
2377
2378 return 0;
2379 }
2380
2381 static void
2382 jme_tx_timeout(struct net_device *netdev)
2383 {
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385
2386 jme->phylink = 0;
2387 jme_reset_phy_processor(jme);
2388 if (test_bit(JME_FLAG_SSET, &jme->flags))
2389 jme_set_settings(netdev, &jme->old_ecmd);
2390
2391 /*
2392 * Force to Reset the link again
2393 */
2394 jme_reset_link(jme);
2395 }
2396
2397 static inline void jme_pause_rx(struct jme_adapter *jme)
2398 {
2399 atomic_dec(&jme->link_changing);
2400
2401 jme_set_rx_pcc(jme, PCC_OFF);
2402 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2403 JME_NAPI_DISABLE(jme);
2404 } else {
2405 tasklet_disable(&jme->rxclean_task);
2406 tasklet_disable(&jme->rxempty_task);
2407 }
2408 }
2409
2410 static inline void jme_resume_rx(struct jme_adapter *jme)
2411 {
2412 struct dynpcc_info *dpi = &(jme->dpi);
2413
2414 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2415 JME_NAPI_ENABLE(jme);
2416 } else {
2417 tasklet_hi_enable(&jme->rxclean_task);
2418 tasklet_hi_enable(&jme->rxempty_task);
2419 }
2420 dpi->cur = PCC_P1;
2421 dpi->attempt = PCC_P1;
2422 dpi->cnt = 0;
2423 jme_set_rx_pcc(jme, PCC_P1);
2424
2425 atomic_inc(&jme->link_changing);
2426 }
2427
2428 static void
2429 jme_get_drvinfo(struct net_device *netdev,
2430 struct ethtool_drvinfo *info)
2431 {
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433
2434 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2435 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2436 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2437 }
2438
2439 static int
2440 jme_get_regs_len(struct net_device *netdev)
2441 {
2442 return JME_REG_LEN;
2443 }
2444
2445 static void
2446 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2447 {
2448 int i;
2449
2450 for (i = 0 ; i < len ; i += 4)
2451 p[i >> 2] = jread32(jme, reg + i);
2452 }
2453
2454 static void
2455 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2456 {
2457 int i;
2458 u16 *p16 = (u16 *)p;
2459
2460 for (i = 0 ; i < reg_nr ; ++i)
2461 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2462 }
2463
2464 static void
2465 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2466 {
2467 struct jme_adapter *jme = netdev_priv(netdev);
2468 u32 *p32 = (u32 *)p;
2469
2470 memset(p, 0xFF, JME_REG_LEN);
2471
2472 regs->version = 1;
2473 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2474
2475 p32 += 0x100 >> 2;
2476 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2477
2478 p32 += 0x100 >> 2;
2479 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2480
2481 p32 += 0x100 >> 2;
2482 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2483
2484 p32 += 0x100 >> 2;
2485 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2486 }
2487
2488 static int
2489 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2490 {
2491 struct jme_adapter *jme = netdev_priv(netdev);
2492
2493 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2494 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2495
2496 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2497 ecmd->use_adaptive_rx_coalesce = false;
2498 ecmd->rx_coalesce_usecs = 0;
2499 ecmd->rx_max_coalesced_frames = 0;
2500 return 0;
2501 }
2502
2503 ecmd->use_adaptive_rx_coalesce = true;
2504
2505 switch (jme->dpi.cur) {
2506 case PCC_P1:
2507 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2508 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2509 break;
2510 case PCC_P2:
2511 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2512 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2513 break;
2514 case PCC_P3:
2515 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2516 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2517 break;
2518 default:
2519 break;
2520 }
2521
2522 return 0;
2523 }
2524
2525 static int
2526 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2527 {
2528 struct jme_adapter *jme = netdev_priv(netdev);
2529 struct dynpcc_info *dpi = &(jme->dpi);
2530
2531 if (netif_running(netdev))
2532 return -EBUSY;
2533
2534 if (ecmd->use_adaptive_rx_coalesce &&
2535 test_bit(JME_FLAG_POLL, &jme->flags)) {
2536 clear_bit(JME_FLAG_POLL, &jme->flags);
2537 jme->jme_rx = netif_rx;
2538 dpi->cur = PCC_P1;
2539 dpi->attempt = PCC_P1;
2540 dpi->cnt = 0;
2541 jme_set_rx_pcc(jme, PCC_P1);
2542 jme_interrupt_mode(jme);
2543 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2544 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2545 set_bit(JME_FLAG_POLL, &jme->flags);
2546 jme->jme_rx = netif_receive_skb;
2547 jme_interrupt_mode(jme);
2548 }
2549
2550 return 0;
2551 }
2552
2553 static void
2554 jme_get_pauseparam(struct net_device *netdev,
2555 struct ethtool_pauseparam *ecmd)
2556 {
2557 struct jme_adapter *jme = netdev_priv(netdev);
2558 u32 val;
2559
2560 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2561 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2562
2563 spin_lock_bh(&jme->phy_lock);
2564 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2565 spin_unlock_bh(&jme->phy_lock);
2566
2567 ecmd->autoneg =
2568 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2569 }
2570
2571 static int
2572 jme_set_pauseparam(struct net_device *netdev,
2573 struct ethtool_pauseparam *ecmd)
2574 {
2575 struct jme_adapter *jme = netdev_priv(netdev);
2576 u32 val;
2577
2578 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2579 (ecmd->tx_pause != 0)) {
2580
2581 if (ecmd->tx_pause)
2582 jme->reg_txpfc |= TXPFC_PF_EN;
2583 else
2584 jme->reg_txpfc &= ~TXPFC_PF_EN;
2585
2586 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2587 }
2588
2589 spin_lock_bh(&jme->rxmcs_lock);
2590 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2591 (ecmd->rx_pause != 0)) {
2592
2593 if (ecmd->rx_pause)
2594 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2595 else
2596 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2597
2598 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2599 }
2600 spin_unlock_bh(&jme->rxmcs_lock);
2601
2602 spin_lock_bh(&jme->phy_lock);
2603 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2604 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2605 (ecmd->autoneg != 0)) {
2606
2607 if (ecmd->autoneg)
2608 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2609 else
2610 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2611
2612 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2613 MII_ADVERTISE, val);
2614 }
2615 spin_unlock_bh(&jme->phy_lock);
2616
2617 return 0;
2618 }
2619
2620 static void
2621 jme_get_wol(struct net_device *netdev,
2622 struct ethtool_wolinfo *wol)
2623 {
2624 struct jme_adapter *jme = netdev_priv(netdev);
2625
2626 wol->supported = WAKE_MAGIC | WAKE_PHY;
2627
2628 wol->wolopts = 0;
2629
2630 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2631 wol->wolopts |= WAKE_PHY;
2632
2633 if (jme->reg_pmcs & PMCS_MFEN)
2634 wol->wolopts |= WAKE_MAGIC;
2635
2636 }
2637
2638 static int
2639 jme_set_wol(struct net_device *netdev,
2640 struct ethtool_wolinfo *wol)
2641 {
2642 struct jme_adapter *jme = netdev_priv(netdev);
2643
2644 if (wol->wolopts & (WAKE_MAGICSECURE |
2645 WAKE_UCAST |
2646 WAKE_MCAST |
2647 WAKE_BCAST |
2648 WAKE_ARP))
2649 return -EOPNOTSUPP;
2650
2651 jme->reg_pmcs = 0;
2652
2653 if (wol->wolopts & WAKE_PHY)
2654 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2655
2656 if (wol->wolopts & WAKE_MAGIC)
2657 jme->reg_pmcs |= PMCS_MFEN;
2658
2659 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2660
2661 return 0;
2662 }
2663
2664 static int
2665 jme_get_settings(struct net_device *netdev,
2666 struct ethtool_cmd *ecmd)
2667 {
2668 struct jme_adapter *jme = netdev_priv(netdev);
2669 int rc;
2670
2671 spin_lock_bh(&jme->phy_lock);
2672 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2673 spin_unlock_bh(&jme->phy_lock);
2674 return rc;
2675 }
2676
2677 static int
2678 jme_set_settings(struct net_device *netdev,
2679 struct ethtool_cmd *ecmd)
2680 {
2681 struct jme_adapter *jme = netdev_priv(netdev);
2682 int rc, fdc = 0;
2683
2684 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2685 && ecmd->autoneg != AUTONEG_ENABLE)
2686 return -EINVAL;
2687
2688 /*
2689 * Check If user changed duplex only while force_media.
2690 * Hardware would not generate link change interrupt.
2691 */
2692 if (jme->mii_if.force_media &&
2693 ecmd->autoneg != AUTONEG_ENABLE &&
2694 (jme->mii_if.full_duplex != ecmd->duplex))
2695 fdc = 1;
2696
2697 spin_lock_bh(&jme->phy_lock);
2698 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2699 spin_unlock_bh(&jme->phy_lock);
2700
2701 if (!rc) {
2702 if (fdc)
2703 jme_reset_link(jme);
2704 jme->old_ecmd = *ecmd;
2705 set_bit(JME_FLAG_SSET, &jme->flags);
2706 }
2707
2708 return rc;
2709 }
2710
2711 static int
2712 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2713 {
2714 int rc;
2715 struct jme_adapter *jme = netdev_priv(netdev);
2716 struct mii_ioctl_data *mii_data = if_mii(rq);
2717 unsigned int duplex_chg;
2718
2719 if (cmd == SIOCSMIIREG) {
2720 u16 val = mii_data->val_in;
2721 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2722 (val & BMCR_SPEED1000))
2723 return -EINVAL;
2724 }
2725
2726 spin_lock_bh(&jme->phy_lock);
2727 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2728 spin_unlock_bh(&jme->phy_lock);
2729
2730 if (!rc && (cmd == SIOCSMIIREG)) {
2731 if (duplex_chg)
2732 jme_reset_link(jme);
2733 jme_get_settings(netdev, &jme->old_ecmd);
2734 set_bit(JME_FLAG_SSET, &jme->flags);
2735 }
2736
2737 return rc;
2738 }
2739
2740 static u32
2741 jme_get_link(struct net_device *netdev)
2742 {
2743 struct jme_adapter *jme = netdev_priv(netdev);
2744 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2745 }
2746
2747 static u32
2748 jme_get_msglevel(struct net_device *netdev)
2749 {
2750 struct jme_adapter *jme = netdev_priv(netdev);
2751 return jme->msg_enable;
2752 }
2753
2754 static void
2755 jme_set_msglevel(struct net_device *netdev, u32 value)
2756 {
2757 struct jme_adapter *jme = netdev_priv(netdev);
2758 jme->msg_enable = value;
2759 }
2760
2761 static netdev_features_t
2762 jme_fix_features(struct net_device *netdev, netdev_features_t features)
2763 {
2764 if (netdev->mtu > 1900)
2765 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2766 return features;
2767 }
2768
2769 static int
2770 jme_set_features(struct net_device *netdev, netdev_features_t features)
2771 {
2772 struct jme_adapter *jme = netdev_priv(netdev);
2773
2774 spin_lock_bh(&jme->rxmcs_lock);
2775 if (features & NETIF_F_RXCSUM)
2776 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2777 else
2778 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2779 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2780 spin_unlock_bh(&jme->rxmcs_lock);
2781
2782 return 0;
2783 }
2784
2785 #ifdef CONFIG_NET_POLL_CONTROLLER
2786 static void jme_netpoll(struct net_device *dev)
2787 {
2788 unsigned long flags;
2789
2790 local_irq_save(flags);
2791 jme_intr(dev->irq, dev);
2792 local_irq_restore(flags);
2793 }
2794 #endif
2795
2796 static int
2797 jme_nway_reset(struct net_device *netdev)
2798 {
2799 struct jme_adapter *jme = netdev_priv(netdev);
2800 jme_restart_an(jme);
2801 return 0;
2802 }
2803
2804 static u8
2805 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2806 {
2807 u32 val;
2808 int to;
2809
2810 val = jread32(jme, JME_SMBCSR);
2811 to = JME_SMB_BUSY_TIMEOUT;
2812 while ((val & SMBCSR_BUSY) && --to) {
2813 msleep(1);
2814 val = jread32(jme, JME_SMBCSR);
2815 }
2816 if (!to) {
2817 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2818 return 0xFF;
2819 }
2820
2821 jwrite32(jme, JME_SMBINTF,
2822 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2823 SMBINTF_HWRWN_READ |
2824 SMBINTF_HWCMD);
2825
2826 val = jread32(jme, JME_SMBINTF);
2827 to = JME_SMB_BUSY_TIMEOUT;
2828 while ((val & SMBINTF_HWCMD) && --to) {
2829 msleep(1);
2830 val = jread32(jme, JME_SMBINTF);
2831 }
2832 if (!to) {
2833 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2834 return 0xFF;
2835 }
2836
2837 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2838 }
2839
2840 static void
2841 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2842 {
2843 u32 val;
2844 int to;
2845
2846 val = jread32(jme, JME_SMBCSR);
2847 to = JME_SMB_BUSY_TIMEOUT;
2848 while ((val & SMBCSR_BUSY) && --to) {
2849 msleep(1);
2850 val = jread32(jme, JME_SMBCSR);
2851 }
2852 if (!to) {
2853 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2854 return;
2855 }
2856
2857 jwrite32(jme, JME_SMBINTF,
2858 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2859 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2860 SMBINTF_HWRWN_WRITE |
2861 SMBINTF_HWCMD);
2862
2863 val = jread32(jme, JME_SMBINTF);
2864 to = JME_SMB_BUSY_TIMEOUT;
2865 while ((val & SMBINTF_HWCMD) && --to) {
2866 msleep(1);
2867 val = jread32(jme, JME_SMBINTF);
2868 }
2869 if (!to) {
2870 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2871 return;
2872 }
2873
2874 mdelay(2);
2875 }
2876
2877 static int
2878 jme_get_eeprom_len(struct net_device *netdev)
2879 {
2880 struct jme_adapter *jme = netdev_priv(netdev);
2881 u32 val;
2882 val = jread32(jme, JME_SMBCSR);
2883 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2884 }
2885
2886 static int
2887 jme_get_eeprom(struct net_device *netdev,
2888 struct ethtool_eeprom *eeprom, u8 *data)
2889 {
2890 struct jme_adapter *jme = netdev_priv(netdev);
2891 int i, offset = eeprom->offset, len = eeprom->len;
2892
2893 /*
2894 * ethtool will check the boundary for us
2895 */
2896 eeprom->magic = JME_EEPROM_MAGIC;
2897 for (i = 0 ; i < len ; ++i)
2898 data[i] = jme_smb_read(jme, i + offset);
2899
2900 return 0;
2901 }
2902
2903 static int
2904 jme_set_eeprom(struct net_device *netdev,
2905 struct ethtool_eeprom *eeprom, u8 *data)
2906 {
2907 struct jme_adapter *jme = netdev_priv(netdev);
2908 int i, offset = eeprom->offset, len = eeprom->len;
2909
2910 if (eeprom->magic != JME_EEPROM_MAGIC)
2911 return -EINVAL;
2912
2913 /*
2914 * ethtool will check the boundary for us
2915 */
2916 for (i = 0 ; i < len ; ++i)
2917 jme_smb_write(jme, i + offset, data[i]);
2918
2919 return 0;
2920 }
2921
2922 static const struct ethtool_ops jme_ethtool_ops = {
2923 .get_drvinfo = jme_get_drvinfo,
2924 .get_regs_len = jme_get_regs_len,
2925 .get_regs = jme_get_regs,
2926 .get_coalesce = jme_get_coalesce,
2927 .set_coalesce = jme_set_coalesce,
2928 .get_pauseparam = jme_get_pauseparam,
2929 .set_pauseparam = jme_set_pauseparam,
2930 .get_wol = jme_get_wol,
2931 .set_wol = jme_set_wol,
2932 .get_settings = jme_get_settings,
2933 .set_settings = jme_set_settings,
2934 .get_link = jme_get_link,
2935 .get_msglevel = jme_get_msglevel,
2936 .set_msglevel = jme_set_msglevel,
2937 .nway_reset = jme_nway_reset,
2938 .get_eeprom_len = jme_get_eeprom_len,
2939 .get_eeprom = jme_get_eeprom,
2940 .set_eeprom = jme_set_eeprom,
2941 };
2942
2943 static int
2944 jme_pci_dma64(struct pci_dev *pdev)
2945 {
2946 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2947 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2948 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2949 return 1;
2950
2951 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2952 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2953 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2954 return 1;
2955
2956 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2957 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2958 return 0;
2959
2960 return -1;
2961 }
2962
2963 static inline void
2964 jme_phy_init(struct jme_adapter *jme)
2965 {
2966 u16 reg26;
2967
2968 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2969 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2970 }
2971
2972 static inline void
2973 jme_check_hw_ver(struct jme_adapter *jme)
2974 {
2975 u32 chipmode;
2976
2977 chipmode = jread32(jme, JME_CHIPMODE);
2978
2979 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2980 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2981 jme->chip_main_rev = jme->chiprev & 0xF;
2982 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2983 }
2984
2985 static const struct net_device_ops jme_netdev_ops = {
2986 .ndo_open = jme_open,
2987 .ndo_stop = jme_close,
2988 .ndo_validate_addr = eth_validate_addr,
2989 .ndo_do_ioctl = jme_ioctl,
2990 .ndo_start_xmit = jme_start_xmit,
2991 .ndo_set_mac_address = jme_set_macaddr,
2992 .ndo_set_rx_mode = jme_set_multi,
2993 .ndo_change_mtu = jme_change_mtu,
2994 .ndo_tx_timeout = jme_tx_timeout,
2995 .ndo_fix_features = jme_fix_features,
2996 .ndo_set_features = jme_set_features,
2997 #ifdef CONFIG_NET_POLL_CONTROLLER
2998 .ndo_poll_controller = jme_netpoll,
2999 #endif
3000 };
3001
3002 static int
3003 jme_init_one(struct pci_dev *pdev,
3004 const struct pci_device_id *ent)
3005 {
3006 int rc = 0, using_dac, i;
3007 struct net_device *netdev;
3008 struct jme_adapter *jme;
3009 u16 bmcr, bmsr;
3010 u32 apmc;
3011
3012 /*
3013 * set up PCI device basics
3014 */
3015 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3016 PCIE_LINK_STATE_CLKPM);
3017
3018 rc = pci_enable_device(pdev);
3019 if (rc) {
3020 pr_err("Cannot enable PCI device\n");
3021 goto err_out;
3022 }
3023
3024 using_dac = jme_pci_dma64(pdev);
3025 if (using_dac < 0) {
3026 pr_err("Cannot set PCI DMA Mask\n");
3027 rc = -EIO;
3028 goto err_out_disable_pdev;
3029 }
3030
3031 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3032 pr_err("No PCI resource region found\n");
3033 rc = -ENOMEM;
3034 goto err_out_disable_pdev;
3035 }
3036
3037 rc = pci_request_regions(pdev, DRV_NAME);
3038 if (rc) {
3039 pr_err("Cannot obtain PCI resource region\n");
3040 goto err_out_disable_pdev;
3041 }
3042
3043 pci_set_master(pdev);
3044
3045 /*
3046 * alloc and init net device
3047 */
3048 netdev = alloc_etherdev(sizeof(*jme));
3049 if (!netdev) {
3050 rc = -ENOMEM;
3051 goto err_out_release_regions;
3052 }
3053 netdev->netdev_ops = &jme_netdev_ops;
3054 netdev->ethtool_ops = &jme_ethtool_ops;
3055 netdev->watchdog_timeo = TX_TIMEOUT;
3056 netdev->hw_features = NETIF_F_IP_CSUM |
3057 NETIF_F_IPV6_CSUM |
3058 NETIF_F_SG |
3059 NETIF_F_TSO |
3060 NETIF_F_TSO6 |
3061 NETIF_F_RXCSUM;
3062 netdev->features = NETIF_F_IP_CSUM |
3063 NETIF_F_IPV6_CSUM |
3064 NETIF_F_SG |
3065 NETIF_F_TSO |
3066 NETIF_F_TSO6 |
3067 NETIF_F_HW_VLAN_CTAG_TX |
3068 NETIF_F_HW_VLAN_CTAG_RX;
3069 if (using_dac)
3070 netdev->features |= NETIF_F_HIGHDMA;
3071
3072 SET_NETDEV_DEV(netdev, &pdev->dev);
3073 pci_set_drvdata(pdev, netdev);
3074
3075 /*
3076 * init adapter info
3077 */
3078 jme = netdev_priv(netdev);
3079 jme->pdev = pdev;
3080 jme->dev = netdev;
3081 jme->jme_rx = netif_rx;
3082 jme->old_mtu = netdev->mtu = 1500;
3083 jme->phylink = 0;
3084 jme->tx_ring_size = 1 << 10;
3085 jme->tx_ring_mask = jme->tx_ring_size - 1;
3086 jme->tx_wake_threshold = 1 << 9;
3087 jme->rx_ring_size = 1 << 9;
3088 jme->rx_ring_mask = jme->rx_ring_size - 1;
3089 jme->msg_enable = JME_DEF_MSG_ENABLE;
3090 jme->regs = ioremap(pci_resource_start(pdev, 0),
3091 pci_resource_len(pdev, 0));
3092 if (!(jme->regs)) {
3093 pr_err("Mapping PCI resource region error\n");
3094 rc = -ENOMEM;
3095 goto err_out_free_netdev;
3096 }
3097
3098 if (no_pseudohp) {
3099 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3100 jwrite32(jme, JME_APMC, apmc);
3101 } else if (force_pseudohp) {
3102 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3103 jwrite32(jme, JME_APMC, apmc);
3104 }
3105
3106 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3107
3108 spin_lock_init(&jme->phy_lock);
3109 spin_lock_init(&jme->macaddr_lock);
3110 spin_lock_init(&jme->rxmcs_lock);
3111
3112 atomic_set(&jme->link_changing, 1);
3113 atomic_set(&jme->rx_cleaning, 1);
3114 atomic_set(&jme->tx_cleaning, 1);
3115 atomic_set(&jme->rx_empty, 1);
3116
3117 tasklet_init(&jme->pcc_task,
3118 jme_pcc_tasklet,
3119 (unsigned long) jme);
3120 jme->dpi.cur = PCC_P1;
3121
3122 jme->reg_ghc = 0;
3123 jme->reg_rxcs = RXCS_DEFAULT;
3124 jme->reg_rxmcs = RXMCS_DEFAULT;
3125 jme->reg_txpfc = 0;
3126 jme->reg_pmcs = PMCS_MFEN;
3127 jme->reg_gpreg1 = GPREG1_DEFAULT;
3128
3129 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3130 netdev->features |= NETIF_F_RXCSUM;
3131
3132 /*
3133 * Get Max Read Req Size from PCI Config Space
3134 */
3135 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3136 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3137 switch (jme->mrrs) {
3138 case MRRS_128B:
3139 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3140 break;
3141 case MRRS_256B:
3142 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3143 break;
3144 default:
3145 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3146 break;
3147 }
3148
3149 /*
3150 * Must check before reset_mac_processor
3151 */
3152 jme_check_hw_ver(jme);
3153 jme->mii_if.dev = netdev;
3154 if (jme->fpgaver) {
3155 jme->mii_if.phy_id = 0;
3156 for (i = 1 ; i < 32 ; ++i) {
3157 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3158 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3159 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3160 jme->mii_if.phy_id = i;
3161 break;
3162 }
3163 }
3164
3165 if (!jme->mii_if.phy_id) {
3166 rc = -EIO;
3167 pr_err("Can not find phy_id\n");
3168 goto err_out_unmap;
3169 }
3170
3171 jme->reg_ghc |= GHC_LINK_POLL;
3172 } else {
3173 jme->mii_if.phy_id = 1;
3174 }
3175 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3176 jme->mii_if.supports_gmii = true;
3177 else
3178 jme->mii_if.supports_gmii = false;
3179 jme->mii_if.phy_id_mask = 0x1F;
3180 jme->mii_if.reg_num_mask = 0x1F;
3181 jme->mii_if.mdio_read = jme_mdio_read;
3182 jme->mii_if.mdio_write = jme_mdio_write;
3183
3184 jme_clear_pm_disable_wol(jme);
3185 device_set_wakeup_enable(&pdev->dev, true);
3186
3187 jme_set_phyfifo_5level(jme);
3188 jme->pcirev = pdev->revision;
3189 if (!jme->fpgaver)
3190 jme_phy_init(jme);
3191 jme_phy_off(jme);
3192
3193 /*
3194 * Reset MAC processor and reload EEPROM for MAC Address
3195 */
3196 jme_reset_mac_processor(jme);
3197 rc = jme_reload_eeprom(jme);
3198 if (rc) {
3199 pr_err("Reload eeprom for reading MAC Address error\n");
3200 goto err_out_unmap;
3201 }
3202 jme_load_macaddr(netdev);
3203
3204 /*
3205 * Tell stack that we are not ready to work until open()
3206 */
3207 netif_carrier_off(netdev);
3208
3209 rc = register_netdev(netdev);
3210 if (rc) {
3211 pr_err("Cannot register net device\n");
3212 goto err_out_unmap;
3213 }
3214
3215 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3216 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3217 "JMC250 Gigabit Ethernet" :
3218 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3219 "JMC260 Fast Ethernet" : "Unknown",
3220 (jme->fpgaver != 0) ? " (FPGA)" : "",
3221 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3222 jme->pcirev, netdev->dev_addr);
3223
3224 return 0;
3225
3226 err_out_unmap:
3227 iounmap(jme->regs);
3228 err_out_free_netdev:
3229 free_netdev(netdev);
3230 err_out_release_regions:
3231 pci_release_regions(pdev);
3232 err_out_disable_pdev:
3233 pci_disable_device(pdev);
3234 err_out:
3235 return rc;
3236 }
3237
3238 static void
3239 jme_remove_one(struct pci_dev *pdev)
3240 {
3241 struct net_device *netdev = pci_get_drvdata(pdev);
3242 struct jme_adapter *jme = netdev_priv(netdev);
3243
3244 unregister_netdev(netdev);
3245 iounmap(jme->regs);
3246 free_netdev(netdev);
3247 pci_release_regions(pdev);
3248 pci_disable_device(pdev);
3249
3250 }
3251
3252 static void
3253 jme_shutdown(struct pci_dev *pdev)
3254 {
3255 struct net_device *netdev = pci_get_drvdata(pdev);
3256 struct jme_adapter *jme = netdev_priv(netdev);
3257
3258 jme_powersave_phy(jme);
3259 pci_pme_active(pdev, true);
3260 }
3261
3262 #ifdef CONFIG_PM_SLEEP
3263 static int
3264 jme_suspend(struct device *dev)
3265 {
3266 struct pci_dev *pdev = to_pci_dev(dev);
3267 struct net_device *netdev = pci_get_drvdata(pdev);
3268 struct jme_adapter *jme = netdev_priv(netdev);
3269
3270 if (!netif_running(netdev))
3271 return 0;
3272
3273 atomic_dec(&jme->link_changing);
3274
3275 netif_device_detach(netdev);
3276 netif_stop_queue(netdev);
3277 jme_stop_irq(jme);
3278
3279 tasklet_disable(&jme->txclean_task);
3280 tasklet_disable(&jme->rxclean_task);
3281 tasklet_disable(&jme->rxempty_task);
3282
3283 if (netif_carrier_ok(netdev)) {
3284 if (test_bit(JME_FLAG_POLL, &jme->flags))
3285 jme_polling_mode(jme);
3286
3287 jme_stop_pcc_timer(jme);
3288 jme_disable_rx_engine(jme);
3289 jme_disable_tx_engine(jme);
3290 jme_reset_mac_processor(jme);
3291 jme_free_rx_resources(jme);
3292 jme_free_tx_resources(jme);
3293 netif_carrier_off(netdev);
3294 jme->phylink = 0;
3295 }
3296
3297 tasklet_enable(&jme->txclean_task);
3298 tasklet_hi_enable(&jme->rxclean_task);
3299 tasklet_hi_enable(&jme->rxempty_task);
3300
3301 jme_powersave_phy(jme);
3302
3303 return 0;
3304 }
3305
3306 static int
3307 jme_resume(struct device *dev)
3308 {
3309 struct pci_dev *pdev = to_pci_dev(dev);
3310 struct net_device *netdev = pci_get_drvdata(pdev);
3311 struct jme_adapter *jme = netdev_priv(netdev);
3312
3313 if (!netif_running(netdev))
3314 return 0;
3315
3316 jme_clear_pm_disable_wol(jme);
3317 jme_phy_on(jme);
3318 if (test_bit(JME_FLAG_SSET, &jme->flags))
3319 jme_set_settings(netdev, &jme->old_ecmd);
3320 else
3321 jme_reset_phy_processor(jme);
3322 jme_phy_calibration(jme);
3323 jme_phy_setEA(jme);
3324 netif_device_attach(netdev);
3325
3326 atomic_inc(&jme->link_changing);
3327
3328 jme_reset_link(jme);
3329
3330 jme_start_irq(jme);
3331
3332 return 0;
3333 }
3334
3335 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3336 #define JME_PM_OPS (&jme_pm_ops)
3337
3338 #else
3339
3340 #define JME_PM_OPS NULL
3341 #endif
3342
3343 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3344 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3345 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3346 { }
3347 };
3348
3349 static struct pci_driver jme_driver = {
3350 .name = DRV_NAME,
3351 .id_table = jme_pci_tbl,
3352 .probe = jme_init_one,
3353 .remove = jme_remove_one,
3354 .shutdown = jme_shutdown,
3355 .driver.pm = JME_PM_OPS,
3356 };
3357
3358 static int __init
3359 jme_init_module(void)
3360 {
3361 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3362 return pci_register_driver(&jme_driver);
3363 }
3364
3365 static void __exit
3366 jme_cleanup_module(void)
3367 {
3368 pci_unregister_driver(&jme_driver);
3369 }
3370
3371 module_init(jme_init_module);
3372 module_exit(jme_cleanup_module);
3373
3374 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3375 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3376 MODULE_LICENSE("GPL");
3377 MODULE_VERSION(DRV_VERSION);
3378 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
Linux with added FPC-III support