MIPS: eBPF: Fix icache flush end address
[linux/fpc-iii.git] / arch / mips / alchemy / board-gpr.c
blobddff9a02513d57e8b86e1c862cac6810ee7976b7
1 /*
2 * GPR board platform device registration (Au1550)
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/physmap.h>
29 #include <linux/leds.h>
30 #include <linux/gpio.h>
31 #include <linux/i2c.h>
32 #include <linux/platform_data/i2c-gpio.h>
33 #include <linux/gpio/machine.h>
34 #include <asm/bootinfo.h>
35 #include <asm/idle.h>
36 #include <asm/reboot.h>
37 #include <asm/setup.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-au1x00/gpio-au1000.h>
40 #include <prom.h>
42 const char *get_system_type(void)
44 return "GPR";
47 void __init prom_init(void)
49 unsigned char *memsize_str;
50 unsigned long memsize;
52 prom_argc = fw_arg0;
53 prom_argv = (char **)fw_arg1;
54 prom_envp = (char **)fw_arg2;
56 prom_init_cmdline();
58 memsize_str = prom_getenv("memsize");
59 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
60 memsize = 0x04000000;
61 add_memory_region(0, memsize, BOOT_MEM_RAM);
64 void prom_putchar(char c)
66 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
69 static void gpr_reset(char *c)
71 /* switch System-LED to orange (red# and green# on) */
72 alchemy_gpio_direction_output(4, 0);
73 alchemy_gpio_direction_output(5, 0);
75 /* trigger watchdog to reset board in 200ms */
76 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
77 raw_local_irq_disable();
78 alchemy_gpio_direction_output(1, 0);
79 udelay(1);
80 alchemy_gpio_set_value(1, 1);
81 while (1)
82 cpu_wait();
85 static void gpr_power_off(void)
87 while (1)
88 cpu_wait();
91 void __init board_setup(void)
93 printk(KERN_INFO "Trapeze ITS GPR board\n");
95 pm_power_off = gpr_power_off;
96 _machine_halt = gpr_power_off;
97 _machine_restart = gpr_reset;
99 /* Enable UART1/3 */
100 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
101 alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
103 /* Take away Reset of UMTS-card */
104 alchemy_gpio_direction_output(215, 1);
108 * Watchdog
110 static struct resource gpr_wdt_resource[] = {
111 [0] = {
112 .start = 1,
113 .end = 1,
114 .name = "gpr-adm6320-wdt",
115 .flags = IORESOURCE_IRQ,
119 static struct platform_device gpr_wdt_device = {
120 .name = "adm6320-wdt",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(gpr_wdt_resource),
123 .resource = gpr_wdt_resource,
127 * FLASH
129 * 0x00000000-0x00200000 : "kernel"
130 * 0x00200000-0x00a00000 : "rootfs"
131 * 0x01d00000-0x01f00000 : "config"
132 * 0x01c00000-0x01d00000 : "yamon"
133 * 0x01d00000-0x01d40000 : "yamon env vars"
134 * 0x00000000-0x00a00000 : "kernel+rootfs"
136 static struct mtd_partition gpr_mtd_partitions[] = {
138 .name = "kernel",
139 .size = 0x00200000,
140 .offset = 0,
143 .name = "rootfs",
144 .size = 0x00800000,
145 .offset = MTDPART_OFS_APPEND,
146 .mask_flags = MTD_WRITEABLE,
149 .name = "config",
150 .size = 0x00200000,
151 .offset = 0x01d00000,
154 .name = "yamon",
155 .size = 0x00100000,
156 .offset = 0x01c00000,
159 .name = "yamon env vars",
160 .size = 0x00040000,
161 .offset = MTDPART_OFS_APPEND,
164 .name = "kernel+rootfs",
165 .size = 0x00a00000,
166 .offset = 0,
170 static struct physmap_flash_data gpr_flash_data = {
171 .width = 4,
172 .nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
173 .parts = gpr_mtd_partitions,
176 static struct resource gpr_mtd_resource = {
177 .start = 0x1e000000,
178 .end = 0x1fffffff,
179 .flags = IORESOURCE_MEM,
182 static struct platform_device gpr_mtd_device = {
183 .name = "physmap-flash",
184 .dev = {
185 .platform_data = &gpr_flash_data,
187 .num_resources = 1,
188 .resource = &gpr_mtd_resource,
192 * LEDs
194 static const struct gpio_led gpr_gpio_leds[] = {
195 { /* green */
196 .name = "gpr:green",
197 .gpio = 4,
198 .active_low = 1,
200 { /* red */
201 .name = "gpr:red",
202 .gpio = 5,
203 .active_low = 1,
207 static struct gpio_led_platform_data gpr_led_data = {
208 .num_leds = ARRAY_SIZE(gpr_gpio_leds),
209 .leds = gpr_gpio_leds,
212 static struct platform_device gpr_led_devices = {
213 .name = "leds-gpio",
214 .id = -1,
215 .dev = {
216 .platform_data = &gpr_led_data,
221 * I2C
223 static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
224 .dev_id = "i2c-gpio",
225 .table = {
227 * This should be on "GPIO2" which has base at 200 so
228 * the global numbers 209 and 210 should correspond to
229 * local offsets 9 and 10.
231 GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
232 GPIO_ACTIVE_HIGH),
233 GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
234 GPIO_ACTIVE_HIGH),
238 static struct i2c_gpio_platform_data gpr_i2c_data = {
240 * The open drain mode is hardwired somewhere or an electrical
241 * property of the alchemy GPIO controller.
243 .sda_is_open_drain = 1,
244 .scl_is_open_drain = 1,
245 .udelay = 2, /* ~100 kHz */
246 .timeout = HZ,
249 static struct platform_device gpr_i2c_device = {
250 .name = "i2c-gpio",
251 .id = -1,
252 .dev.platform_data = &gpr_i2c_data,
255 static struct i2c_board_info gpr_i2c_info[] __initdata = {
257 I2C_BOARD_INFO("lm83", 0x18),
263 static struct resource alchemy_pci_host_res[] = {
264 [0] = {
265 .start = AU1500_PCI_PHYS_ADDR,
266 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
267 .flags = IORESOURCE_MEM,
271 static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
273 if ((slot == 0) && (pin == 1))
274 return AU1550_PCI_INTA;
275 else if ((slot == 0) && (pin == 2))
276 return AU1550_PCI_INTB;
278 return 0xff;
281 static struct alchemy_pci_platdata gpr_pci_pd = {
282 .board_map_irq = gpr_map_pci_irq,
283 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
284 PCI_CONFIG_CH |
285 #if defined(__MIPSEB__)
286 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
287 #else
289 #endif
292 static struct platform_device gpr_pci_host_dev = {
293 .dev.platform_data = &gpr_pci_pd,
294 .name = "alchemy-pci",
295 .id = 0,
296 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
297 .resource = alchemy_pci_host_res,
300 static struct platform_device *gpr_devices[] __initdata = {
301 &gpr_wdt_device,
302 &gpr_mtd_device,
303 &gpr_i2c_device,
304 &gpr_led_devices,
307 static int __init gpr_pci_init(void)
309 return platform_device_register(&gpr_pci_host_dev);
311 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
312 arch_initcall(gpr_pci_init);
315 static int __init gpr_dev_init(void)
317 gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
318 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
320 return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
322 device_initcall(gpr_dev_init);