MIPS: eBPF: Fix icache flush end address
[linux/fpc-iii.git] / arch / mips / math-emu / sp_flong.c
blob012e30ce7589fe2b409af91a8b63c8d2706b555e
1 /* IEEE754 floating point arithmetic
2 * single precision
3 */
4 /*
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "ieee754sp.h"
24 union ieee754sp ieee754sp_flong(s64 x)
26 u64 xm; /* <--- need 64-bit mantissa temp */
27 int xe;
28 int xs;
30 ieee754_clearcx();
32 if (x == 0)
33 return ieee754sp_zero(0);
34 if (x == 1 || x == -1)
35 return ieee754sp_one(x < 0);
36 if (x == 10 || x == -10)
37 return ieee754sp_ten(x < 0);
39 xs = (x < 0);
40 if (xs) {
41 if (x == (1ULL << 63))
42 xm = (1ULL << 63); /* max neg can't be safely negated */
43 else
44 xm = -x;
45 } else {
46 xm = x;
48 xe = SP_FBITS + 3;
50 if (xm >> (SP_FBITS + 1 + 3)) {
51 /* shunt out overflow bits
53 while (xm >> (SP_FBITS + 1 + 3)) {
54 SPXSRSX1();
56 } else {
57 /* normalize in grs extended single precision */
58 while ((xm >> (SP_FBITS + 3)) == 0) {
59 xm <<= 1;
60 xe--;
63 return ieee754sp_format(xs, xe, xm);