MIPS: eBPF: Fix icache flush end address
[linux/fpc-iii.git] / arch / mips / math-emu / sp_sub.c
blob9f2ff72c3d6ba18659361353d5277c7a39d274bc
1 /* IEEE754 floating point arithmetic
2 * single precision
3 */
4 /*
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "ieee754sp.h"
24 union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
26 int s;
28 COMPXSP;
29 COMPYSP;
31 EXPLODEXSP;
32 EXPLODEYSP;
34 ieee754_clearcx();
36 FLUSHXSP;
37 FLUSHYSP;
39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754sp_nanxcpt(y);
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
53 return ieee754sp_nanxcpt(x);
55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
58 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
59 return y;
61 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
63 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
64 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
65 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
66 return x;
70 * Infinity handling
72 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
73 if (xs != ys)
74 return x;
75 ieee754_setcx(IEEE754_INVALID_OPERATION);
76 return ieee754sp_indef();
78 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
79 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
80 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
81 return ieee754sp_inf(ys ^ 1);
83 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
84 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
85 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
86 return x;
89 * Zero handling
91 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
92 if (xs != ys)
93 return x;
94 else
95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
97 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
98 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
99 return x;
101 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
102 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
103 /* quick fix up */
104 SPSIGN(y) ^= 1;
105 return y;
107 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
108 SPDNORMX;
109 /* fall through */
111 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
112 SPDNORMY;
113 break;
115 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
116 SPDNORMX;
117 break;
119 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
120 break;
122 /* flip sign of y and handle as add */
123 ys ^= 1;
125 assert(xm & SP_HIDDEN_BIT);
126 assert(ym & SP_HIDDEN_BIT);
129 /* provide guard,round and stick bit space */
130 xm <<= 3;
131 ym <<= 3;
133 if (xe > ye) {
135 * have to shift y fraction right to align
137 s = xe - ye;
138 ym = XSPSRS(ym, s);
139 ye += s;
140 } else if (ye > xe) {
142 * have to shift x fraction right to align
144 s = ye - xe;
145 xm = XSPSRS(xm, s);
146 xe += s;
148 assert(xe == ye);
149 assert(xe <= SP_EMAX);
151 if (xs == ys) {
152 /* generate 28 bit result of adding two 27 bit numbers
154 xm = xm + ym;
156 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
157 SPXSRSX1(); /* shift preserving sticky */
159 } else {
160 if (xm >= ym) {
161 xm = xm - ym;
162 } else {
163 xm = ym - xm;
164 xs = ys;
166 if (xm == 0) {
167 if (ieee754_csr.rm == FPU_CSR_RD)
168 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */
169 else
170 return ieee754sp_zero(0); /* other round modes => sign = 1 */
172 /* normalize to rounding precision
174 while ((xm >> (SP_FBITS + 3)) == 0) {
175 xm <<= 1;
176 xe--;
180 return ieee754sp_format(xs, xe, xm);