MIPS: eBPF: Fix icache flush end address
[linux/fpc-iii.git] / arch / mips / pistachio / irq.c
blob709a8219073ac772d1aaf6d6ab5bd24a4115b820
1 /*
2 * Pistachio IRQ setup
4 * Copyright (C) 2014 Google, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
11 #include <linux/init.h>
12 #include <linux/irqchip.h>
13 #include <linux/kernel.h>
15 #include <asm/cpu-features.h>
16 #include <asm/irq_cpu.h>
18 void __init arch_init_irq(void)
20 pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off");
21 pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off");
23 if (!cpu_has_veic)
24 mips_cpu_irq_init();
26 irqchip_init();