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MIPS: eBPF: Fix icache flush end address
[linux/fpc-iii.git] / drivers / staging / mt7621-mmc / sd.c
blob0379f9c96f2a99357d128a20b94feac63c24ae5c
1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 *
10 * MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/spinlock.h>
40 #include <linux/platform_device.h>
41
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/mmc.h>
44 #include <linux/mmc/sd.h>
45 #include <linux/mmc/sdio.h>
46
47 #include <asm/mach-ralink/ralink_regs.h>
48
49 #include "board.h"
50 #include "dbg.h"
51 #include "mt6575_sd.h"
52
53 #ifdef CONFIG_SOC_MT7621
54 #define RALINK_SYSCTL_BASE 0xbe000000
55 #else
56 #define RALINK_SYSCTL_BASE 0xb0000000
57 #endif
58
59 #define DRV_NAME "mtk-sd"
60
61 #if defined(CONFIG_SOC_MT7620)
62 #define HOST_MAX_MCLK (48000000) /* +/- by chhung */
63 #elif defined(CONFIG_SOC_MT7621)
64 #define HOST_MAX_MCLK (50000000) /* +/- by chhung */
65 #endif
66 #define HOST_MIN_MCLK (260000)
67
68 #define HOST_MAX_BLKSZ (2048)
69
70 #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
71
72 #define GPIO_PULL_DOWN (0)
73 #define GPIO_PULL_UP (1)
74
75 #define DEFAULT_DEBOUNCE (8) /* 8 cycles */
76 #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
77
78 #define CMD_TIMEOUT (HZ / 10) /* 100ms */
79 #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */
80
81 #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
82
83 #define MAX_GPD_NUM (1 + 1) /* one null gpd */
84 #define MAX_BD_NUM (1024)
85
86 #define MAX_HW_SGMTS (MAX_BD_NUM)
87 #define MAX_SGMT_SZ (MAX_DMA_CNT)
88 #define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
89
90 static int cd_active_low = 1;
91
92 //=================================
93 #define PERI_MSDC0_PDN (15)
94 //#define PERI_MSDC1_PDN (16)
95 //#define PERI_MSDC2_PDN (17)
96 //#define PERI_MSDC3_PDN (18)
97
98 /* +++ by chhung */
99 struct msdc_hw msdc0_hw = {
100 .clk_src = 0,
101 .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE,
102 // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
103 };
104
105 /* end of +++ */
106
107 static int msdc_rsp[] = {
108 0, /* RESP_NONE */
109 1, /* RESP_R1 */
110 2, /* RESP_R2 */
111 3, /* RESP_R3 */
112 4, /* RESP_R4 */
113 1, /* RESP_R5 */
114 1, /* RESP_R6 */
115 1, /* RESP_R7 */
116 7, /* RESP_R1b */
117 };
118
119 #define msdc_dma_on() sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO)
120
121 static void msdc_reset_hw(struct msdc_host *host)
122 {
123 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
124 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
125 cpu_relax();
126 }
127
128 #define msdc_clr_int() \
129 do { \
130 volatile u32 val = readl(host->base + MSDC_INT); \
131 writel(val, host->base + MSDC_INT); \
132 } while (0)
133
134 static void msdc_clr_fifo(struct msdc_host *host)
135 {
136 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
137 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
138 cpu_relax();
139 }
140
141 #define msdc_irq_save(val) \
142 do { \
143 val = readl(host->base + MSDC_INTEN); \
144 sdr_clr_bits(host->base + MSDC_INTEN, val); \
145 } while (0)
146
147 /* clock source for host: global */
148 #if defined(CONFIG_SOC_MT7620)
149 static u32 hclks[] = {48000000}; /* +/- by chhung */
150 #elif defined(CONFIG_SOC_MT7621)
151 static u32 hclks[] = {50000000}; /* +/- by chhung */
152 #endif
153
154 #define sdc_is_busy() (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY)
155 #define sdc_is_cmd_busy() (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY)
156
157 #define sdc_send_cmd(cmd, arg) \
158 do { \
159 writel((arg), host->base + SDC_ARG); \
160 writel((cmd), host->base + SDC_CMD); \
161 } while (0)
162
163 /* +++ by chhung */
164 #ifndef __ASSEMBLY__
165 #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
166 #else
167 #define PHYSADDR(a) ((a) & 0x1fffffff)
168 #endif
169 /* end of +++ */
170 static unsigned int msdc_do_command(struct msdc_host *host,
171 struct mmc_command *cmd,
172 int tune,
173 unsigned long timeout);
174
175 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);
176
177 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
178 {
179 u32 timeout, clk_ns;
180
181 host->timeout_ns = ns;
182 host->timeout_clks = clks;
183
184 clk_ns = 1000000000UL / host->sclk;
185 timeout = ns / clk_ns + clks;
186 timeout = timeout >> 16; /* in 65536 sclk cycle unit */
187 timeout = timeout > 1 ? timeout - 1 : 0;
188 timeout = timeout > 255 ? 255 : timeout;
189
190 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
191 }
192
193 static void msdc_tasklet_card(struct work_struct *work)
194 {
195 struct msdc_host *host = (struct msdc_host *)container_of(work,
196 struct msdc_host, card_delaywork.work);
197 u32 inserted;
198 u32 status = 0;
199
200 spin_lock(&host->lock);
201
202 status = readl(host->base + MSDC_PS);
203 if (cd_active_low)
204 inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
205 else
206 inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
207
208 /* Make sure: handle the last interrupt */
209 host->card_inserted = inserted;
210
211 if (!host->suspend) {
212 host->mmc->f_max = HOST_MAX_MCLK;
213 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
214 }
215
216 spin_unlock(&host->lock);
217 }
218
219 static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)
220 {
221 u32 val;
222
223 BUG_ON(clksrc > 3);
224
225 val = readl(host->base + MSDC_CLKSRC_REG);
226 if (readl(host->base + MSDC_ECO_VER) >= 4) {
227 val &= ~(0x3 << clk_src_bit[host->id]);
228 val |= clksrc << clk_src_bit[host->id];
229 } else {
230 val &= ~0x3; val |= clksrc;
231 }
232 writel(val, host->base + MSDC_CLKSRC_REG);
233
234 host->hclk = hclks[clksrc];
235 host->hw->clk_src = clksrc;
236 }
237 #endif /* end of --- */
238
239 static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
240 {
241 //struct msdc_hw *hw = host->hw;
242 u32 mode;
243 u32 flags;
244 u32 div;
245 u32 sclk;
246 u32 hclk = host->hclk;
247 //u8 clksrc = hw->clk_src;
248
249 if (!hz) { // set mmc system clock to 0 ?
250 msdc_reset_hw(host);
251 return;
252 }
253
254 msdc_irq_save(flags);
255
256 if (ddr) {
257 mode = 0x2; /* ddr mode and use divisor */
258 if (hz >= (hclk >> 2)) {
259 div = 1; /* mean div = 1/4 */
260 sclk = hclk >> 2; /* sclk = clk / 4 */
261 } else {
262 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
263 sclk = (hclk >> 2) / div;
264 }
265 } else if (hz >= hclk) { /* bug fix */
266 mode = 0x1; /* no divisor and divisor is ignored */
267 div = 0;
268 sclk = hclk;
269 } else {
270 mode = 0x0; /* use divisor */
271 if (hz >= (hclk >> 1)) {
272 div = 0; /* mean div = 1/2 */
273 sclk = hclk >> 1; /* sclk = clk / 2 */
274 } else {
275 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
276 sclk = (hclk >> 2) / div;
277 }
278 }
279
280 /* set clock mode and divisor */
281 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, mode);
282 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKDIV, div);
283
284 /* wait clock stable */
285 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
286 cpu_relax();
287
288 host->sclk = sclk;
289 host->mclk = hz;
290 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
291
292 sdr_set_bits(host->base + MSDC_INTEN, flags);
293 }
294
295 /* Fix me. when need to abort */
296 static void msdc_abort_data(struct msdc_host *host)
297 {
298 struct mmc_command *stop = host->mrq->stop;
299
300 dev_err(mmc_dev(host->mmc), "%d -> Need to Abort.\n", host->id);
301
302 msdc_reset_hw(host);
303 msdc_clr_fifo(host);
304 msdc_clr_int();
305
306 // need to check FIFO count 0 ?
307
308 if (stop) { /* try to stop, but may not success */
309 dev_err(mmc_dev(host->mmc), "%d -> stop when abort CMD<%d>\n",
310 host->id, stop->opcode);
311 (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
312 }
313
314 //if (host->mclk >= 25000000) {
315 // msdc_set_mclk(host, 0, host->mclk >> 1);
316 //}
317 }
318
319 #ifdef CONFIG_PM
320 /*
321 register as callback function of WIFI(combo_sdio_register_pm) .
322 can called by msdc_drv_suspend/resume too.
323 */
324 static void msdc_pm(pm_message_t state, void *data)
325 {
326 struct msdc_host *host = (struct msdc_host *)data;
327 int evt = state.event;
328
329 if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
330 if (host->suspend) /* already suspend */ /* default 0*/
331 return;
332
333 /* for memory card. already power off by mmc */
334 if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
335 return;
336
337 host->suspend = 1;
338 host->pm_state = state; /* default PMSG_RESUME */
339
340 } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
341 if (!host->suspend)
342 return;
343
344 /* No PM resume when USR suspend */
345 if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
346 dev_err(mmc_dev(host->mmc),
347 "%d -> PM Resume when in USR Suspend\n",
348 host->id); /* won't happen. */
349 return;
350 }
351
352 host->suspend = 0;
353 host->pm_state = state;
354
355 }
356 }
357 #endif
358
359 static inline u32 msdc_cmd_find_resp(struct mmc_command *cmd)
360 {
361 u32 opcode = cmd->opcode;
362 u32 resp;
363
364 if (opcode == MMC_SET_RELATIVE_ADDR) {
365 resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
366 } else if (opcode == MMC_FAST_IO) {
367 resp = RESP_R4;
368 } else if (opcode == MMC_GO_IRQ_STATE) {
369 resp = RESP_R5;
370 } else if (opcode == MMC_SELECT_CARD) {
371 resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
372 } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {
373 resp = RESP_R1; /* SDIO workaround. */
374 } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {
375 resp = RESP_R1;
376 } else {
377 switch (mmc_resp_type(cmd)) {
378 case MMC_RSP_R1:
379 resp = RESP_R1;
380 break;
381 case MMC_RSP_R1B:
382 resp = RESP_R1B;
383 break;
384 case MMC_RSP_R2:
385 resp = RESP_R2;
386 break;
387 case MMC_RSP_R3:
388 resp = RESP_R3;
389 break;
390 case MMC_RSP_NONE:
391 default:
392 resp = RESP_NONE;
393 break;
394 }
395 }
396
397 return resp;
398 }
399
400 /*--------------------------------------------------------------------------*/
401 /* mmc_host_ops members */
402 /*--------------------------------------------------------------------------*/
403 static unsigned int msdc_command_start(struct msdc_host *host,
404 struct mmc_command *cmd,
405 unsigned long timeout)
406 {
407 u32 opcode = cmd->opcode;
408 u32 rawcmd;
409 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
410 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
411 MSDC_INT_ACMD19_DONE;
412
413 u32 resp;
414 unsigned long tmo;
415
416 /* Protocol layer does not provide response type, but our hardware needs
417 * to know exact type, not just size!
418 */
419 resp = msdc_cmd_find_resp(cmd);
420
421 cmd->error = 0;
422 /* rawcmd :
423 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
424 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
425 */
426 rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
427
428 if (opcode == MMC_READ_MULTIPLE_BLOCK) {
429 rawcmd |= (2 << 11);
430 } else if (opcode == MMC_READ_SINGLE_BLOCK) {
431 rawcmd |= (1 << 11);
432 } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
433 rawcmd |= ((2 << 11) | (1 << 13));
434 } else if (opcode == MMC_WRITE_BLOCK) {
435 rawcmd |= ((1 << 11) | (1 << 13));
436 } else if (opcode == SD_IO_RW_EXTENDED) {
437 if (cmd->data->flags & MMC_DATA_WRITE)
438 rawcmd |= (1 << 13);
439 if (cmd->data->blocks > 1)
440 rawcmd |= (2 << 11);
441 else
442 rawcmd |= (1 << 11);
443 } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
444 rawcmd |= (1 << 14);
445 } else if ((opcode == SD_APP_SEND_SCR) ||
446 (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
447 (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
448 (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
449 (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
450 rawcmd |= (1 << 11);
451 } else if (opcode == MMC_STOP_TRANSMISSION) {
452 rawcmd |= (1 << 14);
453 rawcmd &= ~(0x0FFF << 16);
454 }
455
456 tmo = jiffies + timeout;
457
458 if (opcode == MMC_SEND_STATUS) {
459 for (;;) {
460 if (!sdc_is_cmd_busy())
461 break;
462
463 if (time_after(jiffies, tmo)) {
464 dev_err(mmc_dev(host->mmc),
465 "%d -> XXX cmd_busy timeout: before CMD<%d>\n",
466 host->id, opcode);
467 cmd->error = -ETIMEDOUT;
468 msdc_reset_hw(host);
469 goto end;
470 }
471 }
472 } else {
473 for (;;) {
474 if (!sdc_is_busy())
475 break;
476 if (time_after(jiffies, tmo)) {
477 dev_err(mmc_dev(host->mmc),
478 "%d -> XXX sdc_busy timeout: before CMD<%d>\n",
479 host->id, opcode);
480 cmd->error = -ETIMEDOUT;
481 msdc_reset_hw(host);
482 goto end;
483 }
484 }
485 }
486
487 //BUG_ON(in_interrupt());
488 host->cmd = cmd;
489 host->cmd_rsp = resp;
490
491 init_completion(&host->cmd_done);
492
493 sdr_set_bits(host->base + MSDC_INTEN, wints);
494 sdc_send_cmd(rawcmd, cmd->arg);
495
496 end:
497 return cmd->error;
498 }
499
500 static unsigned int msdc_command_resp(struct msdc_host *host,
501 struct mmc_command *cmd,
502 int tune,
503 unsigned long timeout)
504 __must_hold(&host->lock)
505 {
506 u32 opcode = cmd->opcode;
507 //u32 rawcmd;
508 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
509 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
510 MSDC_INT_ACMD19_DONE;
511
512 BUG_ON(in_interrupt());
513 //init_completion(&host->cmd_done);
514 //sdr_set_bits(host->base + MSDC_INTEN, wints);
515
516 spin_unlock(&host->lock);
517 if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {
518 dev_err(mmc_dev(host->mmc),
519 "%d -> XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\n",
520 host->id, opcode, cmd->arg);
521 cmd->error = -ETIMEDOUT;
522 msdc_reset_hw(host);
523 }
524 spin_lock(&host->lock);
525
526 sdr_clr_bits(host->base + MSDC_INTEN, wints);
527 host->cmd = NULL;
528
529 //end:
530 /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
531
532 if (!tune)
533 return cmd->error;
534
535 /* memory card CRC */
536 if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) {
537 /* check if has data phase */
538 if (readl(host->base + SDC_CMD) & 0x1800) {
539 msdc_abort_data(host);
540 } else {
541 /* do basic: reset*/
542 msdc_reset_hw(host);
543 msdc_clr_fifo(host);
544 msdc_clr_int();
545 }
546 cmd->error = msdc_tune_cmdrsp(host, cmd);
547 }
548
549 // check DAT0
550 /* if (resp == RESP_R1B) {
551 while ((readl(host->base + MSDC_PS) & 0x10000) != 0x10000);
552 } */
553 /* CMD12 Error Handle */
554
555 return cmd->error;
556 }
557
558 static unsigned int msdc_do_command(struct msdc_host *host,
559 struct mmc_command *cmd,
560 int tune,
561 unsigned long timeout)
562 {
563 if (msdc_command_start(host, cmd, timeout))
564 goto end;
565
566 if (msdc_command_resp(host, cmd, tune, timeout))
567 goto end;
568
569 end:
570
571 return cmd->error;
572 }
573
574 static void msdc_dma_start(struct msdc_host *host)
575 {
576 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
577
578 sdr_set_bits(host->base + MSDC_INTEN, wints);
579 //dsb(); /* --- by chhung */
580 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
581 }
582
583 static void msdc_dma_stop(struct msdc_host *host)
584 {
585 //u32 retries=500;
586 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
587
588 //while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
589
590 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
591 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
592 ;
593
594 //dsb(); /* --- by chhung */
595 sdr_clr_bits(host->base + MSDC_INTEN, wints); /* Not just xfer_comp */
596 }
597
598 /* calc checksum */
599 static u8 msdc_dma_calcs(u8 *buf, u32 len)
600 {
601 u32 i, sum = 0;
602
603 for (i = 0; i < len; i++)
604 sum += buf[i];
605 return 0xFF - (u8)sum;
606 }
607
608 static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
609 struct scatterlist *sg_cmd, unsigned int sglen)
610 {
611 struct scatterlist *sg;
612 struct gpd *gpd;
613 struct bd *bd;
614 u32 j;
615
616 BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
617
618 gpd = dma->gpd;
619 bd = dma->bd;
620
621 /* modify gpd*/
622 //gpd->intr = 0;
623 gpd->hwo = 1; /* hw will clear it */
624 gpd->bdp = 1;
625 gpd->chksum = 0; /* need to clear first. */
626 gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);
627
628 /* modify bd*/
629 for_each_sg(sg_cmd, sg, sglen, j) {
630 bd[j].blkpad = 0;
631 bd[j].dwpad = 0;
632 bd[j].ptr = (void *)sg_dma_address(sg);
633 bd[j].buflen = sg_dma_len(sg);
634
635 if (j == sglen - 1)
636 bd[j].eol = 1; /* the last bd */
637 else
638 bd[j].eol = 0;
639
640 bd[j].chksum = 0; /* checksume need to clear first */
641 bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);
642 }
643
644 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
645 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
646 MSDC_BRUST_64B);
647 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
648
649 writel(PHYSADDR((u32)dma->gpd_addr), host->base + MSDC_DMA_SA);
650 }
651
652 static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)
653 __must_hold(&host->lock)
654 {
655 struct msdc_host *host = mmc_priv(mmc);
656 struct mmc_command *cmd;
657 struct mmc_data *data;
658 //u32 intsts = 0;
659 int read = 1, send_type = 0;
660
661 #define SND_DAT 0
662 #define SND_CMD 1
663
664 BUG_ON(!mmc);
665 BUG_ON(!mrq);
666
667 host->error = 0;
668
669 cmd = mrq->cmd;
670 data = mrq->cmd->data;
671
672 if (!data) {
673 send_type = SND_CMD;
674 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
675 goto done;
676 } else {
677 BUG_ON(data->blksz > HOST_MAX_BLKSZ);
678 send_type = SND_DAT;
679
680 data->error = 0;
681 read = data->flags & MMC_DATA_READ ? 1 : 0;
682 host->data = data;
683 host->xfer_size = data->blocks * data->blksz;
684 host->blksz = data->blksz;
685
686 if (read) {
687 if ((host->timeout_ns != data->timeout_ns) ||
688 (host->timeout_clks != data->timeout_clks)) {
689 msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
690 }
691 }
692
693 writel(data->blocks, host->base + SDC_BLK_NUM);
694 //msdc_clr_fifo(host); /* no need */
695
696 msdc_dma_on(); /* enable DMA mode first!! */
697 init_completion(&host->xfer_done);
698
699 /* start the command first*/
700 if (msdc_command_start(host, cmd, CMD_TIMEOUT) != 0)
701 goto done;
702
703 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,
704 data->sg_len,
705 mmc_get_dma_dir(data));
706 msdc_dma_setup(host, &host->dma, data->sg,
707 data->sg_count);
708
709 /* then wait command done */
710 if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
711 goto done;
712
713 /* for read, the data coming too fast, then CRC error
714 start DMA no business with CRC. */
715 //init_completion(&host->xfer_done);
716 msdc_dma_start(host);
717
718 spin_unlock(&host->lock);
719 if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
720 dev_err(mmc_dev(host->mmc),
721 "%d -> XXX CMD<%d> wait xfer_done<%d> timeout!!\n",
722 host->id, cmd->opcode,
723 data->blocks * data->blksz);
724 dev_err(mmc_dev(host->mmc),
725 "%d -> DMA_SA = 0x%x\n",
726 host->id, readl(host->base + MSDC_DMA_SA));
727 dev_err(mmc_dev(host->mmc),
728 "%d -> DMA_CA = 0x%x\n",
729 host->id, readl(host->base + MSDC_DMA_CA));
730 dev_err(mmc_dev(host->mmc),
731 "%d -> DMA_CTRL = 0x%x\n",
732 host->id, readl(host->base + MSDC_DMA_CTRL));
733 dev_err(mmc_dev(host->mmc),
734 "%d -> DMA_CFG = 0x%x\n",
735 host->id, readl(host->base + MSDC_DMA_CFG));
736 data->error = -ETIMEDOUT;
737
738 msdc_reset_hw(host);
739 msdc_clr_fifo(host);
740 msdc_clr_int();
741 }
742 spin_lock(&host->lock);
743 msdc_dma_stop(host);
744
745 /* Last: stop transfer */
746 if (data->stop) {
747 if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)
748 goto done;
749 }
750 }
751
752 done:
753 if (data) {
754 host->data = NULL;
755 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
756 mmc_get_dma_dir(data));
757 host->blksz = 0;
758 }
759
760 if (mrq->cmd->error)
761 host->error = 0x001;
762 if (mrq->data && mrq->data->error)
763 host->error |= 0x010;
764 if (mrq->stop && mrq->stop->error)
765 host->error |= 0x100;
766
767 return host->error;
768 }
769
770 static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
771 {
772 struct mmc_command cmd;
773 struct mmc_request mrq;
774 u32 err;
775
776 memset(&cmd, 0, sizeof(struct mmc_command));
777 cmd.opcode = MMC_APP_CMD;
778 cmd.arg = host->app_cmd_arg;
779 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
780
781 memset(&mrq, 0, sizeof(struct mmc_request));
782 mrq.cmd = &cmd; cmd.mrq = &mrq;
783 cmd.data = NULL;
784
785 err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
786 return err;
787 }
788
789 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)
790 {
791 int result = -1;
792 u32 rsmpl, cur_rsmpl, orig_rsmpl;
793 u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
794 u32 skip = 1;
795
796 /* ==== don't support 3.0 now ====
797 1: R_SMPL[1]
798 2: PAD_CMD_RESP_RXDLY[26:22]
799 ==========================*/
800
801 // save the previous tune result
802 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl);
803 sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
804 &orig_rrdly);
805
806 rrdly = 0;
807 do {
808 for (rsmpl = 0; rsmpl < 2; rsmpl++) {
809 /* Lv1: R_SMPL[1] */
810 cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
811 if (skip == 1) {
812 skip = 0;
813 continue;
814 }
815 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL,
816 cur_rsmpl);
817
818 if (host->app_cmd) {
819 result = msdc_app_cmd(host->mmc, host);
820 if (result) {
821 dev_err(mmc_dev(host->mmc),
822 "%d -> TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\n",
823 host->id,
824 host->mrq->cmd->opcode,
825 cur_rrdly, cur_rsmpl);
826 continue;
827 }
828 }
829 result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
830 dev_err(mmc_dev(host->mmc),
831 "%d -> TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\n",
832 host->id, cmd->opcode,
833 (result == 0) ? "PASS" : "FAIL", cur_rrdly,
834 cur_rsmpl);
835
836 if (result == 0)
837 return 0;
838 if (result != -EIO) {
839 dev_err(mmc_dev(host->mmc),
840 "%d -> TUNE_CMD<%d> Error<%d> not -EIO\n",
841 host->id, cmd->opcode, result);
842 return result;
843 }
844
845 /* should be EIO */
846 /* check if has data phase */
847 if (readl(host->base + SDC_CMD) & 0x1800)
848 msdc_abort_data(host);
849 }
850
851 /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
852 cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
853 sdr_set_field(host->base + MSDC_PAD_TUNE,
854 MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
855 } while (++rrdly < 32);
856
857 return result;
858 }
859
860 /* Support SD2.0 Only */
861 static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
862 {
863 struct msdc_host *host = mmc_priv(mmc);
864 u32 ddr = 0;
865 u32 dcrc = 0;
866 u32 rxdly, cur_rxdly0, cur_rxdly1;
867 u32 dsmpl, cur_dsmpl, orig_dsmpl;
868 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
869 u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
870 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
871 u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
872 int result = -1;
873 u32 skip = 1;
874
875 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
876
877 /* Tune Method 2. */
878 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
879
880 rxdly = 0;
881 do {
882 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
883 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
884 if (skip == 1) {
885 skip = 0;
886 continue;
887 }
888 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL,
889 cur_dsmpl);
890
891 if (host->app_cmd) {
892 result = msdc_app_cmd(host->mmc, host);
893 if (result) {
894 dev_err(mmc_dev(host->mmc),
895 "%d -> TUNE_BREAD app_cmd<%d> failed\n",
896 host->id,
897 host->mrq->cmd->opcode);
898 continue;
899 }
900 }
901 result = msdc_do_request(mmc, mrq);
902
903 sdr_get_field(host->base + SDC_DCRC_STS,
904 SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG,
905 &dcrc); /* RO */
906 if (!ddr)
907 dcrc &= ~SDC_DCRC_STS_NEG;
908 dev_err(mmc_dev(host->mmc),
909 "%d -> TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\n",
910 host->id,
911 (result == 0 && dcrc == 0) ? "PASS" : "FAIL",
912 dcrc, readl(host->base + MSDC_DAT_RDDLY0),
913 readl(host->base + MSDC_DAT_RDDLY1),
914 cur_dsmpl);
915
916 /* Fix me: result is 0, but dcrc is still exist */
917 if (result == 0 && dcrc == 0) {
918 goto done;
919 } else {
920 /* there is a case: command timeout, and data phase not processed */
921 if (mrq->data->error != 0 &&
922 mrq->data->error != -EIO) {
923 dev_err(mmc_dev(host->mmc),
924 "%d -> TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
925 host->id, result,
926 mrq->cmd->error,
927 mrq->data->error);
928 goto done;
929 }
930 }
931 }
932
933 cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0);
934 cur_rxdly1 = readl(host->base + MSDC_DAT_RDDLY1);
935
936 /* E1 ECO. YD: Reverse */
937 if (readl(host->base + MSDC_ECO_VER) >= 4) {
938 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
939 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
940 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
941 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
942 orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
943 orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
944 orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
945 orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
946 } else {
947 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
948 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
949 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
950 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
951 orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
952 orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
953 orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
954 orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
955 }
956
957 if (ddr) {
958 cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
959 cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
960 cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
961 cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
962 } else {
963 cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
964 cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
965 cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
966 cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
967 }
968 cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
969 cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
970 cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
971 cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
972
973 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
974 cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
975
976 writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0);
977 writel(cur_rxdly1, host->base + MSDC_DAT_RDDLY1);
978
979 } while (++rxdly < 32);
980
981 done:
982 return result;
983 }
984
985 static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)
986 {
987 struct msdc_host *host = mmc_priv(mmc);
988
989 u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
990 u32 dsmpl, cur_dsmpl, orig_dsmpl;
991 u32 rxdly, cur_rxdly0;
992 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
993 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
994 int result = -1;
995 u32 skip = 1;
996
997 // MSDC_IOCON_DDR50CKD need to check. [Fix me]
998
999 sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY,
1000 &orig_wrrdly);
1001 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1002
1003 /* Tune Method 2. just DAT0 */
1004 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1005 cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0);
1006
1007 /* E1 ECO. YD: Reverse */
1008 if (readl(host->base + MSDC_ECO_VER) >= 4) {
1009 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1010 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1011 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1012 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1013 } else {
1014 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1015 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1016 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1017 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1018 }
1019
1020 rxdly = 0;
1021 do {
1022 wrrdly = 0;
1023 do {
1024 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1025 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1026 if (skip == 1) {
1027 skip = 0;
1028 continue;
1029 }
1030 sdr_set_field(host->base + MSDC_IOCON,
1031 MSDC_IOCON_DSPL, cur_dsmpl);
1032
1033 if (host->app_cmd) {
1034 result = msdc_app_cmd(host->mmc, host);
1035 if (result) {
1036 dev_err(mmc_dev(host->mmc),
1037 "%d -> TUNE_BWRITE app_cmd<%d> failed\n",
1038 host->id,
1039 host->mrq->cmd->opcode);
1040 continue;
1041 }
1042 }
1043 result = msdc_do_request(mmc, mrq);
1044
1045 dev_err(mmc_dev(host->mmc),
1046 "%d -> TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\n",
1047 host->id,
1048 result == 0 ? "PASS" : "FAIL",
1049 cur_dsmpl, cur_wrrdly, cur_rxdly0);
1050
1051 if (result == 0) {
1052 goto done;
1053 } else {
1054 /* there is a case: command timeout, and data phase not processed */
1055 if (mrq->data->error != -EIO) {
1056 dev_err(mmc_dev(host->mmc),
1057 "%d -> TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
1058 host->id, result,
1059 mrq->cmd->error,
1060 mrq->data->error);
1061 goto done;
1062 }
1063 }
1064 }
1065 cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
1066 sdr_set_field(host->base + MSDC_PAD_TUNE,
1067 MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
1068 } while (++wrrdly < 32);
1069
1070 cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
1071 cur_dat1 = orig_dat1;
1072 cur_dat2 = orig_dat2;
1073 cur_dat3 = orig_dat3;
1074
1075 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1076 writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0);
1077 } while (++rxdly < 32);
1078
1079 done:
1080 return result;
1081 }
1082
1083 static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
1084 {
1085 struct mmc_command cmd;
1086 struct mmc_request mrq;
1087 u32 err;
1088
1089 memset(&cmd, 0, sizeof(struct mmc_command));
1090 cmd.opcode = MMC_SEND_STATUS;
1091 if (mmc->card) {
1092 cmd.arg = mmc->card->rca << 16;
1093 } else {
1094 dev_err(mmc_dev(host->mmc), "%d -> cmd13 mmc card is null\n",
1095 host->id);
1096 cmd.arg = host->app_cmd_arg;
1097 }
1098 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
1099
1100 memset(&mrq, 0, sizeof(struct mmc_request));
1101 mrq.cmd = &cmd; cmd.mrq = &mrq;
1102 cmd.data = NULL;
1103
1104 err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
1105
1106 if (status)
1107 *status = cmd.resp[0];
1108
1109 return err;
1110 }
1111
1112 static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
1113 {
1114 u32 err = 0;
1115 u32 status = 0;
1116
1117 do {
1118 err = msdc_get_card_status(mmc, host, &status);
1119 if (err)
1120 return err;
1121 /* need cmd12? */
1122 dev_err(mmc_dev(host->mmc), "%d -> cmd<13> resp<0x%x>\n",
1123 host->id, status);
1124 } while (R1_CURRENT_STATE(status) == 7);
1125
1126 return err;
1127 }
1128
1129 /* failed when msdc_do_request */
1130 static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
1131 {
1132 struct msdc_host *host = mmc_priv(mmc);
1133 struct mmc_data *data;
1134 //u32 base = host->base;
1135 int ret = 0, read;
1136
1137 data = mrq->cmd->data;
1138
1139 read = data->flags & MMC_DATA_READ ? 1 : 0;
1140
1141 if (read) {
1142 if (data->error == -EIO)
1143 ret = msdc_tune_bread(mmc, mrq);
1144 } else {
1145 ret = msdc_check_busy(mmc, host);
1146 if (ret) {
1147 dev_err(mmc_dev(host->mmc),
1148 "%d -> XXX cmd13 wait program done failed\n",
1149 host->id);
1150 return ret;
1151 }
1152 /* CRC and TO */
1153 /* Fix me: don't care card status? */
1154 ret = msdc_tune_bwrite(mmc, mrq);
1155 }
1156
1157 return ret;
1158 }
1159
1160 /* ops.request */
1161 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1162 {
1163 struct msdc_host *host = mmc_priv(mmc);
1164
1165 WARN_ON(host->mrq);
1166
1167 /* start to process */
1168 spin_lock(&host->lock);
1169
1170 host->mrq = mrq;
1171
1172 if (msdc_do_request(mmc, mrq)) {
1173 if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)
1174 msdc_tune_request(mmc, mrq);
1175 }
1176
1177 /* ==== when request done, check if app_cmd ==== */
1178 if (mrq->cmd->opcode == MMC_APP_CMD) {
1179 host->app_cmd = 1;
1180 host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
1181 } else {
1182 host->app_cmd = 0;
1183 //host->app_cmd_arg = 0;
1184 }
1185
1186 host->mrq = NULL;
1187
1188 spin_unlock(&host->lock);
1189
1190 mmc_request_done(mmc, mrq);
1191
1192 return;
1193 }
1194
1195 /* called by ops.set_ios */
1196 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1197 {
1198 u32 val = readl(host->base + SDC_CFG);
1199
1200 val &= ~SDC_CFG_BUSWIDTH;
1201
1202 switch (width) {
1203 default:
1204 case MMC_BUS_WIDTH_1:
1205 width = 1;
1206 val |= (MSDC_BUS_1BITS << 16);
1207 break;
1208 case MMC_BUS_WIDTH_4:
1209 val |= (MSDC_BUS_4BITS << 16);
1210 break;
1211 case MMC_BUS_WIDTH_8:
1212 val |= (MSDC_BUS_8BITS << 16);
1213 break;
1214 }
1215
1216 writel(val, host->base + SDC_CFG);
1217 }
1218
1219 /* ops.set_ios */
1220 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1221 {
1222 struct msdc_host *host = mmc_priv(mmc);
1223 u32 ddr = 0;
1224
1225 #ifdef MT6575_SD_DEBUG
1226 static char *vdd[] = {
1227 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
1228 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
1229 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
1230 "3.40v", "3.50v", "3.60v"
1231 };
1232 static char *power_mode[] = {
1233 "OFF", "UP", "ON"
1234 };
1235 static char *bus_mode[] = {
1236 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
1237 };
1238 static char *timing[] = {
1239 "LEGACY", "MMC_HS", "SD_HS"
1240 };
1241
1242 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
1243 ios->clock / 1000, bus_mode[ios->bus_mode],
1244 (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
1245 power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
1246 #endif
1247
1248 msdc_set_buswidth(host, ios->bus_width);
1249
1250 /* Power control ??? */
1251 switch (ios->power_mode) {
1252 case MMC_POWER_OFF:
1253 case MMC_POWER_UP:
1254 break;
1255 case MMC_POWER_ON:
1256 host->power_mode = MMC_POWER_ON;
1257 break;
1258 default:
1259 break;
1260 }
1261
1262 /* Clock control */
1263 if (host->mclk != ios->clock) {
1264 if (ios->clock > 25000000) {
1265 //if (!(host->hw->flags & MSDC_REMOVABLE)) {
1266 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL,
1267 MSDC_SMPL_FALLING);
1268 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL,
1269 MSDC_SMPL_FALLING);
1270 //} /* for tuning debug */
1271 } else { /* default value */
1272 writel(0x00000000, host->base + MSDC_IOCON);
1273 // writel(0x00000000, host->base + MSDC_DAT_RDDLY0);
1274
1275 // for MT7620 E2 and afterward
1276 writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
1277
1278 writel(0x00000000, host->base + MSDC_DAT_RDDLY1);
1279 // writel(0x00000000, host->base + MSDC_PAD_TUNE);
1280
1281 // for MT7620 E2 and afterward
1282 writel(0x84101010, host->base + MSDC_PAD_TUNE);
1283 }
1284 msdc_set_mclk(host, ddr, ios->clock);
1285 }
1286 }
1287
1288 /* ops.get_ro */
1289 static int msdc_ops_get_ro(struct mmc_host *mmc)
1290 {
1291 struct msdc_host *host = mmc_priv(mmc);
1292 unsigned long flags;
1293 int ro = 0;
1294
1295 if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
1296 spin_lock_irqsave(&host->lock, flags);
1297 ro = (readl(host->base + MSDC_PS) >> 31);
1298 spin_unlock_irqrestore(&host->lock, flags);
1299 }
1300 return ro;
1301 }
1302
1303 /* ops.get_cd */
1304 static int msdc_ops_get_cd(struct mmc_host *mmc)
1305 {
1306 struct msdc_host *host = mmc_priv(mmc);
1307 unsigned long flags;
1308 int present = 1;
1309
1310 /* for sdio, MSDC_REMOVABLE not set, always return 1 */
1311 if (!(host->hw->flags & MSDC_REMOVABLE)) {
1312 /* For sdio, read H/W always get<1>, but may timeout some times */
1313 #if 1
1314 host->card_inserted = 1;
1315 return 1;
1316 #else
1317 host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
1318 return host->card_inserted;
1319 #endif
1320 }
1321
1322 /* MSDC_CD_PIN_EN set for card */
1323 if (host->hw->flags & MSDC_CD_PIN_EN) {
1324 spin_lock_irqsave(&host->lock, flags);
1325 // CD
1326 present = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
1327 if (cd_active_low)
1328 present = present ? 0 : 1;
1329 else
1330 present = present ? 1 : 0;
1331 host->card_inserted = present;
1332 spin_unlock_irqrestore(&host->lock, flags);
1333 } else {
1334 present = 0; /* TODO? Check DAT3 pins for card detection */
1335 }
1336
1337 return present;
1338 }
1339
1340 static struct mmc_host_ops mt_msdc_ops = {
1341 .request = msdc_ops_request,
1342 .set_ios = msdc_ops_set_ios,
1343 .get_ro = msdc_ops_get_ro,
1344 .get_cd = msdc_ops_get_cd,
1345 };
1346
1347 /*--------------------------------------------------------------------------*/
1348 /* interrupt handler */
1349 /*--------------------------------------------------------------------------*/
1350 static irqreturn_t msdc_irq(int irq, void *dev_id)
1351 {
1352 struct msdc_host *host = (struct msdc_host *)dev_id;
1353 struct mmc_data *data = host->data;
1354 struct mmc_command *cmd = host->cmd;
1355
1356 u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
1357 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
1358 MSDC_INT_ACMD19_DONE;
1359 u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;
1360
1361 u32 intsts = readl(host->base + MSDC_INT);
1362 u32 inten = readl(host->base + MSDC_INTEN); inten &= intsts;
1363
1364 writel(intsts, host->base + MSDC_INT); /* clear interrupts */
1365 /* MSG will cause fatal error */
1366
1367 /* card change interrupt */
1368 if (intsts & MSDC_INT_CDSC) {
1369 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
1370 return IRQ_HANDLED;
1371 schedule_delayed_work(&host->card_delaywork, HZ);
1372 /* tuning when plug card ? */
1373 }
1374
1375 /* transfer complete interrupt */
1376 if (data) {
1377 if (inten & MSDC_INT_XFER_COMPL) {
1378 data->bytes_xfered = host->xfer_size;
1379 complete(&host->xfer_done);
1380 }
1381
1382 if (intsts & datsts) {
1383 /* do basic reset, or stop command will sdc_busy */
1384 msdc_reset_hw(host);
1385 msdc_clr_fifo(host);
1386 msdc_clr_int();
1387
1388 if (intsts & MSDC_INT_DATTMO)
1389 data->error = -ETIMEDOUT;
1390 else if (intsts & MSDC_INT_DATCRCERR)
1391 data->error = -EIO;
1392
1393 //if(readl(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
1394 complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
1395 }
1396 }
1397
1398 /* command interrupts */
1399 if (cmd && (intsts & cmdsts)) {
1400 if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
1401 (intsts & MSDC_INT_ACMD19_DONE)) {
1402 u32 *rsp = &cmd->resp[0];
1403
1404 switch (host->cmd_rsp) {
1405 case RESP_NONE:
1406 break;
1407 case RESP_R2:
1408 *rsp++ = readl(host->base + SDC_RESP3);
1409 *rsp++ = readl(host->base + SDC_RESP2);
1410 *rsp++ = readl(host->base + SDC_RESP1);
1411 *rsp++ = readl(host->base + SDC_RESP0);
1412 break;
1413 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
1414 if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))
1415 *rsp = readl(host->base + SDC_ACMD_RESP);
1416 else
1417 *rsp = readl(host->base + SDC_RESP0);
1418 break;
1419 }
1420 } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
1421 cmd->error = -EIO;
1422 } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
1423 cmd->error = -ETIMEDOUT;
1424 msdc_reset_hw(host);
1425 msdc_clr_fifo(host);
1426 msdc_clr_int();
1427 }
1428 complete(&host->cmd_done);
1429 }
1430
1431 /* mmc irq interrupts */
1432 if (intsts & MSDC_INT_MMCIRQ)
1433 dev_info(mmc_dev(host->mmc), "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n",
1434 host->id, readl(host->base + SDC_CSTS));
1435
1436 return IRQ_HANDLED;
1437 }
1438
1439 /*--------------------------------------------------------------------------*/
1440 /* platform_driver members */
1441 /*--------------------------------------------------------------------------*/
1442 /* called by msdc_drv_probe/remove */
1443 static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
1444 {
1445 struct msdc_hw *hw = host->hw;
1446
1447 /* for sdio, not set */
1448 if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
1449 /* Pull down card detection pin since it is not avaiable */
1450 /*
1451 if (hw->config_gpio_pin)
1452 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
1453 */
1454 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1455 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1456 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1457 return;
1458 }
1459
1460 if (enable) {
1461 /* card detection circuit relies on the core power so that the core power
1462 * shouldn't be turned off. Here adds a reference count to keep
1463 * the core power alive.
1464 */
1465
1466 if (hw->config_gpio_pin) /* NULL */
1467 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
1468
1469 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1470 DEFAULT_DEBOUNCE);
1471 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1472 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1473
1474 /* not in document! Fix me */
1475 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1476 } else {
1477 if (hw->config_gpio_pin) /* NULL */
1478 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
1479
1480 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1481 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1482 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1483
1484 /* Here decreases a reference count to core power since card
1485 * detection circuit is shutdown.
1486 */
1487 }
1488 }
1489
1490 /* called by msdc_drv_probe */
1491 static void msdc_init_hw(struct msdc_host *host)
1492 {
1493
1494 /* Configure to MMC/SD mode */
1495 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
1496
1497 /* Reset */
1498 msdc_reset_hw(host);
1499 msdc_clr_fifo(host);
1500
1501 /* Disable card detection */
1502 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1503
1504 /* Disable and clear all interrupts */
1505 sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN));
1506 writel(readl(host->base + MSDC_INT), host->base + MSDC_INT);
1507
1508 #if 1
1509 /* reset tuning parameter */
1510 writel(0x00090000, host->base + MSDC_PAD_CTL0);
1511 writel(0x000A0000, host->base + MSDC_PAD_CTL1);
1512 writel(0x000A0000, host->base + MSDC_PAD_CTL2);
1513 // writel( 0x00000000, host->base + MSDC_PAD_TUNE);
1514
1515 // for MT7620 E2 and afterward
1516 writel(0x84101010, host->base + MSDC_PAD_TUNE);
1517
1518 // writel(0x00000000, host->base + MSDC_DAT_RDDLY0);
1519
1520 // for MT7620 E2 and afterward
1521 writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
1522
1523 writel(0x00000000, host->base + MSDC_DAT_RDDLY1);
1524 writel(0x00000000, host->base + MSDC_IOCON);
1525
1526 if (readl(host->base + MSDC_ECO_VER) >= 4) {
1527 if (host->id == 1) {
1528 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1529 MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
1530 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1531 MSDC_PATCH_BIT1_CMD_RSP, 1);
1532
1533 /* internal clock: latch read data */
1534 sdr_set_bits(host->base + MSDC_PATCH_BIT0,
1535 MSDC_PATCH_BIT_CKGEN_CK);
1536 }
1537 }
1538 #endif
1539
1540 /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
1541 pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
1542 set when kernel driver wants to use SDIO bus interrupt */
1543 /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
1544 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1545
1546 /* disable detect SDIO device interupt function */
1547 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1548
1549 /* eneable SMT for glitch filter */
1550 sdr_set_bits(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
1551 sdr_set_bits(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
1552 sdr_set_bits(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
1553
1554 #if 1
1555 /* set clk, cmd, dat pad driving */
1556 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4);
1557 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4);
1558 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);
1559 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);
1560 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);
1561 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);
1562 #else
1563 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
1564 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
1565 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
1566 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
1567 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
1568 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
1569 #endif
1570
1571 /* set sampling edge */
1572
1573 /* write crc timeout detection */
1574 sdr_set_field(host->base + MSDC_PATCH_BIT0, 1 << 30, 1);
1575
1576 /* Configure to default data timeout */
1577 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
1578
1579 msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
1580 }
1581
1582 /* called by msdc_drv_remove */
1583 static void msdc_deinit_hw(struct msdc_host *host)
1584 {
1585 /* Disable and clear all interrupts */
1586 sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN));
1587 writel(readl(host->base + MSDC_INT), host->base + MSDC_INT);
1588
1589 /* Disable card detection */
1590 msdc_enable_cd_irq(host, 0);
1591 }
1592
1593 /* init gpd and bd list in msdc_drv_probe */
1594 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1595 {
1596 struct gpd *gpd = dma->gpd;
1597 struct bd *bd = dma->bd;
1598 int i;
1599
1600 /* we just support one gpd, but gpd->next must be set for desc
1601 * DMA. That's why we alloc 2 gpd structurs.
1602 */
1603
1604 memset(gpd, 0, sizeof(struct gpd) * 2);
1605
1606 gpd->bdp = 1; /* hwo, cs, bd pointer */
1607 gpd->ptr = (void *)dma->bd_addr; /* physical address */
1608 gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));
1609
1610 memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);
1611 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1612 bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));
1613 }
1614
1615 static int msdc_drv_probe(struct platform_device *pdev)
1616 {
1617 struct resource *res;
1618 __iomem void *base;
1619 struct mmc_host *mmc;
1620 struct msdc_host *host;
1621 struct msdc_hw *hw;
1622 int ret;
1623
1624 hw = &msdc0_hw;
1625
1626 if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
1627 msdc0_hw.flags |= MSDC_WP_PIN_EN;
1628
1629 /* Allocate MMC host for this device */
1630 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1631 if (!mmc)
1632 return -ENOMEM;
1633
1634 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1635 base = devm_ioremap_resource(&pdev->dev, res);
1636 if (IS_ERR(base)) {
1637 ret = PTR_ERR(base);
1638 goto host_free;
1639 }
1640
1641 /* Set host parameters to mmc */
1642 mmc->ops = &mt_msdc_ops;
1643 mmc->f_min = HOST_MIN_MCLK;
1644 mmc->f_max = HOST_MAX_MCLK;
1645 mmc->ocr_avail = MSDC_OCR_AVAIL;
1646
1647 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1648
1649 //TODO: read this as bus-width from dt (via mmc_of_parse)
1650 mmc->caps |= MMC_CAP_4_BIT_DATA;
1651
1652 cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
1653
1654 if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll"))
1655 mmc->caps |= MMC_CAP_NEEDS_POLL;
1656
1657 /* MMC core transfer sizes tunable parameters */
1658 mmc->max_segs = MAX_HW_SGMTS;
1659
1660 mmc->max_seg_size = MAX_SGMT_SZ;
1661 mmc->max_blk_size = HOST_MAX_BLKSZ;
1662 mmc->max_req_size = MAX_REQ_SZ;
1663 mmc->max_blk_count = mmc->max_req_size;
1664
1665 host = mmc_priv(mmc);
1666 host->hw = hw;
1667 host->mmc = mmc;
1668 host->id = pdev->id;
1669 if (host->id < 0 || host->id >= 4)
1670 host->id = 0;
1671 host->error = 0;
1672
1673 host->irq = platform_get_irq(pdev, 0);
1674 if (host->irq < 0) {
1675 ret = -EINVAL;
1676 goto host_free;
1677 }
1678
1679 host->base = base;
1680 host->mclk = 0; /* mclk: the request clock of mmc sub-system */
1681 host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
1682 host->sclk = 0; /* sclk: the really clock after divition */
1683 host->pm_state = PMSG_RESUME;
1684 host->suspend = 0;
1685 host->core_clkon = 0;
1686 host->card_clkon = 0;
1687 host->core_power = 0;
1688 host->power_mode = MMC_POWER_OFF;
1689 // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
1690 host->timeout_ns = 0;
1691 host->timeout_clks = DEFAULT_DTOC * 65536;
1692
1693 host->mrq = NULL;
1694 //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
1695
1696 mmc_dev(mmc)->dma_mask = NULL;
1697
1698 /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
1699 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1700 MAX_GPD_NUM * sizeof(struct gpd),
1701 &host->dma.gpd_addr, GFP_KERNEL);
1702 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1703 MAX_BD_NUM * sizeof(struct bd),
1704 &host->dma.bd_addr, GFP_KERNEL);
1705 if (!host->dma.gpd || !host->dma.bd) {
1706 ret = -ENOMEM;
1707 goto release_mem;
1708 }
1709 msdc_init_gpd_bd(host, &host->dma);
1710
1711 INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
1712 spin_lock_init(&host->lock);
1713 msdc_init_hw(host);
1714
1715 /* TODO check weather flags 0 is correct, the mtk-sd driver uses
1716 * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags
1717 *
1718 * for flags 0 the trigger polarity is determined by the
1719 * device tree, but not the oneshot flag, but maybe it is also
1720 * not needed because the soc could be oneshot safe.
1721 */
1722 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,
1723 host);
1724 if (ret)
1725 goto release;
1726
1727 platform_set_drvdata(pdev, mmc);
1728
1729 ret = mmc_add_host(mmc);
1730 if (ret)
1731 goto release;
1732
1733 /* Config card detection pin and enable interrupts */
1734 if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
1735 msdc_enable_cd_irq(host, 1);
1736 } else {
1737 msdc_enable_cd_irq(host, 0);
1738 }
1739
1740 return 0;
1741
1742 release:
1743 platform_set_drvdata(pdev, NULL);
1744 msdc_deinit_hw(host);
1745 cancel_delayed_work_sync(&host->card_delaywork);
1746
1747 release_mem:
1748 if (host->dma.gpd)
1749 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
1750 host->dma.gpd, host->dma.gpd_addr);
1751 if (host->dma.bd)
1752 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
1753 host->dma.bd, host->dma.bd_addr);
1754 host_free:
1755 mmc_free_host(mmc);
1756
1757 return ret;
1758 }
1759
1760 /* 4 device share one driver, using "drvdata" to show difference */
1761 static int msdc_drv_remove(struct platform_device *pdev)
1762 {
1763 struct mmc_host *mmc;
1764 struct msdc_host *host;
1765
1766 mmc = platform_get_drvdata(pdev);
1767 BUG_ON(!mmc);
1768
1769 host = mmc_priv(mmc);
1770 BUG_ON(!host);
1771
1772 dev_err(mmc_dev(host->mmc), "%d -> removed !!!\n",
1773 host->id);
1774
1775 platform_set_drvdata(pdev, NULL);
1776 mmc_remove_host(host->mmc);
1777 msdc_deinit_hw(host);
1778
1779 cancel_delayed_work_sync(&host->card_delaywork);
1780
1781 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
1782 host->dma.gpd, host->dma.gpd_addr);
1783 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
1784 host->dma.bd, host->dma.bd_addr);
1785
1786 mmc_free_host(host->mmc);
1787
1788 return 0;
1789 }
1790
1791 /* Fix me: Power Flow */
1792 #ifdef CONFIG_PM
1793
1794 static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)
1795 {
1796 struct mmc_host *mmc = platform_get_drvdata(pdev);
1797
1798 if (mmc) {
1799 struct msdc_host *host = mmc_priv(mmc);
1800 msdc_pm(state, (void *)host);
1801 }
1802 }
1803
1804 static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
1805 {
1806 if (state.event == PM_EVENT_SUSPEND)
1807 msdc_drv_pm(pdev, state);
1808 return 0;
1809 }
1810
1811 static int msdc_drv_resume(struct platform_device *pdev)
1812 {
1813 struct pm_message state;
1814
1815 state.event = PM_EVENT_RESUME;
1816 msdc_drv_pm(pdev, state);
1817 return 0;
1818 }
1819 #endif
1820
1821 static const struct of_device_id mt7620_sdhci_match[] = {
1822 { .compatible = "ralink,mt7620-sdhci" },
1823 {},
1824 };
1825 MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
1826
1827 static struct platform_driver mt_msdc_driver = {
1828 .probe = msdc_drv_probe,
1829 .remove = msdc_drv_remove,
1830 #ifdef CONFIG_PM
1831 .suspend = msdc_drv_suspend,
1832 .resume = msdc_drv_resume,
1833 #endif
1834 .driver = {
1835 .name = DRV_NAME,
1836 .of_match_table = mt7620_sdhci_match,
1837 },
1838 };
1839
1840 /*--------------------------------------------------------------------------*/
1841 /* module init/exit */
1842 /*--------------------------------------------------------------------------*/
1843 static int __init mt_msdc_init(void)
1844 {
1845 int ret;
1846 u32 reg;
1847
1848 // Set the pins for sdxc to sdxc mode
1849 //FIXME: this should be done by pinctl and not by the sd driver
1850 reg = readl((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
1851 writel(reg, (void __iomem *)(RALINK_SYSCTL_BASE + 0x60));
1852
1853 ret = platform_driver_register(&mt_msdc_driver);
1854 if (ret) {
1855 pr_err("%s: Can't register driver", DRV_NAME);
1856 return ret;
1857 }
1858
1859 #if defined(MT6575_SD_DEBUG)
1860 msdc_debug_proc_init();
1861 #endif
1862 return 0;
1863 }
1864
1865 static void __exit mt_msdc_exit(void)
1866 {
1867 platform_driver_unregister(&mt_msdc_driver);
1868 }
1869
1870 module_init(mt_msdc_init);
1871 module_exit(mt_msdc_exit);
1872 MODULE_LICENSE("GPL");
1873 MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
1874 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
Linux with added FPC-III support