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compat: return -EFAULT on error in waitid()
[linux/fpc-iii.git] / drivers / char / agp / intel-gtt.c
blobdbd901e94ea637bcfad26cc21de52c89e10862e9
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
25 #include <asm/smp.h>
26 #include "agp.h"
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43 unsigned int gen : 8;
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
50 int (*setup)(void);
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63 struct intel_gtt base;
64 const struct intel_gtt_driver *driver;
65 struct pci_dev *pcidev; /* device one */
66 struct pci_dev *bridge_dev;
67 u8 __iomem *registers;
68 phys_addr_t gtt_bus_addr;
69 u32 PGETBL_save;
70 u32 __iomem *gtt; /* I915G */
71 bool clear_fake_agp; /* on first access via agp, fill with scratch */
72 int num_dcache_entries;
73 void __iomem *i9xx_flush_page;
74 char *i81x_gtt_table;
75 struct resource ifp_resource;
76 int resource_valid;
77 struct page *scratch_page;
78 int refcount;
79 } intel_private;
80
81 #define INTEL_GTT_GEN intel_private.driver->gen
82 #define IS_G33 intel_private.driver->is_g33
83 #define IS_PINEVIEW intel_private.driver->is_pineview
84 #define IS_IRONLAKE intel_private.driver->is_ironlake
85 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
86
87 static int intel_gtt_map_memory(struct page **pages,
88 unsigned int num_entries,
89 struct sg_table *st)
90 {
91 struct scatterlist *sg;
92 int i;
93
94 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
95
96 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
97 goto err;
98
99 for_each_sg(st->sgl, sg, num_entries, i)
100 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
101
102 if (!pci_map_sg(intel_private.pcidev,
103 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
104 goto err;
105
106 return 0;
107
108 err:
109 sg_free_table(st);
110 return -ENOMEM;
111 }
112
113 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
114 {
115 struct sg_table st;
116 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
117
118 pci_unmap_sg(intel_private.pcidev, sg_list,
119 num_sg, PCI_DMA_BIDIRECTIONAL);
120
121 st.sgl = sg_list;
122 st.orig_nents = st.nents = num_sg;
123
124 sg_free_table(&st);
125 }
126
127 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
128 {
129 return;
130 }
131
132 /* Exists to support ARGB cursors */
133 static struct page *i8xx_alloc_pages(void)
134 {
135 struct page *page;
136
137 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
138 if (page == NULL)
139 return NULL;
140
141 if (set_pages_uc(page, 4) < 0) {
142 set_pages_wb(page, 4);
143 __free_pages(page, 2);
144 return NULL;
145 }
146 get_page(page);
147 atomic_inc(&agp_bridge->current_memory_agp);
148 return page;
149 }
150
151 static void i8xx_destroy_pages(struct page *page)
152 {
153 if (page == NULL)
154 return;
155
156 set_pages_wb(page, 4);
157 put_page(page);
158 __free_pages(page, 2);
159 atomic_dec(&agp_bridge->current_memory_agp);
160 }
161
162 #define I810_GTT_ORDER 4
163 static int i810_setup(void)
164 {
165 u32 reg_addr;
166 char *gtt_table;
167
168 /* i81x does not preallocate the gtt. It's always 64kb in size. */
169 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
170 if (gtt_table == NULL)
171 return -ENOMEM;
172 intel_private.i81x_gtt_table = gtt_table;
173
174 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
175 reg_addr &= 0xfff80000;
176
177 intel_private.registers = ioremap(reg_addr, KB(64));
178 if (!intel_private.registers)
179 return -ENOMEM;
180
181 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
182 intel_private.registers+I810_PGETBL_CTL);
183
184 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
185
186 if ((readl(intel_private.registers+I810_DRAM_CTL)
187 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
188 dev_info(&intel_private.pcidev->dev,
189 "detected 4MB dedicated video ram\n");
190 intel_private.num_dcache_entries = 1024;
191 }
192
193 return 0;
194 }
195
196 static void i810_cleanup(void)
197 {
198 writel(0, intel_private.registers+I810_PGETBL_CTL);
199 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
200 }
201
202 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
203 int type)
204 {
205 int i;
206
207 if ((pg_start + mem->page_count)
208 > intel_private.num_dcache_entries)
209 return -EINVAL;
210
211 if (!mem->is_flushed)
212 global_cache_flush();
213
214 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
215 dma_addr_t addr = i << PAGE_SHIFT;
216 intel_private.driver->write_entry(addr,
217 i, type);
218 }
219 readl(intel_private.gtt+i-1);
220
221 return 0;
222 }
223
224 /*
225 * The i810/i830 requires a physical address to program its mouse
226 * pointer into hardware.
227 * However the Xserver still writes to it through the agp aperture.
228 */
229 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
230 {
231 struct agp_memory *new;
232 struct page *page;
233
234 switch (pg_count) {
235 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
236 break;
237 case 4:
238 /* kludge to get 4 physical pages for ARGB cursor */
239 page = i8xx_alloc_pages();
240 break;
241 default:
242 return NULL;
243 }
244
245 if (page == NULL)
246 return NULL;
247
248 new = agp_create_memory(pg_count);
249 if (new == NULL)
250 return NULL;
251
252 new->pages[0] = page;
253 if (pg_count == 4) {
254 /* kludge to get 4 physical pages for ARGB cursor */
255 new->pages[1] = new->pages[0] + 1;
256 new->pages[2] = new->pages[1] + 1;
257 new->pages[3] = new->pages[2] + 1;
258 }
259 new->page_count = pg_count;
260 new->num_scratch_pages = pg_count;
261 new->type = AGP_PHYS_MEMORY;
262 new->physical = page_to_phys(new->pages[0]);
263 return new;
264 }
265
266 static void intel_i810_free_by_type(struct agp_memory *curr)
267 {
268 agp_free_key(curr->key);
269 if (curr->type == AGP_PHYS_MEMORY) {
270 if (curr->page_count == 4)
271 i8xx_destroy_pages(curr->pages[0]);
272 else {
273 agp_bridge->driver->agp_destroy_page(curr->pages[0],
274 AGP_PAGE_DESTROY_UNMAP);
275 agp_bridge->driver->agp_destroy_page(curr->pages[0],
276 AGP_PAGE_DESTROY_FREE);
277 }
278 agp_free_page_array(curr);
279 }
280 kfree(curr);
281 }
282
283 static int intel_gtt_setup_scratch_page(void)
284 {
285 struct page *page;
286 dma_addr_t dma_addr;
287
288 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
289 if (page == NULL)
290 return -ENOMEM;
291 get_page(page);
292 set_pages_uc(page, 1);
293
294 if (intel_private.base.needs_dmar) {
295 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
296 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
297 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
298 return -EINVAL;
299
300 intel_private.base.scratch_page_dma = dma_addr;
301 } else
302 intel_private.base.scratch_page_dma = page_to_phys(page);
303
304 intel_private.scratch_page = page;
305
306 return 0;
307 }
308
309 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
310 unsigned int flags)
311 {
312 u32 pte_flags = I810_PTE_VALID;
313
314 switch (flags) {
315 case AGP_DCACHE_MEMORY:
316 pte_flags |= I810_PTE_LOCAL;
317 break;
318 case AGP_USER_CACHED_MEMORY:
319 pte_flags |= I830_PTE_SYSTEM_CACHED;
320 break;
321 }
322
323 writel(addr | pte_flags, intel_private.gtt + entry);
324 }
325
326 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
327 {32, 8192, 3},
328 {64, 16384, 4},
329 {128, 32768, 5},
330 {256, 65536, 6},
331 {512, 131072, 7},
332 };
333
334 static unsigned int intel_gtt_stolen_size(void)
335 {
336 u16 gmch_ctrl;
337 u8 rdct;
338 int local = 0;
339 static const int ddt[4] = { 0, 16, 32, 64 };
340 unsigned int stolen_size = 0;
341
342 if (INTEL_GTT_GEN == 1)
343 return 0; /* no stolen mem on i81x */
344
345 pci_read_config_word(intel_private.bridge_dev,
346 I830_GMCH_CTRL, &gmch_ctrl);
347
348 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
349 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
350 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
351 case I830_GMCH_GMS_STOLEN_512:
352 stolen_size = KB(512);
353 break;
354 case I830_GMCH_GMS_STOLEN_1024:
355 stolen_size = MB(1);
356 break;
357 case I830_GMCH_GMS_STOLEN_8192:
358 stolen_size = MB(8);
359 break;
360 case I830_GMCH_GMS_LOCAL:
361 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
362 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
363 MB(ddt[I830_RDRAM_DDT(rdct)]);
364 local = 1;
365 break;
366 default:
367 stolen_size = 0;
368 break;
369 }
370 } else {
371 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
372 case I855_GMCH_GMS_STOLEN_1M:
373 stolen_size = MB(1);
374 break;
375 case I855_GMCH_GMS_STOLEN_4M:
376 stolen_size = MB(4);
377 break;
378 case I855_GMCH_GMS_STOLEN_8M:
379 stolen_size = MB(8);
380 break;
381 case I855_GMCH_GMS_STOLEN_16M:
382 stolen_size = MB(16);
383 break;
384 case I855_GMCH_GMS_STOLEN_32M:
385 stolen_size = MB(32);
386 break;
387 case I915_GMCH_GMS_STOLEN_48M:
388 stolen_size = MB(48);
389 break;
390 case I915_GMCH_GMS_STOLEN_64M:
391 stolen_size = MB(64);
392 break;
393 case G33_GMCH_GMS_STOLEN_128M:
394 stolen_size = MB(128);
395 break;
396 case G33_GMCH_GMS_STOLEN_256M:
397 stolen_size = MB(256);
398 break;
399 case INTEL_GMCH_GMS_STOLEN_96M:
400 stolen_size = MB(96);
401 break;
402 case INTEL_GMCH_GMS_STOLEN_160M:
403 stolen_size = MB(160);
404 break;
405 case INTEL_GMCH_GMS_STOLEN_224M:
406 stolen_size = MB(224);
407 break;
408 case INTEL_GMCH_GMS_STOLEN_352M:
409 stolen_size = MB(352);
410 break;
411 default:
412 stolen_size = 0;
413 break;
414 }
415 }
416
417 if (stolen_size > 0) {
418 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
419 stolen_size / KB(1), local ? "local" : "stolen");
420 } else {
421 dev_info(&intel_private.bridge_dev->dev,
422 "no pre-allocated video memory detected\n");
423 stolen_size = 0;
424 }
425
426 return stolen_size;
427 }
428
429 static void i965_adjust_pgetbl_size(unsigned int size_flag)
430 {
431 u32 pgetbl_ctl, pgetbl_ctl2;
432
433 /* ensure that ppgtt is disabled */
434 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
435 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
436 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
437
438 /* write the new ggtt size */
439 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
440 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
441 pgetbl_ctl |= size_flag;
442 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
443 }
444
445 static unsigned int i965_gtt_total_entries(void)
446 {
447 int size;
448 u32 pgetbl_ctl;
449 u16 gmch_ctl;
450
451 pci_read_config_word(intel_private.bridge_dev,
452 I830_GMCH_CTRL, &gmch_ctl);
453
454 if (INTEL_GTT_GEN == 5) {
455 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
456 case G4x_GMCH_SIZE_1M:
457 case G4x_GMCH_SIZE_VT_1M:
458 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
459 break;
460 case G4x_GMCH_SIZE_VT_1_5M:
461 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
462 break;
463 case G4x_GMCH_SIZE_2M:
464 case G4x_GMCH_SIZE_VT_2M:
465 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
466 break;
467 }
468 }
469
470 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
471
472 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
473 case I965_PGETBL_SIZE_128KB:
474 size = KB(128);
475 break;
476 case I965_PGETBL_SIZE_256KB:
477 size = KB(256);
478 break;
479 case I965_PGETBL_SIZE_512KB:
480 size = KB(512);
481 break;
482 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
483 case I965_PGETBL_SIZE_1MB:
484 size = KB(1024);
485 break;
486 case I965_PGETBL_SIZE_2MB:
487 size = KB(2048);
488 break;
489 case I965_PGETBL_SIZE_1_5MB:
490 size = KB(1024 + 512);
491 break;
492 default:
493 dev_info(&intel_private.pcidev->dev,
494 "unknown page table size, assuming 512KB\n");
495 size = KB(512);
496 }
497
498 return size/4;
499 }
500
501 static unsigned int intel_gtt_total_entries(void)
502 {
503 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
504 return i965_gtt_total_entries();
505 else {
506 /* On previous hardware, the GTT size was just what was
507 * required to map the aperture.
508 */
509 return intel_private.base.gtt_mappable_entries;
510 }
511 }
512
513 static unsigned int intel_gtt_mappable_entries(void)
514 {
515 unsigned int aperture_size;
516
517 if (INTEL_GTT_GEN == 1) {
518 u32 smram_miscc;
519
520 pci_read_config_dword(intel_private.bridge_dev,
521 I810_SMRAM_MISCC, &smram_miscc);
522
523 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
524 == I810_GFX_MEM_WIN_32M)
525 aperture_size = MB(32);
526 else
527 aperture_size = MB(64);
528 } else if (INTEL_GTT_GEN == 2) {
529 u16 gmch_ctrl;
530
531 pci_read_config_word(intel_private.bridge_dev,
532 I830_GMCH_CTRL, &gmch_ctrl);
533
534 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
535 aperture_size = MB(64);
536 else
537 aperture_size = MB(128);
538 } else {
539 /* 9xx supports large sizes, just look at the length */
540 aperture_size = pci_resource_len(intel_private.pcidev, 2);
541 }
542
543 return aperture_size >> PAGE_SHIFT;
544 }
545
546 static void intel_gtt_teardown_scratch_page(void)
547 {
548 set_pages_wb(intel_private.scratch_page, 1);
549 pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
550 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
551 put_page(intel_private.scratch_page);
552 __free_page(intel_private.scratch_page);
553 }
554
555 static void intel_gtt_cleanup(void)
556 {
557 intel_private.driver->cleanup();
558
559 iounmap(intel_private.gtt);
560 iounmap(intel_private.registers);
561
562 intel_gtt_teardown_scratch_page();
563 }
564
565 static int intel_gtt_init(void)
566 {
567 u32 gma_addr;
568 u32 gtt_map_size;
569 int ret;
570
571 ret = intel_private.driver->setup();
572 if (ret != 0)
573 return ret;
574
575 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
576 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
577
578 /* save the PGETBL reg for resume */
579 intel_private.PGETBL_save =
580 readl(intel_private.registers+I810_PGETBL_CTL)
581 & ~I810_PGETBL_ENABLED;
582 /* we only ever restore the register when enabling the PGTBL... */
583 if (HAS_PGTBL_EN)
584 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
585
586 dev_info(&intel_private.bridge_dev->dev,
587 "detected gtt size: %dK total, %dK mappable\n",
588 intel_private.base.gtt_total_entries * 4,
589 intel_private.base.gtt_mappable_entries * 4);
590
591 gtt_map_size = intel_private.base.gtt_total_entries * 4;
592
593 intel_private.gtt = NULL;
594 if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
595 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
596 gtt_map_size);
597 if (intel_private.gtt == NULL)
598 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
599 gtt_map_size);
600 if (intel_private.gtt == NULL) {
601 intel_private.driver->cleanup();
602 iounmap(intel_private.registers);
603 return -ENOMEM;
604 }
605 intel_private.base.gtt = intel_private.gtt;
606
607 global_cache_flush(); /* FIXME: ? */
608
609 intel_private.base.stolen_size = intel_gtt_stolen_size();
610
611 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
612
613 ret = intel_gtt_setup_scratch_page();
614 if (ret != 0) {
615 intel_gtt_cleanup();
616 return ret;
617 }
618
619 if (INTEL_GTT_GEN <= 2)
620 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
621 &gma_addr);
622 else
623 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
624 &gma_addr);
625
626 intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
627
628 return 0;
629 }
630
631 static int intel_fake_agp_fetch_size(void)
632 {
633 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
634 unsigned int aper_size;
635 int i;
636
637 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
638 / MB(1);
639
640 for (i = 0; i < num_sizes; i++) {
641 if (aper_size == intel_fake_agp_sizes[i].size) {
642 agp_bridge->current_size =
643 (void *) (intel_fake_agp_sizes + i);
644 return aper_size;
645 }
646 }
647
648 return 0;
649 }
650
651 static void i830_cleanup(void)
652 {
653 }
654
655 /* The chipset_flush interface needs to get data that has already been
656 * flushed out of the CPU all the way out to main memory, because the GPU
657 * doesn't snoop those buffers.
658 *
659 * The 8xx series doesn't have the same lovely interface for flushing the
660 * chipset write buffers that the later chips do. According to the 865
661 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
662 * that buffer out, we just fill 1KB and clflush it out, on the assumption
663 * that it'll push whatever was in there out. It appears to work.
664 */
665 static void i830_chipset_flush(void)
666 {
667 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
668
669 /* Forcibly evict everything from the CPU write buffers.
670 * clflush appears to be insufficient.
671 */
672 wbinvd_on_all_cpus();
673
674 /* Now we've only seen documents for this magic bit on 855GM,
675 * we hope it exists for the other gen2 chipsets...
676 *
677 * Also works as advertised on my 845G.
678 */
679 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
680 intel_private.registers+I830_HIC);
681
682 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
683 if (time_after(jiffies, timeout))
684 break;
685
686 udelay(50);
687 }
688 }
689
690 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
691 unsigned int flags)
692 {
693 u32 pte_flags = I810_PTE_VALID;
694
695 if (flags == AGP_USER_CACHED_MEMORY)
696 pte_flags |= I830_PTE_SYSTEM_CACHED;
697
698 writel(addr | pte_flags, intel_private.gtt + entry);
699 }
700
701 bool intel_enable_gtt(void)
702 {
703 u8 __iomem *reg;
704
705 if (INTEL_GTT_GEN == 2) {
706 u16 gmch_ctrl;
707
708 pci_read_config_word(intel_private.bridge_dev,
709 I830_GMCH_CTRL, &gmch_ctrl);
710 gmch_ctrl |= I830_GMCH_ENABLED;
711 pci_write_config_word(intel_private.bridge_dev,
712 I830_GMCH_CTRL, gmch_ctrl);
713
714 pci_read_config_word(intel_private.bridge_dev,
715 I830_GMCH_CTRL, &gmch_ctrl);
716 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
717 dev_err(&intel_private.pcidev->dev,
718 "failed to enable the GTT: GMCH_CTRL=%x\n",
719 gmch_ctrl);
720 return false;
721 }
722 }
723
724 /* On the resume path we may be adjusting the PGTBL value, so
725 * be paranoid and flush all chipset write buffers...
726 */
727 if (INTEL_GTT_GEN >= 3)
728 writel(0, intel_private.registers+GFX_FLSH_CNTL);
729
730 reg = intel_private.registers+I810_PGETBL_CTL;
731 writel(intel_private.PGETBL_save, reg);
732 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
733 dev_err(&intel_private.pcidev->dev,
734 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
735 readl(reg), intel_private.PGETBL_save);
736 return false;
737 }
738
739 if (INTEL_GTT_GEN >= 3)
740 writel(0, intel_private.registers+GFX_FLSH_CNTL);
741
742 return true;
743 }
744 EXPORT_SYMBOL(intel_enable_gtt);
745
746 static int i830_setup(void)
747 {
748 u32 reg_addr;
749
750 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
751 reg_addr &= 0xfff80000;
752
753 intel_private.registers = ioremap(reg_addr, KB(64));
754 if (!intel_private.registers)
755 return -ENOMEM;
756
757 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
758
759 return 0;
760 }
761
762 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
763 {
764 agp_bridge->gatt_table_real = NULL;
765 agp_bridge->gatt_table = NULL;
766 agp_bridge->gatt_bus_addr = 0;
767
768 return 0;
769 }
770
771 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
772 {
773 return 0;
774 }
775
776 static int intel_fake_agp_configure(void)
777 {
778 if (!intel_enable_gtt())
779 return -EIO;
780
781 intel_private.clear_fake_agp = true;
782 agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
783
784 return 0;
785 }
786
787 static bool i830_check_flags(unsigned int flags)
788 {
789 switch (flags) {
790 case 0:
791 case AGP_PHYS_MEMORY:
792 case AGP_USER_CACHED_MEMORY:
793 case AGP_USER_MEMORY:
794 return true;
795 }
796
797 return false;
798 }
799
800 void intel_gtt_insert_sg_entries(struct sg_table *st,
801 unsigned int pg_start,
802 unsigned int flags)
803 {
804 struct scatterlist *sg;
805 unsigned int len, m;
806 int i, j;
807
808 j = pg_start;
809
810 /* sg may merge pages, but we have to separate
811 * per-page addr for GTT */
812 for_each_sg(st->sgl, sg, st->nents, i) {
813 len = sg_dma_len(sg) >> PAGE_SHIFT;
814 for (m = 0; m < len; m++) {
815 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
816 intel_private.driver->write_entry(addr, j, flags);
817 j++;
818 }
819 }
820 readl(intel_private.gtt+j-1);
821 }
822 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
823
824 static void intel_gtt_insert_pages(unsigned int first_entry,
825 unsigned int num_entries,
826 struct page **pages,
827 unsigned int flags)
828 {
829 int i, j;
830
831 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
832 dma_addr_t addr = page_to_phys(pages[i]);
833 intel_private.driver->write_entry(addr,
834 j, flags);
835 }
836 readl(intel_private.gtt+j-1);
837 }
838
839 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
840 off_t pg_start, int type)
841 {
842 int ret = -EINVAL;
843
844 if (intel_private.base.do_idle_maps)
845 return -ENODEV;
846
847 if (intel_private.clear_fake_agp) {
848 int start = intel_private.base.stolen_size / PAGE_SIZE;
849 int end = intel_private.base.gtt_mappable_entries;
850 intel_gtt_clear_range(start, end - start);
851 intel_private.clear_fake_agp = false;
852 }
853
854 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
855 return i810_insert_dcache_entries(mem, pg_start, type);
856
857 if (mem->page_count == 0)
858 goto out;
859
860 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
861 goto out_err;
862
863 if (type != mem->type)
864 goto out_err;
865
866 if (!intel_private.driver->check_flags(type))
867 goto out_err;
868
869 if (!mem->is_flushed)
870 global_cache_flush();
871
872 if (intel_private.base.needs_dmar) {
873 struct sg_table st;
874
875 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
876 if (ret != 0)
877 return ret;
878
879 intel_gtt_insert_sg_entries(&st, pg_start, type);
880 mem->sg_list = st.sgl;
881 mem->num_sg = st.nents;
882 } else
883 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
884 type);
885
886 out:
887 ret = 0;
888 out_err:
889 mem->is_flushed = true;
890 return ret;
891 }
892
893 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
894 {
895 unsigned int i;
896
897 for (i = first_entry; i < (first_entry + num_entries); i++) {
898 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
899 i, 0);
900 }
901 readl(intel_private.gtt+i-1);
902 }
903 EXPORT_SYMBOL(intel_gtt_clear_range);
904
905 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
906 off_t pg_start, int type)
907 {
908 if (mem->page_count == 0)
909 return 0;
910
911 if (intel_private.base.do_idle_maps)
912 return -ENODEV;
913
914 intel_gtt_clear_range(pg_start, mem->page_count);
915
916 if (intel_private.base.needs_dmar) {
917 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
918 mem->sg_list = NULL;
919 mem->num_sg = 0;
920 }
921
922 return 0;
923 }
924
925 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
926 int type)
927 {
928 struct agp_memory *new;
929
930 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
931 if (pg_count != intel_private.num_dcache_entries)
932 return NULL;
933
934 new = agp_create_memory(1);
935 if (new == NULL)
936 return NULL;
937
938 new->type = AGP_DCACHE_MEMORY;
939 new->page_count = pg_count;
940 new->num_scratch_pages = 0;
941 agp_free_page_array(new);
942 return new;
943 }
944 if (type == AGP_PHYS_MEMORY)
945 return alloc_agpphysmem_i8xx(pg_count, type);
946 /* always return NULL for other allocation types for now */
947 return NULL;
948 }
949
950 static int intel_alloc_chipset_flush_resource(void)
951 {
952 int ret;
953 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
954 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
955 pcibios_align_resource, intel_private.bridge_dev);
956
957 return ret;
958 }
959
960 static void intel_i915_setup_chipset_flush(void)
961 {
962 int ret;
963 u32 temp;
964
965 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
966 if (!(temp & 0x1)) {
967 intel_alloc_chipset_flush_resource();
968 intel_private.resource_valid = 1;
969 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
970 } else {
971 temp &= ~1;
972
973 intel_private.resource_valid = 1;
974 intel_private.ifp_resource.start = temp;
975 intel_private.ifp_resource.end = temp + PAGE_SIZE;
976 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
977 /* some BIOSes reserve this area in a pnp some don't */
978 if (ret)
979 intel_private.resource_valid = 0;
980 }
981 }
982
983 static void intel_i965_g33_setup_chipset_flush(void)
984 {
985 u32 temp_hi, temp_lo;
986 int ret;
987
988 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
989 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
990
991 if (!(temp_lo & 0x1)) {
992
993 intel_alloc_chipset_flush_resource();
994
995 intel_private.resource_valid = 1;
996 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
997 upper_32_bits(intel_private.ifp_resource.start));
998 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
999 } else {
1000 u64 l64;
1001
1002 temp_lo &= ~0x1;
1003 l64 = ((u64)temp_hi << 32) | temp_lo;
1004
1005 intel_private.resource_valid = 1;
1006 intel_private.ifp_resource.start = l64;
1007 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1008 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1009 /* some BIOSes reserve this area in a pnp some don't */
1010 if (ret)
1011 intel_private.resource_valid = 0;
1012 }
1013 }
1014
1015 static void intel_i9xx_setup_flush(void)
1016 {
1017 /* return if already configured */
1018 if (intel_private.ifp_resource.start)
1019 return;
1020
1021 if (INTEL_GTT_GEN == 6)
1022 return;
1023
1024 /* setup a resource for this object */
1025 intel_private.ifp_resource.name = "Intel Flush Page";
1026 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1027
1028 /* Setup chipset flush for 915 */
1029 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1030 intel_i965_g33_setup_chipset_flush();
1031 } else {
1032 intel_i915_setup_chipset_flush();
1033 }
1034
1035 if (intel_private.ifp_resource.start)
1036 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1037 if (!intel_private.i9xx_flush_page)
1038 dev_err(&intel_private.pcidev->dev,
1039 "can't ioremap flush page - no chipset flushing\n");
1040 }
1041
1042 static void i9xx_cleanup(void)
1043 {
1044 if (intel_private.i9xx_flush_page)
1045 iounmap(intel_private.i9xx_flush_page);
1046 if (intel_private.resource_valid)
1047 release_resource(&intel_private.ifp_resource);
1048 intel_private.ifp_resource.start = 0;
1049 intel_private.resource_valid = 0;
1050 }
1051
1052 static void i9xx_chipset_flush(void)
1053 {
1054 if (intel_private.i9xx_flush_page)
1055 writel(1, intel_private.i9xx_flush_page);
1056 }
1057
1058 static void i965_write_entry(dma_addr_t addr,
1059 unsigned int entry,
1060 unsigned int flags)
1061 {
1062 u32 pte_flags;
1063
1064 pte_flags = I810_PTE_VALID;
1065 if (flags == AGP_USER_CACHED_MEMORY)
1066 pte_flags |= I830_PTE_SYSTEM_CACHED;
1067
1068 /* Shift high bits down */
1069 addr |= (addr >> 28) & 0xf0;
1070 writel(addr | pte_flags, intel_private.gtt + entry);
1071 }
1072
1073 /* Certain Gen5 chipsets require require idling the GPU before
1074 * unmapping anything from the GTT when VT-d is enabled.
1075 */
1076 static inline int needs_idle_maps(void)
1077 {
1078 #ifdef CONFIG_INTEL_IOMMU
1079 const unsigned short gpu_devid = intel_private.pcidev->device;
1080
1081 /* Query intel_iommu to see if we need the workaround. Presumably that
1082 * was loaded first.
1083 */
1084 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1085 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1086 intel_iommu_gfx_mapped)
1087 return 1;
1088 #endif
1089 return 0;
1090 }
1091
1092 static int i9xx_setup(void)
1093 {
1094 u32 reg_addr, gtt_addr;
1095 int size = KB(512);
1096
1097 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1098
1099 reg_addr &= 0xfff80000;
1100
1101 intel_private.registers = ioremap(reg_addr, size);
1102 if (!intel_private.registers)
1103 return -ENOMEM;
1104
1105 switch (INTEL_GTT_GEN) {
1106 case 3:
1107 pci_read_config_dword(intel_private.pcidev,
1108 I915_PTEADDR, &gtt_addr);
1109 intel_private.gtt_bus_addr = gtt_addr;
1110 break;
1111 case 5:
1112 intel_private.gtt_bus_addr = reg_addr + MB(2);
1113 break;
1114 default:
1115 intel_private.gtt_bus_addr = reg_addr + KB(512);
1116 break;
1117 }
1118
1119 if (needs_idle_maps())
1120 intel_private.base.do_idle_maps = 1;
1121
1122 intel_i9xx_setup_flush();
1123
1124 return 0;
1125 }
1126
1127 static const struct agp_bridge_driver intel_fake_agp_driver = {
1128 .owner = THIS_MODULE,
1129 .size_type = FIXED_APER_SIZE,
1130 .aperture_sizes = intel_fake_agp_sizes,
1131 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1132 .configure = intel_fake_agp_configure,
1133 .fetch_size = intel_fake_agp_fetch_size,
1134 .cleanup = intel_gtt_cleanup,
1135 .agp_enable = intel_fake_agp_enable,
1136 .cache_flush = global_cache_flush,
1137 .create_gatt_table = intel_fake_agp_create_gatt_table,
1138 .free_gatt_table = intel_fake_agp_free_gatt_table,
1139 .insert_memory = intel_fake_agp_insert_entries,
1140 .remove_memory = intel_fake_agp_remove_entries,
1141 .alloc_by_type = intel_fake_agp_alloc_by_type,
1142 .free_by_type = intel_i810_free_by_type,
1143 .agp_alloc_page = agp_generic_alloc_page,
1144 .agp_alloc_pages = agp_generic_alloc_pages,
1145 .agp_destroy_page = agp_generic_destroy_page,
1146 .agp_destroy_pages = agp_generic_destroy_pages,
1147 };
1148
1149 static const struct intel_gtt_driver i81x_gtt_driver = {
1150 .gen = 1,
1151 .has_pgtbl_enable = 1,
1152 .dma_mask_size = 32,
1153 .setup = i810_setup,
1154 .cleanup = i810_cleanup,
1155 .check_flags = i830_check_flags,
1156 .write_entry = i810_write_entry,
1157 };
1158 static const struct intel_gtt_driver i8xx_gtt_driver = {
1159 .gen = 2,
1160 .has_pgtbl_enable = 1,
1161 .setup = i830_setup,
1162 .cleanup = i830_cleanup,
1163 .write_entry = i830_write_entry,
1164 .dma_mask_size = 32,
1165 .check_flags = i830_check_flags,
1166 .chipset_flush = i830_chipset_flush,
1167 };
1168 static const struct intel_gtt_driver i915_gtt_driver = {
1169 .gen = 3,
1170 .has_pgtbl_enable = 1,
1171 .setup = i9xx_setup,
1172 .cleanup = i9xx_cleanup,
1173 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1174 .write_entry = i830_write_entry,
1175 .dma_mask_size = 32,
1176 .check_flags = i830_check_flags,
1177 .chipset_flush = i9xx_chipset_flush,
1178 };
1179 static const struct intel_gtt_driver g33_gtt_driver = {
1180 .gen = 3,
1181 .is_g33 = 1,
1182 .setup = i9xx_setup,
1183 .cleanup = i9xx_cleanup,
1184 .write_entry = i965_write_entry,
1185 .dma_mask_size = 36,
1186 .check_flags = i830_check_flags,
1187 .chipset_flush = i9xx_chipset_flush,
1188 };
1189 static const struct intel_gtt_driver pineview_gtt_driver = {
1190 .gen = 3,
1191 .is_pineview = 1, .is_g33 = 1,
1192 .setup = i9xx_setup,
1193 .cleanup = i9xx_cleanup,
1194 .write_entry = i965_write_entry,
1195 .dma_mask_size = 36,
1196 .check_flags = i830_check_flags,
1197 .chipset_flush = i9xx_chipset_flush,
1198 };
1199 static const struct intel_gtt_driver i965_gtt_driver = {
1200 .gen = 4,
1201 .has_pgtbl_enable = 1,
1202 .setup = i9xx_setup,
1203 .cleanup = i9xx_cleanup,
1204 .write_entry = i965_write_entry,
1205 .dma_mask_size = 36,
1206 .check_flags = i830_check_flags,
1207 .chipset_flush = i9xx_chipset_flush,
1208 };
1209 static const struct intel_gtt_driver g4x_gtt_driver = {
1210 .gen = 5,
1211 .setup = i9xx_setup,
1212 .cleanup = i9xx_cleanup,
1213 .write_entry = i965_write_entry,
1214 .dma_mask_size = 36,
1215 .check_flags = i830_check_flags,
1216 .chipset_flush = i9xx_chipset_flush,
1217 };
1218 static const struct intel_gtt_driver ironlake_gtt_driver = {
1219 .gen = 5,
1220 .is_ironlake = 1,
1221 .setup = i9xx_setup,
1222 .cleanup = i9xx_cleanup,
1223 .write_entry = i965_write_entry,
1224 .dma_mask_size = 36,
1225 .check_flags = i830_check_flags,
1226 .chipset_flush = i9xx_chipset_flush,
1227 };
1228
1229 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1230 * driver and gmch_driver must be non-null, and find_gmch will determine
1231 * which one should be used if a gmch_chip_id is present.
1232 */
1233 static const struct intel_gtt_driver_description {
1234 unsigned int gmch_chip_id;
1235 char *name;
1236 const struct intel_gtt_driver *gtt_driver;
1237 } intel_gtt_chipsets[] = {
1238 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1239 &i81x_gtt_driver},
1240 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1241 &i81x_gtt_driver},
1242 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1243 &i81x_gtt_driver},
1244 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1245 &i81x_gtt_driver},
1246 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1247 &i8xx_gtt_driver},
1248 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1249 &i8xx_gtt_driver},
1250 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1251 &i8xx_gtt_driver},
1252 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1253 &i8xx_gtt_driver},
1254 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1255 &i8xx_gtt_driver},
1256 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1257 &i915_gtt_driver },
1258 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1259 &i915_gtt_driver },
1260 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1261 &i915_gtt_driver },
1262 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1263 &i915_gtt_driver },
1264 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1265 &i915_gtt_driver },
1266 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1267 &i915_gtt_driver },
1268 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1269 &i965_gtt_driver },
1270 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1271 &i965_gtt_driver },
1272 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1273 &i965_gtt_driver },
1274 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1275 &i965_gtt_driver },
1276 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1277 &i965_gtt_driver },
1278 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1279 &i965_gtt_driver },
1280 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1281 &g33_gtt_driver },
1282 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1283 &g33_gtt_driver },
1284 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1285 &g33_gtt_driver },
1286 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1287 &pineview_gtt_driver },
1288 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1289 &pineview_gtt_driver },
1290 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1291 &g4x_gtt_driver },
1292 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1293 &g4x_gtt_driver },
1294 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1295 &g4x_gtt_driver },
1296 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1297 &g4x_gtt_driver },
1298 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1299 &g4x_gtt_driver },
1300 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1301 &g4x_gtt_driver },
1302 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1303 &g4x_gtt_driver },
1304 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1305 "HD Graphics", &ironlake_gtt_driver },
1306 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1307 "HD Graphics", &ironlake_gtt_driver },
1308 { 0, NULL, NULL }
1309 };
1310
1311 static int find_gmch(u16 device)
1312 {
1313 struct pci_dev *gmch_device;
1314
1315 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1316 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1317 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1318 device, gmch_device);
1319 }
1320
1321 if (!gmch_device)
1322 return 0;
1323
1324 intel_private.pcidev = gmch_device;
1325 return 1;
1326 }
1327
1328 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1329 struct agp_bridge_data *bridge)
1330 {
1331 int i, mask;
1332
1333 /*
1334 * Can be called from the fake agp driver but also directly from
1335 * drm/i915.ko. Hence we need to check whether everything is set up
1336 * already.
1337 */
1338 if (intel_private.driver) {
1339 intel_private.refcount++;
1340 return 1;
1341 }
1342
1343 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1344 if (gpu_pdev) {
1345 if (gpu_pdev->device ==
1346 intel_gtt_chipsets[i].gmch_chip_id) {
1347 intel_private.pcidev = pci_dev_get(gpu_pdev);
1348 intel_private.driver =
1349 intel_gtt_chipsets[i].gtt_driver;
1350
1351 break;
1352 }
1353 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1354 intel_private.driver =
1355 intel_gtt_chipsets[i].gtt_driver;
1356 break;
1357 }
1358 }
1359
1360 if (!intel_private.driver)
1361 return 0;
1362
1363 intel_private.refcount++;
1364
1365 if (bridge) {
1366 bridge->driver = &intel_fake_agp_driver;
1367 bridge->dev_private_data = &intel_private;
1368 bridge->dev = bridge_pdev;
1369 }
1370
1371 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1372
1373 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1374
1375 mask = intel_private.driver->dma_mask_size;
1376 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1377 dev_err(&intel_private.pcidev->dev,
1378 "set gfx device dma mask %d-bit failed!\n", mask);
1379 else
1380 pci_set_consistent_dma_mask(intel_private.pcidev,
1381 DMA_BIT_MASK(mask));
1382
1383 if (intel_gtt_init() != 0) {
1384 intel_gmch_remove();
1385
1386 return 0;
1387 }
1388
1389 return 1;
1390 }
1391 EXPORT_SYMBOL(intel_gmch_probe);
1392
1393 struct intel_gtt *intel_gtt_get(void)
1394 {
1395 return &intel_private.base;
1396 }
1397 EXPORT_SYMBOL(intel_gtt_get);
1398
1399 void intel_gtt_chipset_flush(void)
1400 {
1401 if (intel_private.driver->chipset_flush)
1402 intel_private.driver->chipset_flush();
1403 }
1404 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1405
1406 void intel_gmch_remove(void)
1407 {
1408 if (--intel_private.refcount)
1409 return;
1410
1411 if (intel_private.pcidev)
1412 pci_dev_put(intel_private.pcidev);
1413 if (intel_private.bridge_dev)
1414 pci_dev_put(intel_private.bridge_dev);
1415 intel_private.driver = NULL;
1416 }
1417 EXPORT_SYMBOL(intel_gmch_remove);
1418
1419 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1420 MODULE_LICENSE("GPL and additional rights");
Linux with added FPC-III support