ARM: mmp: fix potential NULL dereference
[linux/fpc-iii.git] / arch / alpha / kernel / ptrace.c
blob54616f496aedb27629d298329a43ff8447113300
1 /* ptrace.c */
2 /* By Ross Biro 1/23/92 */
3 /* edited by Linus Torvalds */
4 /* mangled further by Bob Manson (manson@santafe.edu) */
5 /* more mutilation by David Mosberger (davidm@azstarnet.com) */
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/smp.h>
11 #include <linux/errno.h>
12 #include <linux/ptrace.h>
13 #include <linux/user.h>
14 #include <linux/security.h>
15 #include <linux/signal.h>
17 #include <asm/uaccess.h>
18 #include <asm/pgtable.h>
19 #include <asm/fpu.h>
21 #include "proto.h"
23 #define DEBUG DBG_MEM
24 #undef DEBUG
26 #ifdef DEBUG
27 enum {
28 DBG_MEM = (1<<0),
29 DBG_BPT = (1<<1),
30 DBG_MEM_ALL = (1<<2)
32 #define DBG(fac,args) {if ((fac) & DEBUG) printk args;}
33 #else
34 #define DBG(fac,args)
35 #endif
37 #define BREAKINST 0x00000080 /* call_pal bpt */
40 * does not yet catch signals sent when the child dies.
41 * in exit.c or in signal.c.
45 * Processes always block with the following stack-layout:
47 * +================================+ <---- task + 2*PAGE_SIZE
48 * | PALcode saved frame (ps, pc, | ^
49 * | gp, a0, a1, a2) | |
50 * +================================+ | struct pt_regs
51 * | | |
52 * | frame generated by SAVE_ALL | |
53 * | | v
54 * +================================+
55 * | | ^
56 * | frame saved by do_switch_stack | | struct switch_stack
57 * | | v
58 * +================================+
61 /*
62 * The following table maps a register index into the stack offset at
63 * which the register is saved. Register indices are 0-31 for integer
64 * regs, 32-63 for fp regs, and 64 for the pc. Notice that sp and
65 * zero have no stack-slot and need to be treated specially (see
66 * get_reg/put_reg below).
68 enum {
69 REG_R0 = 0, REG_F0 = 32, REG_FPCR = 63, REG_PC = 64
72 #define PT_REG(reg) \
73 (PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg))
75 #define SW_REG(reg) \
76 (PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
77 + offsetof(struct switch_stack, reg))
79 static int regoff[] = {
80 PT_REG( r0), PT_REG( r1), PT_REG( r2), PT_REG( r3),
81 PT_REG( r4), PT_REG( r5), PT_REG( r6), PT_REG( r7),
82 PT_REG( r8), SW_REG( r9), SW_REG( r10), SW_REG( r11),
83 SW_REG( r12), SW_REG( r13), SW_REG( r14), SW_REG( r15),
84 PT_REG( r16), PT_REG( r17), PT_REG( r18), PT_REG( r19),
85 PT_REG( r20), PT_REG( r21), PT_REG( r22), PT_REG( r23),
86 PT_REG( r24), PT_REG( r25), PT_REG( r26), PT_REG( r27),
87 PT_REG( r28), PT_REG( gp), -1, -1,
88 SW_REG(fp[ 0]), SW_REG(fp[ 1]), SW_REG(fp[ 2]), SW_REG(fp[ 3]),
89 SW_REG(fp[ 4]), SW_REG(fp[ 5]), SW_REG(fp[ 6]), SW_REG(fp[ 7]),
90 SW_REG(fp[ 8]), SW_REG(fp[ 9]), SW_REG(fp[10]), SW_REG(fp[11]),
91 SW_REG(fp[12]), SW_REG(fp[13]), SW_REG(fp[14]), SW_REG(fp[15]),
92 SW_REG(fp[16]), SW_REG(fp[17]), SW_REG(fp[18]), SW_REG(fp[19]),
93 SW_REG(fp[20]), SW_REG(fp[21]), SW_REG(fp[22]), SW_REG(fp[23]),
94 SW_REG(fp[24]), SW_REG(fp[25]), SW_REG(fp[26]), SW_REG(fp[27]),
95 SW_REG(fp[28]), SW_REG(fp[29]), SW_REG(fp[30]), SW_REG(fp[31]),
96 PT_REG( pc)
99 static unsigned long zero;
102 * Get address of register REGNO in task TASK.
104 static unsigned long *
105 get_reg_addr(struct task_struct * task, unsigned long regno)
107 unsigned long *addr;
109 if (regno == 30) {
110 addr = &task_thread_info(task)->pcb.usp;
111 } else if (regno == 65) {
112 addr = &task_thread_info(task)->pcb.unique;
113 } else if (regno == 31 || regno > 65) {
114 zero = 0;
115 addr = &zero;
116 } else {
117 addr = task_stack_page(task) + regoff[regno];
119 return addr;
123 * Get contents of register REGNO in task TASK.
125 static unsigned long
126 get_reg(struct task_struct * task, unsigned long regno)
128 /* Special hack for fpcr -- combine hardware and software bits. */
129 if (regno == 63) {
130 unsigned long fpcr = *get_reg_addr(task, regno);
131 unsigned long swcr
132 = task_thread_info(task)->ieee_state & IEEE_SW_MASK;
133 swcr = swcr_update_status(swcr, fpcr);
134 return fpcr | swcr;
136 return *get_reg_addr(task, regno);
140 * Write contents of register REGNO in task TASK.
142 static int
143 put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
145 if (regno == 63) {
146 task_thread_info(task)->ieee_state
147 = ((task_thread_info(task)->ieee_state & ~IEEE_SW_MASK)
148 | (data & IEEE_SW_MASK));
149 data = (data & FPCR_DYN_MASK) | ieee_swcr_to_fpcr(data);
151 *get_reg_addr(task, regno) = data;
152 return 0;
155 static inline int
156 read_int(struct task_struct *task, unsigned long addr, int * data)
158 int copied = access_process_vm(task, addr, data, sizeof(int), 0);
159 return (copied == sizeof(int)) ? 0 : -EIO;
162 static inline int
163 write_int(struct task_struct *task, unsigned long addr, int data)
165 int copied = access_process_vm(task, addr, &data, sizeof(int), 1);
166 return (copied == sizeof(int)) ? 0 : -EIO;
170 * Set breakpoint.
173 ptrace_set_bpt(struct task_struct * child)
175 int displ, i, res, reg_b, nsaved = 0;
176 unsigned int insn, op_code;
177 unsigned long pc;
179 pc = get_reg(child, REG_PC);
180 res = read_int(child, pc, (int *) &insn);
181 if (res < 0)
182 return res;
184 op_code = insn >> 26;
185 if (op_code >= 0x30) {
187 * It's a branch: instead of trying to figure out
188 * whether the branch will be taken or not, we'll put
189 * a breakpoint at either location. This is simpler,
190 * more reliable, and probably not a whole lot slower
191 * than the alternative approach of emulating the
192 * branch (emulation can be tricky for fp branches).
194 displ = ((s32)(insn << 11)) >> 9;
195 task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
196 if (displ) /* guard against unoptimized code */
197 task_thread_info(child)->bpt_addr[nsaved++]
198 = pc + 4 + displ;
199 DBG(DBG_BPT, ("execing branch\n"));
200 } else if (op_code == 0x1a) {
201 reg_b = (insn >> 16) & 0x1f;
202 task_thread_info(child)->bpt_addr[nsaved++] = get_reg(child, reg_b);
203 DBG(DBG_BPT, ("execing jump\n"));
204 } else {
205 task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
206 DBG(DBG_BPT, ("execing normal insn\n"));
209 /* install breakpoints: */
210 for (i = 0; i < nsaved; ++i) {
211 res = read_int(child, task_thread_info(child)->bpt_addr[i],
212 (int *) &insn);
213 if (res < 0)
214 return res;
215 task_thread_info(child)->bpt_insn[i] = insn;
216 DBG(DBG_BPT, (" -> next_pc=%lx\n",
217 task_thread_info(child)->bpt_addr[i]));
218 res = write_int(child, task_thread_info(child)->bpt_addr[i],
219 BREAKINST);
220 if (res < 0)
221 return res;
223 task_thread_info(child)->bpt_nsaved = nsaved;
224 return 0;
228 * Ensure no single-step breakpoint is pending. Returns non-zero
229 * value if child was being single-stepped.
232 ptrace_cancel_bpt(struct task_struct * child)
234 int i, nsaved = task_thread_info(child)->bpt_nsaved;
236 task_thread_info(child)->bpt_nsaved = 0;
238 if (nsaved > 2) {
239 printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
240 nsaved = 2;
243 for (i = 0; i < nsaved; ++i) {
244 write_int(child, task_thread_info(child)->bpt_addr[i],
245 task_thread_info(child)->bpt_insn[i]);
247 return (nsaved != 0);
250 void user_enable_single_step(struct task_struct *child)
252 /* Mark single stepping. */
253 task_thread_info(child)->bpt_nsaved = -1;
256 void user_disable_single_step(struct task_struct *child)
258 ptrace_cancel_bpt(child);
262 * Called by kernel/ptrace.c when detaching..
264 * Make sure the single step bit is not set.
266 void ptrace_disable(struct task_struct *child)
268 user_disable_single_step(child);
271 long arch_ptrace(struct task_struct *child, long request,
272 unsigned long addr, unsigned long data)
274 unsigned long tmp;
275 size_t copied;
276 long ret;
278 switch (request) {
279 /* When I and D space are separate, these will need to be fixed. */
280 case PTRACE_PEEKTEXT: /* read word at location addr. */
281 case PTRACE_PEEKDATA:
282 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
283 ret = -EIO;
284 if (copied != sizeof(tmp))
285 break;
287 force_successful_syscall_return();
288 ret = tmp;
289 break;
291 /* Read register number ADDR. */
292 case PTRACE_PEEKUSR:
293 force_successful_syscall_return();
294 ret = get_reg(child, addr);
295 DBG(DBG_MEM, ("peek $%lu->%#lx\n", addr, ret));
296 break;
298 /* When I and D space are separate, this will have to be fixed. */
299 case PTRACE_POKETEXT: /* write the word at location addr. */
300 case PTRACE_POKEDATA:
301 ret = generic_ptrace_pokedata(child, addr, data);
302 break;
304 case PTRACE_POKEUSR: /* write the specified register */
305 DBG(DBG_MEM, ("poke $%lu<-%#lx\n", addr, data));
306 ret = put_reg(child, addr, data);
307 break;
308 default:
309 ret = ptrace_request(child, request, addr, data);
310 break;
312 return ret;
315 asmlinkage void
316 syscall_trace(void)
318 if (!test_thread_flag(TIF_SYSCALL_TRACE))
319 return;
320 if (!(current->ptrace & PT_PTRACED))
321 return;
322 /* The 0x80 provides a way for the tracing parent to distinguish
323 between a syscall stop and SIGTRAP delivery */
324 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
325 ? 0x80 : 0));
328 * This isn't the same as continuing with a signal, but it will do
329 * for normal use. strace only continues with a signal if the
330 * stopping signal is not SIGTRAP. -brl
332 if (current->exit_code) {
333 send_sig(current->exit_code, current, 1);
334 current->exit_code = 0;