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ARM: mmp: fix potential NULL dereference
[linux/fpc-iii.git] / arch / mips / alchemy / devboards / db1200.c
blobbf2248474fa8da6c4516c0567803c781636cb385
1 /*
2 * DBAu1200/PBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2011 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/dma-mapping.h>
22 #include <linux/gpio.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/leds.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/platform_device.h>
34 #include <linux/serial_8250.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37 #include <linux/smc91x.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-au1x00/au1100_mmc.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1200fb.h>
42 #include <asm/mach-au1x00/au1550_spi.h>
43 #include <asm/mach-db1x00/bcsr.h>
44 #include <asm/mach-db1x00/db1200.h>
45
46 #include "platform.h"
47
48 static const char *board_type_str(void)
49 {
50 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
51 case BCSR_WHOAMI_PB1200_DDR1:
52 case BCSR_WHOAMI_PB1200_DDR2:
53 return "PB1200";
54 case BCSR_WHOAMI_DB1200:
55 return "DB1200";
56 default:
57 return "(unknown)";
58 }
59 }
60
61 const char *get_system_type(void)
62 {
63 return board_type_str();
64 }
65
66 static int __init detect_board(void)
67 {
68 int bid;
69
70 /* try the DB1200 first */
71 bcsr_init(DB1200_BCSR_PHYS_ADDR,
72 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
73 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
74 unsigned short t = bcsr_read(BCSR_HEXLEDS);
75 bcsr_write(BCSR_HEXLEDS, ~t);
76 if (bcsr_read(BCSR_HEXLEDS) != t) {
77 bcsr_write(BCSR_HEXLEDS, t);
78 return 0;
79 }
80 }
81
82 /* okay, try the PB1200 then */
83 bcsr_init(PB1200_BCSR_PHYS_ADDR,
84 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
85 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
86 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
87 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
88 unsigned short t = bcsr_read(BCSR_HEXLEDS);
89 bcsr_write(BCSR_HEXLEDS, ~t);
90 if (bcsr_read(BCSR_HEXLEDS) != t) {
91 bcsr_write(BCSR_HEXLEDS, t);
92 return 0;
93 }
94 }
95
96 return 1; /* it's neither */
97 }
98
99 void __init board_setup(void)
100 {
101 unsigned long freq0, clksrc, div, pfc;
102 unsigned short whoami;
103
104 if (detect_board()) {
105 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n");
106 return;
107 }
108
109 whoami = bcsr_read(BCSR_WHOAMI);
110 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
111 " Board-ID %d Daughtercard ID %d\n", board_type_str(),
112 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
113
114 /* SMBus/SPI on PSC0, Audio on PSC1 */
115 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
116 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
117 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
118 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
119 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
120 wmb();
121
122 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
123 * CPU clock; all other clock generators off/unused.
124 */
125 div = (get_au1x00_speed() + 25000000) / 50000000;
126 if (div & 1)
127 div++;
128 div = ((div >> 1) - 1) & 0xff;
129
130 freq0 = div << SYS_FC_FRDIV0_BIT;
131 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
132 wmb();
133 freq0 |= SYS_FC_FE0; /* enable F0 */
134 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
135 wmb();
136
137 /* psc0_intclk comes 1:1 from F0 */
138 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
139 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
140 wmb();
141 }
142
143 /******************************************************************************/
144
145 static struct mtd_partition db1200_spiflash_parts[] = {
146 {
147 .name = "spi_flash",
148 .offset = 0,
149 .size = MTDPART_SIZ_FULL,
150 },
151 };
152
153 static struct flash_platform_data db1200_spiflash_data = {
154 .name = "s25fl001",
155 .parts = db1200_spiflash_parts,
156 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
157 .type = "m25p10",
158 };
159
160 static struct spi_board_info db1200_spi_devs[] __initdata = {
161 {
162 /* TI TMP121AIDBVR temp sensor */
163 .modalias = "tmp121",
164 .max_speed_hz = 2000000,
165 .bus_num = 0,
166 .chip_select = 0,
167 .mode = 0,
168 },
169 {
170 /* Spansion S25FL001D0FMA SPI flash */
171 .modalias = "m25p80",
172 .max_speed_hz = 50000000,
173 .bus_num = 0,
174 .chip_select = 1,
175 .mode = 0,
176 .platform_data = &db1200_spiflash_data,
177 },
178 };
179
180 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
181 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
182 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
183 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
184 };
185
186 /**********************************************************************/
187
188 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
189 unsigned int ctrl)
190 {
191 struct nand_chip *this = mtd->priv;
192 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
193
194 ioaddr &= 0xffffff00;
195
196 if (ctrl & NAND_CLE) {
197 ioaddr += MEM_STNAND_CMD;
198 } else if (ctrl & NAND_ALE) {
199 ioaddr += MEM_STNAND_ADDR;
200 } else {
201 /* assume we want to r/w real data by default */
202 ioaddr += MEM_STNAND_DATA;
203 }
204 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
205 if (cmd != NAND_CMD_NONE) {
206 __raw_writeb(cmd, this->IO_ADDR_W);
207 wmb();
208 }
209 }
210
211 static int au1200_nand_device_ready(struct mtd_info *mtd)
212 {
213 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
214 }
215
216 static struct mtd_partition db1200_nand_parts[] = {
217 {
218 .name = "NAND FS 0",
219 .offset = 0,
220 .size = 8 * 1024 * 1024,
221 },
222 {
223 .name = "NAND FS 1",
224 .offset = MTDPART_OFS_APPEND,
225 .size = MTDPART_SIZ_FULL
226 },
227 };
228
229 struct platform_nand_data db1200_nand_platdata = {
230 .chip = {
231 .nr_chips = 1,
232 .chip_offset = 0,
233 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
234 .partitions = db1200_nand_parts,
235 .chip_delay = 20,
236 },
237 .ctrl = {
238 .dev_ready = au1200_nand_device_ready,
239 .cmd_ctrl = au1200_nand_cmd_ctrl,
240 },
241 };
242
243 static struct resource db1200_nand_res[] = {
244 [0] = {
245 .start = DB1200_NAND_PHYS_ADDR,
246 .end = DB1200_NAND_PHYS_ADDR + 0xff,
247 .flags = IORESOURCE_MEM,
248 },
249 };
250
251 static struct platform_device db1200_nand_dev = {
252 .name = "gen_nand",
253 .num_resources = ARRAY_SIZE(db1200_nand_res),
254 .resource = db1200_nand_res,
255 .id = -1,
256 .dev = {
257 .platform_data = &db1200_nand_platdata,
258 }
259 };
260
261 /**********************************************************************/
262
263 static struct smc91x_platdata db1200_eth_data = {
264 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
265 .leda = RPC_LED_100_10,
266 .ledb = RPC_LED_TX_RX,
267 };
268
269 static struct resource db1200_eth_res[] = {
270 [0] = {
271 .start = DB1200_ETH_PHYS_ADDR,
272 .end = DB1200_ETH_PHYS_ADDR + 0xf,
273 .flags = IORESOURCE_MEM,
274 },
275 [1] = {
276 .start = DB1200_ETH_INT,
277 .end = DB1200_ETH_INT,
278 .flags = IORESOURCE_IRQ,
279 },
280 };
281
282 static struct platform_device db1200_eth_dev = {
283 .dev = {
284 .platform_data = &db1200_eth_data,
285 },
286 .name = "smc91x",
287 .id = -1,
288 .num_resources = ARRAY_SIZE(db1200_eth_res),
289 .resource = db1200_eth_res,
290 };
291
292 /**********************************************************************/
293
294 static struct resource db1200_ide_res[] = {
295 [0] = {
296 .start = DB1200_IDE_PHYS_ADDR,
297 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = DB1200_IDE_INT,
302 .end = DB1200_IDE_INT,
303 .flags = IORESOURCE_IRQ,
304 },
305 [2] = {
306 .start = AU1200_DSCR_CMD0_DMA_REQ1,
307 .end = AU1200_DSCR_CMD0_DMA_REQ1,
308 .flags = IORESOURCE_DMA,
309 },
310 };
311
312 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
313
314 static struct platform_device db1200_ide_dev = {
315 .name = "au1200-ide",
316 .id = 0,
317 .dev = {
318 .dma_mask = &au1200_ide_dmamask,
319 .coherent_dma_mask = DMA_BIT_MASK(32),
320 },
321 .num_resources = ARRAY_SIZE(db1200_ide_res),
322 .resource = db1200_ide_res,
323 };
324
325 /**********************************************************************/
326
327 /* SD carddetects: they're supposed to be edge-triggered, but ack
328 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
329 * is disabled and its counterpart enabled. The 500ms timeout is
330 * because the carddetect isn't debounced in hardware.
331 */
332 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
333 {
334 void(*mmc_cd)(struct mmc_host *, unsigned long);
335
336 if (irq == DB1200_SD0_INSERT_INT) {
337 disable_irq_nosync(DB1200_SD0_INSERT_INT);
338 enable_irq(DB1200_SD0_EJECT_INT);
339 } else {
340 disable_irq_nosync(DB1200_SD0_EJECT_INT);
341 enable_irq(DB1200_SD0_INSERT_INT);
342 }
343
344 /* link against CONFIG_MMC=m */
345 mmc_cd = symbol_get(mmc_detect_change);
346 if (mmc_cd) {
347 mmc_cd(ptr, msecs_to_jiffies(500));
348 symbol_put(mmc_detect_change);
349 }
350
351 return IRQ_HANDLED;
352 }
353
354 static int db1200_mmc_cd_setup(void *mmc_host, int en)
355 {
356 int ret;
357
358 if (en) {
359 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
360 0, "sd_insert", mmc_host);
361 if (ret)
362 goto out;
363
364 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
365 0, "sd_eject", mmc_host);
366 if (ret) {
367 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
368 goto out;
369 }
370
371 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
372 enable_irq(DB1200_SD0_EJECT_INT);
373 else
374 enable_irq(DB1200_SD0_INSERT_INT);
375
376 } else {
377 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
378 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
379 }
380 ret = 0;
381 out:
382 return ret;
383 }
384
385 static void db1200_mmc_set_power(void *mmc_host, int state)
386 {
387 if (state) {
388 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
389 msleep(400); /* stabilization time */
390 } else
391 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
392 }
393
394 static int db1200_mmc_card_readonly(void *mmc_host)
395 {
396 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
397 }
398
399 static int db1200_mmc_card_inserted(void *mmc_host)
400 {
401 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
402 }
403
404 static void db1200_mmcled_set(struct led_classdev *led,
405 enum led_brightness brightness)
406 {
407 if (brightness != LED_OFF)
408 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
409 else
410 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
411 }
412
413 static struct led_classdev db1200_mmc_led = {
414 .brightness_set = db1200_mmcled_set,
415 };
416
417 /* -- */
418
419 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
420 {
421 void(*mmc_cd)(struct mmc_host *, unsigned long);
422
423 if (irq == PB1200_SD1_INSERT_INT) {
424 disable_irq_nosync(PB1200_SD1_INSERT_INT);
425 enable_irq(PB1200_SD1_EJECT_INT);
426 } else {
427 disable_irq_nosync(PB1200_SD1_EJECT_INT);
428 enable_irq(PB1200_SD1_INSERT_INT);
429 }
430
431 /* link against CONFIG_MMC=m */
432 mmc_cd = symbol_get(mmc_detect_change);
433 if (mmc_cd) {
434 mmc_cd(ptr, msecs_to_jiffies(500));
435 symbol_put(mmc_detect_change);
436 }
437
438 return IRQ_HANDLED;
439 }
440
441 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
442 {
443 int ret;
444
445 if (en) {
446 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
447 "sd1_insert", mmc_host);
448 if (ret)
449 goto out;
450
451 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
452 "sd1_eject", mmc_host);
453 if (ret) {
454 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
455 goto out;
456 }
457
458 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
459 enable_irq(PB1200_SD1_EJECT_INT);
460 else
461 enable_irq(PB1200_SD1_INSERT_INT);
462
463 } else {
464 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
465 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
466 }
467 ret = 0;
468 out:
469 return ret;
470 }
471
472 static void pb1200_mmc1led_set(struct led_classdev *led,
473 enum led_brightness brightness)
474 {
475 if (brightness != LED_OFF)
476 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
477 else
478 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
479 }
480
481 static struct led_classdev pb1200_mmc1_led = {
482 .brightness_set = pb1200_mmc1led_set,
483 };
484
485 static void pb1200_mmc1_set_power(void *mmc_host, int state)
486 {
487 if (state) {
488 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
489 msleep(400); /* stabilization time */
490 } else
491 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
492 }
493
494 static int pb1200_mmc1_card_readonly(void *mmc_host)
495 {
496 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
497 }
498
499 static int pb1200_mmc1_card_inserted(void *mmc_host)
500 {
501 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
502 }
503
504
505 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
506 [0] = {
507 .cd_setup = db1200_mmc_cd_setup,
508 .set_power = db1200_mmc_set_power,
509 .card_inserted = db1200_mmc_card_inserted,
510 .card_readonly = db1200_mmc_card_readonly,
511 .led = &db1200_mmc_led,
512 },
513 [1] = {
514 .cd_setup = pb1200_mmc1_cd_setup,
515 .set_power = pb1200_mmc1_set_power,
516 .card_inserted = pb1200_mmc1_card_inserted,
517 .card_readonly = pb1200_mmc1_card_readonly,
518 .led = &pb1200_mmc1_led,
519 },
520 };
521
522 static struct resource au1200_mmc0_resources[] = {
523 [0] = {
524 .start = AU1100_SD0_PHYS_ADDR,
525 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
526 .flags = IORESOURCE_MEM,
527 },
528 [1] = {
529 .start = AU1200_SD_INT,
530 .end = AU1200_SD_INT,
531 .flags = IORESOURCE_IRQ,
532 },
533 [2] = {
534 .start = AU1200_DSCR_CMD0_SDMS_TX0,
535 .end = AU1200_DSCR_CMD0_SDMS_TX0,
536 .flags = IORESOURCE_DMA,
537 },
538 [3] = {
539 .start = AU1200_DSCR_CMD0_SDMS_RX0,
540 .end = AU1200_DSCR_CMD0_SDMS_RX0,
541 .flags = IORESOURCE_DMA,
542 }
543 };
544
545 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
546
547 static struct platform_device db1200_mmc0_dev = {
548 .name = "au1xxx-mmc",
549 .id = 0,
550 .dev = {
551 .dma_mask = &au1xxx_mmc_dmamask,
552 .coherent_dma_mask = DMA_BIT_MASK(32),
553 .platform_data = &db1200_mmc_platdata[0],
554 },
555 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
556 .resource = au1200_mmc0_resources,
557 };
558
559 static struct resource au1200_mmc1_res[] = {
560 [0] = {
561 .start = AU1100_SD1_PHYS_ADDR,
562 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
563 .flags = IORESOURCE_MEM,
564 },
565 [1] = {
566 .start = AU1200_SD_INT,
567 .end = AU1200_SD_INT,
568 .flags = IORESOURCE_IRQ,
569 },
570 [2] = {
571 .start = AU1200_DSCR_CMD0_SDMS_TX1,
572 .end = AU1200_DSCR_CMD0_SDMS_TX1,
573 .flags = IORESOURCE_DMA,
574 },
575 [3] = {
576 .start = AU1200_DSCR_CMD0_SDMS_RX1,
577 .end = AU1200_DSCR_CMD0_SDMS_RX1,
578 .flags = IORESOURCE_DMA,
579 }
580 };
581
582 static struct platform_device pb1200_mmc1_dev = {
583 .name = "au1xxx-mmc",
584 .id = 1,
585 .dev = {
586 .dma_mask = &au1xxx_mmc_dmamask,
587 .coherent_dma_mask = DMA_BIT_MASK(32),
588 .platform_data = &db1200_mmc_platdata[1],
589 },
590 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
591 .resource = au1200_mmc1_res,
592 };
593
594 /**********************************************************************/
595
596 static int db1200fb_panel_index(void)
597 {
598 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
599 }
600
601 static int db1200fb_panel_init(void)
602 {
603 /* Apply power */
604 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
605 BCSR_BOARD_LCDBL);
606 return 0;
607 }
608
609 static int db1200fb_panel_shutdown(void)
610 {
611 /* Remove power */
612 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
613 BCSR_BOARD_LCDBL, 0);
614 return 0;
615 }
616
617 static struct au1200fb_platdata db1200fb_pd = {
618 .panel_index = db1200fb_panel_index,
619 .panel_init = db1200fb_panel_init,
620 .panel_shutdown = db1200fb_panel_shutdown,
621 };
622
623 static struct resource au1200_lcd_res[] = {
624 [0] = {
625 .start = AU1200_LCD_PHYS_ADDR,
626 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
627 .flags = IORESOURCE_MEM,
628 },
629 [1] = {
630 .start = AU1200_LCD_INT,
631 .end = AU1200_LCD_INT,
632 .flags = IORESOURCE_IRQ,
633 }
634 };
635
636 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
637
638 static struct platform_device au1200_lcd_dev = {
639 .name = "au1200-lcd",
640 .id = 0,
641 .dev = {
642 .dma_mask = &au1200_lcd_dmamask,
643 .coherent_dma_mask = DMA_BIT_MASK(32),
644 .platform_data = &db1200fb_pd,
645 },
646 .num_resources = ARRAY_SIZE(au1200_lcd_res),
647 .resource = au1200_lcd_res,
648 };
649
650 /**********************************************************************/
651
652 static struct resource au1200_psc0_res[] = {
653 [0] = {
654 .start = AU1550_PSC0_PHYS_ADDR,
655 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
656 .flags = IORESOURCE_MEM,
657 },
658 [1] = {
659 .start = AU1200_PSC0_INT,
660 .end = AU1200_PSC0_INT,
661 .flags = IORESOURCE_IRQ,
662 },
663 [2] = {
664 .start = AU1200_DSCR_CMD0_PSC0_TX,
665 .end = AU1200_DSCR_CMD0_PSC0_TX,
666 .flags = IORESOURCE_DMA,
667 },
668 [3] = {
669 .start = AU1200_DSCR_CMD0_PSC0_RX,
670 .end = AU1200_DSCR_CMD0_PSC0_RX,
671 .flags = IORESOURCE_DMA,
672 },
673 };
674
675 static struct platform_device db1200_i2c_dev = {
676 .name = "au1xpsc_smbus",
677 .id = 0, /* bus number */
678 .num_resources = ARRAY_SIZE(au1200_psc0_res),
679 .resource = au1200_psc0_res,
680 };
681
682 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
683 {
684 if (cs)
685 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
686 else
687 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
688 }
689
690 static struct au1550_spi_info db1200_spi_platdata = {
691 .mainclk_hz = 50000000, /* PSC0 clock */
692 .num_chipselect = 2,
693 .activate_cs = db1200_spi_cs_en,
694 };
695
696 static u64 spi_dmamask = DMA_BIT_MASK(32);
697
698 static struct platform_device db1200_spi_dev = {
699 .dev = {
700 .dma_mask = &spi_dmamask,
701 .coherent_dma_mask = DMA_BIT_MASK(32),
702 .platform_data = &db1200_spi_platdata,
703 },
704 .name = "au1550-spi",
705 .id = 0, /* bus number */
706 .num_resources = ARRAY_SIZE(au1200_psc0_res),
707 .resource = au1200_psc0_res,
708 };
709
710 static struct resource au1200_psc1_res[] = {
711 [0] = {
712 .start = AU1550_PSC1_PHYS_ADDR,
713 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
714 .flags = IORESOURCE_MEM,
715 },
716 [1] = {
717 .start = AU1200_PSC1_INT,
718 .end = AU1200_PSC1_INT,
719 .flags = IORESOURCE_IRQ,
720 },
721 [2] = {
722 .start = AU1200_DSCR_CMD0_PSC1_TX,
723 .end = AU1200_DSCR_CMD0_PSC1_TX,
724 .flags = IORESOURCE_DMA,
725 },
726 [3] = {
727 .start = AU1200_DSCR_CMD0_PSC1_RX,
728 .end = AU1200_DSCR_CMD0_PSC1_RX,
729 .flags = IORESOURCE_DMA,
730 },
731 };
732
733 /* AC97 or I2S device */
734 static struct platform_device db1200_audio_dev = {
735 /* name assigned later based on switch setting */
736 .id = 1, /* PSC ID */
737 .num_resources = ARRAY_SIZE(au1200_psc1_res),
738 .resource = au1200_psc1_res,
739 };
740
741 /* DB1200 ASoC card device */
742 static struct platform_device db1200_sound_dev = {
743 /* name assigned later based on switch setting */
744 .id = 1, /* PSC ID */
745 };
746
747 static struct platform_device db1200_stac_dev = {
748 .name = "ac97-codec",
749 .id = 1, /* on PSC1 */
750 };
751
752 static struct platform_device db1200_audiodma_dev = {
753 .name = "au1xpsc-pcm",
754 .id = 1, /* PSC ID */
755 };
756
757 static struct platform_device *db1200_devs[] __initdata = {
758 NULL, /* PSC0, selected by S6.8 */
759 &db1200_ide_dev,
760 &db1200_mmc0_dev,
761 &au1200_lcd_dev,
762 &db1200_eth_dev,
763 &db1200_nand_dev,
764 &db1200_audiodma_dev,
765 &db1200_audio_dev,
766 &db1200_stac_dev,
767 &db1200_sound_dev,
768 };
769
770 static struct platform_device *pb1200_devs[] __initdata = {
771 &pb1200_mmc1_dev,
772 };
773
774 /* Some peripheral base addresses differ on the PB1200 */
775 static int __init pb1200_res_fixup(void)
776 {
777 /* CPLD Revs earlier than 4 cause problems */
778 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
779 printk(KERN_ERR "WARNING!!!\n");
780 printk(KERN_ERR "WARNING!!!\n");
781 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
782 printk(KERN_ERR "the board updated to latest revisions.\n");
783 printk(KERN_ERR "This software will not work reliably\n");
784 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
785 printk(KERN_ERR "WARNING!!!\n");
786 printk(KERN_ERR "WARNING!!!\n");
787 return 1;
788 }
789
790 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
791 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
792 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
793 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
794 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
795 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
796 return 0;
797 }
798
799 static int __init db1200_dev_init(void)
800 {
801 unsigned long pfc;
802 unsigned short sw;
803 int swapped, bid;
804
805 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
806 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
807 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
808 if (pb1200_res_fixup())
809 return -ENODEV;
810 }
811
812 /* GPIO7 is low-level triggered CPLD cascade */
813 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
814 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
815
816 /* insert/eject pairs: one of both is always screaming. To avoid
817 * issues they must not be automatically enabled when initially
818 * requested.
819 */
820 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
821 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
822 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
823 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
824 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
825 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
826
827 i2c_register_board_info(0, db1200_i2c_devs,
828 ARRAY_SIZE(db1200_i2c_devs));
829 spi_register_board_info(db1200_spi_devs,
830 ARRAY_SIZE(db1200_i2c_devs));
831
832 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
833 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
834 * or S12 on the PB1200.
835 */
836
837 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
838 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
839 * allow to free it without crippling the SPI interface).
840 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
841 * it as an input pin which is pulled high on the boards).
842 */
843 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
844
845 /* switch off OTG VBUS supply */
846 gpio_request(215, "otg-vbus");
847 gpio_direction_output(215, 1);
848
849 printk(KERN_INFO "%s device configuration:\n", board_type_str());
850
851 sw = bcsr_read(BCSR_SWITCHES);
852 if (sw & BCSR_SWITCHES_DIP_8) {
853 db1200_devs[0] = &db1200_i2c_dev;
854 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
855
856 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
857
858 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
859 printk(KERN_INFO " OTG port VBUS supply available!\n");
860 } else {
861 db1200_devs[0] = &db1200_spi_dev;
862 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
863
864 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
865
866 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
867 printk(KERN_INFO " OTG port VBUS supply disabled\n");
868 }
869 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
870 wmb();
871
872 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
873 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
874 */
875 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
876 if (sw == BCSR_SWITCHES_DIP_8) {
877 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
878 db1200_audio_dev.name = "au1xpsc_i2s";
879 db1200_sound_dev.name = "db1200-i2s";
880 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
881 } else {
882 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
883 db1200_audio_dev.name = "au1xpsc_ac97";
884 db1200_sound_dev.name = "db1200-ac97";
885 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
886 }
887
888 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
889 __raw_writel(PSC_SEL_CLK_SERCLK,
890 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
891 wmb();
892
893 db1x_register_pcmcia_socket(
894 AU1000_PCMCIA_ATTR_PHYS_ADDR,
895 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
896 AU1000_PCMCIA_MEM_PHYS_ADDR,
897 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
898 AU1000_PCMCIA_IO_PHYS_ADDR,
899 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
900 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
901 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
902
903 db1x_register_pcmcia_socket(
904 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
905 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
906 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
907 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
908 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
909 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
910 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
911 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
912
913 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
914 db1x_register_norflash(64 << 20, 2, swapped);
915
916 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
917
918 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
919 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
920 (bid == BCSR_WHOAMI_PB1200_DDR2))
921 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
922
923 return 0;
924 }
925 device_initcall(db1200_dev_init);
Linux with added FPC-III support