arch/x86/kernel/acpi/cstate.c

   1 /*
   2  * Copyright (C) 2005 Intel Corporation
   3  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
   4  *      - Added _PDC for SMP C-states on Intel CPUs
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/acpi.h>
  11 #include <linux/cpu.h>
  12 #include <linux/sched.h>
  13
  14 #include <acpi/processor.h>
  15 #include <asm/acpi.h>
  16 #include <asm/mwait.h>
  17 #include <asm/special_insns.h>
  18
  19 /*
  20  * Initialize bm_flags based on the CPU cache properties
  21  * On SMP it depends on cache configuration
  22  * - When cache is not shared among all CPUs, we flush cache
  23  *   before entering C3.
  24  * - When cache is shared among all CPUs, we use bm_check
  25  *   mechanism as in UP case
  26  *
  27  * This routine is called only after all the CPUs are online
  28  */
  29 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
  30                                         unsigned int cpu)
  31 {
  32         struct cpuinfo_x86 *c = &cpu_data(cpu);
  33
  34         flags->bm_check = 0;
  35         if (num_online_cpus() == 1)
  36                 flags->bm_check = 1;
  37         else if (c->x86_vendor == X86_VENDOR_INTEL) {
  38                 /*
  39                  * Today all MP CPUs that support C3 share cache.
  40                  * And caches should not be flushed by software while
  41                  * entering C3 type state.
  42                  */
  43                 flags->bm_check = 1;
  44         }
  45
  46         /*
  47          * On all recent Intel platforms, ARB_DISABLE is a nop.
  48          * So, set bm_control to zero to indicate that ARB_DISABLE
  49          * is not required while entering C3 type state on
  50          * P4, Core and beyond CPUs
  51          */
  52         if (c->x86_vendor == X86_VENDOR_INTEL &&
  53             (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
  54                         flags->bm_control = 0;
  55 }
  56 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
  57
  58 /* The code below handles cstate entry with monitor-mwait pair on Intel*/
  59
  60 struct cstate_entry {
  61         struct {
  62                 unsigned int eax;
  63                 unsigned int ecx;
  64         } states[ACPI_PROCESSOR_MAX_POWER];
  65 };
  66 static struct cstate_entry __percpu *cpu_cstate_entry;  /* per CPU ptr */
  67
  68 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
  69
  70 #define NATIVE_CSTATE_BEYOND_HALT       (2)
  71
  72 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
  73 {
  74         struct acpi_processor_cx *cx = _cx;
  75         long retval;
  76         unsigned int eax, ebx, ecx, edx;
  77         unsigned int edx_part;
  78         unsigned int cstate_type; /* C-state type and not ACPI C-state type */
  79         unsigned int num_cstate_subtype;
  80
  81         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
  82
  83         /* Check whether this particular cx_type (in CST) is supported or not */
  84         cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
  85                         MWAIT_CSTATE_MASK) + 1;
  86         edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
  87         num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
  88
  89         retval = 0;
  90         if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
  91                 retval = -1;
  92                 goto out;
  93         }
  94
  95         /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
  96         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
  97             !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
  98                 retval = -1;
  99                 goto out;
 100         }
 101
 102         if (!mwait_supported[cstate_type]) {
 103                 mwait_supported[cstate_type] = 1;
 104                 printk(KERN_DEBUG
 105                         "Monitor-Mwait will be used to enter C-%d "
 106                         "state\n", cx->type);
 107         }
 108         snprintf(cx->desc,
 109                         ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
 110                         cx->address);
 111 out:
 112         return retval;
 113 }
 114
 115 int acpi_processor_ffh_cstate_probe(unsigned int cpu,
 116                 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
 117 {
 118         struct cstate_entry *percpu_entry;
 119         struct cpuinfo_x86 *c = &cpu_data(cpu);
 120         long retval;
 121
 122         if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
 123                 return -1;
 124
 125         if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
 126                 return -1;
 127
 128         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
 129         percpu_entry->states[cx->index].eax = 0;
 130         percpu_entry->states[cx->index].ecx = 0;
 131
 132         /* Make sure we are running on right CPU */
 133
 134         retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
 135         if (retval == 0) {
 136                 /* Use the hint in CST */
 137                 percpu_entry->states[cx->index].eax = cx->address;
 138                 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
 139         }
 140
 141         /*
 142          * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
 143          * then we should skip checking BM_STS for this C-state.
 144          * ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
 145          */
 146         if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
 147                 cx->bm_sts_skip = 1;
 148
 149         return retval;
 150 }
 151 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
 152
 153 /*
 154  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 155  * which can obviate IPI to trigger checking of need_resched.
 156  * We execute MONITOR against need_resched and enter optimized wait state
 157  * through MWAIT. Whenever someone changes need_resched, we would be woken
 158  * up from MWAIT (without an IPI).
 159  *
 160  * New with Core Duo processors, MWAIT can take some hints based on CPU
 161  * capability.
 162  */
 163 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 164 {
 165         if (!need_resched()) {
 166                 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
 167                         clflush((void *)&current_thread_info()->flags);
 168
 169                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 170                 smp_mb();
 171                 if (!need_resched())
 172                         __mwait(ax, cx);
 173         }
 174 }
 175
 176 void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
 177 {
 178         unsigned int cpu = smp_processor_id();
 179         struct cstate_entry *percpu_entry;
 180
 181         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
 182         mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
 183                               percpu_entry->states[cx->index].ecx);
 184 }
 185 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
 186
 187 static int __init ffh_cstate_init(void)
 188 {
 189         struct cpuinfo_x86 *c = &boot_cpu_data;
 190         if (c->x86_vendor != X86_VENDOR_INTEL)
 191                 return -1;
 192
 193         cpu_cstate_entry = alloc_percpu(struct cstate_entry);
 194         return 0;
 195 }
 196
 197 static void __exit ffh_cstate_exit(void)
 198 {
 199         free_percpu(cpu_cstate_entry);
 200         cpu_cstate_entry = NULL;
 201 }
 202
 203 arch_initcall(ffh_cstate_init);
 204 __exitcall(ffh_cstate_exit);